FPGA可编程逻辑器件芯片XC2V6000-4FG256I中文规格书-USB迷|专注于互联网分享

2024年10月28日发(作者：昂英杰)

Feature Descriptions

SGMII GTX Transceiver Clock Generation

[Figure1-2, callout 16]

An Integrated Circuit Systems ICS844021I chip (U2) generates a high-quality, low-jitter, 125MHz

LVDS clock from a 25MHz crystal (X3). This clock is sent to FPGA U1, Bank 113 GTX

transceiver (clock pins AH8 (P) and AH7 (N)) driving the SGMII interface. Series AC coupling

capacitors are present to allow the clock input of the FPGA to set the common mode voltage.

Figure1-17 shows the Ethernet SGMII clock source.

C300

18pF 50V

NPO

VDDA_SGMIICLKVDD_SGMIICLK

25.00 MHz

SGMIICLK_XTAL_OUT

ICS844021I-01

Clock Generator

VDDA

XTAL_OUT

VDD

SGMIICLK_Q0_C_P

R320

1.0MΩ 5%

C301

18pF 50V

NPO

GND2

C28

0.1μF 25V

X5R

SGMIICLK_Q0_P

GND2X2

SGMIICLK_XTAL_IN

XTAL_IN

GND

NQ0

SGMIICLK_Q0_C_NSGMIICLK_Q0_N

C29

0.1μF 25V

X5R

UG885_c1_17_020612

GND_SGMIICLKGND_SGMIICLK

GND_SGMIICLK

Figure 1-17:Ethernet 125 MHz SGMII GTX Clock

References

Details about the tri-mode Ethernet MAC core are provided in LogiCORE IP Tri-Mode Ethernet

MAC Product Guide for Vivado Design Suite (PG051) [Ref9] and in the LogiCORE IP Tri-Mode

Ethernet MAC v4.5 User Guide (UG138) [Ref13].

The product brief for the Marvell 88E1111 Alaska Gigabit Ethernet Transceiver can be found at the

Marvell website [Ref21].

The data sheet can be obtained under NDA with Marvell. Contact information is at the Marvell

website [Ref21].

For more information about the ICS844021 device, go to the Integrated Device Technology website

[Ref22] and search for part number ICS844021.

USB-to-UART Bridge

[Figure1-2, callout 17]

The VC707 board contains a Silicon Labs CP2103GM USB-to-UART bridge device (U44) which

allows a connection to a host computer with a USB port. The USB cable is supplied in the VC707

Evaluation Kit (Type-A end to host computer, Type mini-B end to VC707 board connector J17). The

CP2103GM is powered by the USB 5V provided by the host PC when the USB cable is plugged into

the USB port on the VC707 board.

Xilinx UART IP is expected to be implemented in the FPGA logic. The FPGA supports the

USB-to-UART bridge using four signal pins: Transmit (TX), Receive (RX), Request to Send (RTS),

and Clear to Send (CTS).

Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers for the host computer. These

drivers permit the CP2103GM USB-to-UART bridge to appear as a COM port to communications

application software (for example, TeraTerm) that runs on the host computer. The VCP device

VC707 Evaluation Board

UG885 (v1.8) February 20, 2019

Feature Descriptions

User SMA

Figure1-28 shows the user SMA circuit.

J33

SMA

Connector

USER SMA GPIO P

GND

J34

SMA

Connector

USER SMA GPIO N

GND

UG885_c1_126_012413

Figure 1-28:User SMA

Table1-26 lists the GPIO Connections to FPGA U1.

Table 1-26:GPIO Connections to FPGA U1

Schematic Net NameI/O StandardGPIO PinFPGA (U1) Pin

Indicator LEDs (Active-High)

AM39

AN39

AR37

AT37

AR35

AP41

AP42

AU39

GPIO_LED_0

GPIO_LED_1

GPIO_LED_2

GPIO_LED_3

GPIO_LED_4

GPIO_LED_5

GPIO_LED_6

GPIO_LED_7

LVCMOS18

DS2.2

DS3.2

DS4.2

DS5.2

DS6.2

DS7.2

DS8.2

DS9.2

CPU Reset Pushbutton Switch

AV40CPU_RESETLVCMOS18SW8.3

Directional Pushbutton Switches

AR40

AU38

AP40

GPIO_SW_N

GPIO_SW_E

GPIO_SW_S

LVCMOS18

SW3.3

SW4.3

SW5.3

VC707 Evaluation Board

UG885 (v1.8) February 20, 2019

Chapter 1:VC707 Evaluation Board Features

Table 1-28:J37 VITA 57.1 FMC 2 HPC Connections (Cont’d)

I/O U1 FPGA

StandardPin

LVCMOS18

AD32

AD33

Y32

Y33

AE29

AE30

AE32

AE33

AG36

AH36

AD36

AD37

AT16

AU16

BA17

BB17

AV20

AW20

AT20

AT19

AP18

AP17

AN19

AN18

J37

FMC 2

Schematic Net Name

HPC

E10

E12

E13

E15

E16

E18

E19

E21

E22

E24

E25

E27

E28

E30

E31

E33

E34

E36

E37

E39

FMC2_HPC_HA01_CC_P

FMC2_HPC_HA01_CC_N

FMC2_HPC_HA05_P

FMC2_HPC_HA05_N

FMC2_HPC_HA09_P

FMC2_HPC_HA09_N

FMC2_HPC_HA13_P

FMC2_HPC_HA13_N

FMC2_HPC_HA16_P

FMC2_HPC_HA16_N

FMC2_HPC_HA20_P

FMC2_HPC_HA20_N

FMC2_HPC_HB03_P

FMC2_HPC_HB03_N

FMC2_HPC_HB05_P

FMC2_HPC_HB05_N

FMC2_HPC_HB09_P

FMC2_HPC_HB09_N

FMC2_HPC_HB13_P

FMC2_HPC_HB13_N

FMC2_HPC_HB19_P

FMC2_HPC_HB19_N

FMC2_HPC_HB21_P

FMC2_HPC_HB21_N

VADJ

J37

FMC 2

HPC

F10

F11

F13

F14

F16

F17

F19

F20

F22

F23

F25

F26

F28

F29

F31

F32

F34

F35

F37

F38

F40

Schematic Net Name

I/O U1 FPGA

StandardPin

LVCMOS18

AF29

AB33

AC33

AB29

AC29

AA31

AA32

AF34

AG34

AE37

AF37

AC35

AC36

AV16

AW16

AU18

AV18

AY20

BA20

AU19

AV19

AR18

AR17

AK17

AL17

FMC2_HPC_PG_M2C

FMC2_HPC_HA00_CC_P

FMC2_HPC_HA00_CC_N

FMC2_HPC_HA04_P

FMC2_HPC_HA04_N

FMC2_HPC_HA08_P

FMC2_HPC_HA08_N

FMC2_HPC_HA12_P

FMC2_HPC_HA12_N

FMC2_HPC_HA15_P

FMC2_HPC_HA15_N

FMC2_HPC_HA19_P

FMC2_HPC_HA19_N

FMC2_HPC_HB02_P

FMC2_HPC_HB02_N

FMC2_HPC_HB04_P

FMC2_HPC_HB04_N

FMC2_HPC_HB08_P

FMC2_HPC_HB08_N

FMC2_HPC_HB12_P

FMC2_HPC_HB12_N

FMC2_HPC_HB16_P

FMC2_HPC_HB16_N

FMC2_HPC_HB20_P

FMC2_HPC_HB20_N

VADJ

VC707 Evaluation Board

UG885 (v1.8) February 20, 2019

Chapter 1:VC707 Evaluation Board Features

VC707 Evaluation Board

UG885 (v1.8) February 20, 2019

Appendix A:Default Switch and Jumper Settings

VC707 Evaluation Board

UG885 (v1.8) February 20, 2019

2024年10月28日发(作者：昂英杰)

Feature Descriptions

SGMII GTX Transceiver Clock Generation

[Figure1-2, callout 16]

An Integrated Circuit Systems ICS844021I chip (U2) generates a high-quality, low-jitter, 125MHz

LVDS clock from a 25MHz crystal (X3). This clock is sent to FPGA U1, Bank 113 GTX

transceiver (clock pins AH8 (P) and AH7 (N)) driving the SGMII interface. Series AC coupling

capacitors are present to allow the clock input of the FPGA to set the common mode voltage.

Figure1-17 shows the Ethernet SGMII clock source.

C300

18pF 50V

NPO

VDDA_SGMIICLKVDD_SGMIICLK

25.00 MHz

SGMIICLK_XTAL_OUT

ICS844021I-01

Clock Generator

VDDA

XTAL_OUT

VDD

SGMIICLK_Q0_C_P

R320

1.0MΩ 5%

C301

18pF 50V

NPO

GND2

C28

0.1μF 25V

X5R

SGMIICLK_Q0_P

GND2X2

SGMIICLK_XTAL_IN

XTAL_IN

GND

NQ0

SGMIICLK_Q0_C_NSGMIICLK_Q0_N

C29

0.1μF 25V

X5R

UG885_c1_17_020612

GND_SGMIICLKGND_SGMIICLK

GND_SGMIICLK

Figure 1-17:Ethernet 125 MHz SGMII GTX Clock

References

Details about the tri-mode Ethernet MAC core are provided in LogiCORE IP Tri-Mode Ethernet

MAC Product Guide for Vivado Design Suite (PG051) [Ref9] and in the LogiCORE IP Tri-Mode

Ethernet MAC v4.5 User Guide (UG138) [Ref13].

The product brief for the Marvell 88E1111 Alaska Gigabit Ethernet Transceiver can be found at the

Marvell website [Ref21].

The data sheet can be obtained under NDA with Marvell. Contact information is at the Marvell

website [Ref21].

For more information about the ICS844021 device, go to the Integrated Device Technology website

[Ref22] and search for part number ICS844021.

USB-to-UART Bridge

[Figure1-2, callout 17]

The VC707 board contains a Silicon Labs CP2103GM USB-to-UART bridge device (U44) which

allows a connection to a host computer with a USB port. The USB cable is supplied in the VC707

Evaluation Kit (Type-A end to host computer, Type mini-B end to VC707 board connector J17). The

CP2103GM is powered by the USB 5V provided by the host PC when the USB cable is plugged into

the USB port on the VC707 board.

Xilinx UART IP is expected to be implemented in the FPGA logic. The FPGA supports the

USB-to-UART bridge using four signal pins: Transmit (TX), Receive (RX), Request to Send (RTS),

and Clear to Send (CTS).

Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers for the host computer. These

drivers permit the CP2103GM USB-to-UART bridge to appear as a COM port to communications

application software (for example, TeraTerm) that runs on the host computer. The VCP device

VC707 Evaluation Board

UG885 (v1.8) February 20, 2019

Feature Descriptions

User SMA

Figure1-28 shows the user SMA circuit.

J33

SMA

Connector

USER SMA GPIO P

GND

J34

SMA

Connector

USER SMA GPIO N

GND

UG885_c1_126_012413

Figure 1-28:User SMA

Table1-26 lists the GPIO Connections to FPGA U1.

Table 1-26:GPIO Connections to FPGA U1

Schematic Net NameI/O StandardGPIO PinFPGA (U1) Pin

Indicator LEDs (Active-High)

AM39

AN39

AR37

AT37

AR35

AP41

AP42

AU39

GPIO_LED_0

GPIO_LED_1

GPIO_LED_2

GPIO_LED_3

GPIO_LED_4

GPIO_LED_5

GPIO_LED_6

GPIO_LED_7

LVCMOS18

DS2.2

DS3.2

DS4.2

DS5.2

DS6.2

DS7.2

DS8.2

DS9.2

CPU Reset Pushbutton Switch

AV40CPU_RESETLVCMOS18SW8.3

Directional Pushbutton Switches

AR40

AU38

AP40

GPIO_SW_N

GPIO_SW_E

GPIO_SW_S

LVCMOS18

SW3.3

SW4.3

SW5.3

VC707 Evaluation Board

UG885 (v1.8) February 20, 2019

Chapter 1:VC707 Evaluation Board Features

Table 1-28:J37 VITA 57.1 FMC 2 HPC Connections (Cont’d)

I/O U1 FPGA

StandardPin

LVCMOS18

AD32

AD33

Y32

Y33

AE29

AE30

AE32

AE33

AG36

AH36

AD36

AD37

AT16

AU16

BA17

BB17

AV20

AW20

AT20

AT19

AP18

AP17

AN19

AN18

J37

FMC 2

Schematic Net Name

HPC

E10

E12

E13

E15

E16

E18

E19

E21

E22

E24

E25

E27

E28

E30

E31

E33

E34

E36

E37

E39

FMC2_HPC_HA01_CC_P

FMC2_HPC_HA01_CC_N

FMC2_HPC_HA05_P

FMC2_HPC_HA05_N

FMC2_HPC_HA09_P

FMC2_HPC_HA09_N

FMC2_HPC_HA13_P

FMC2_HPC_HA13_N

FMC2_HPC_HA16_P

FMC2_HPC_HA16_N

FMC2_HPC_HA20_P

FMC2_HPC_HA20_N

FMC2_HPC_HB03_P

FMC2_HPC_HB03_N

FMC2_HPC_HB05_P

FMC2_HPC_HB05_N

FMC2_HPC_HB09_P

FMC2_HPC_HB09_N

FMC2_HPC_HB13_P

FMC2_HPC_HB13_N

FMC2_HPC_HB19_P

FMC2_HPC_HB19_N

FMC2_HPC_HB21_P

FMC2_HPC_HB21_N

VADJ

J37

FMC 2

HPC

F10

F11

F13

F14

F16

F17

F19

F20

F22

F23

F25

F26

F28

F29

F31

F32

F34

F35

F37

F38

F40

Schematic Net Name

I/O U1 FPGA

StandardPin

LVCMOS18

AF29

AB33

AC33

AB29

AC29

AA31

AA32

AF34

AG34

AE37

AF37

AC35

AC36

AV16

AW16

AU18

AV18

AY20

BA20

AU19

AV19

AR18

AR17

AK17

AL17

FMC2_HPC_PG_M2C

FMC2_HPC_HA00_CC_P

FMC2_HPC_HA00_CC_N

FMC2_HPC_HA04_P

FMC2_HPC_HA04_N

FMC2_HPC_HA08_P

FMC2_HPC_HA08_N

FMC2_HPC_HA12_P

FMC2_HPC_HA12_N

FMC2_HPC_HA15_P

FMC2_HPC_HA15_N

FMC2_HPC_HA19_P

FMC2_HPC_HA19_N

FMC2_HPC_HB02_P

FMC2_HPC_HB02_N

FMC2_HPC_HB04_P

FMC2_HPC_HB04_N

FMC2_HPC_HB08_P

FMC2_HPC_HB08_N

FMC2_HPC_HB12_P

FMC2_HPC_HB12_N

FMC2_HPC_HB16_P

FMC2_HPC_HB16_N

FMC2_HPC_HB20_P

FMC2_HPC_HB20_N

VADJ

VC707 Evaluation Board

UG885 (v1.8) February 20, 2019

Chapter 1:VC707 Evaluation Board Features

VC707 Evaluation Board

UG885 (v1.8) February 20, 2019

Appendix A:Default Switch and Jumper Settings

VC707 Evaluation Board

UG885 (v1.8) February 20, 2019

USB迷 | 专注于互联网分享

FPGA可编程逻辑器件芯片XC2V6000-4FG256I中文规格书

与本文相关的文章

评论列表 (0)