2024年2月20日发(作者：不语柳)
54321DDU1A(7)PCIE_REFCLKP(7)PCIE_REFCLKNPCIE_REFCLKPPCIE_REFCLKNPCIE_RXP0PCIE_RXN0PCIE_RXP1PCIE_RXN1PCIE_RXP2PCIE_RXN2PCIE_RXP3PCIE_RXN3PCIE_RXP4PCIE_RXN4PCIE_RXP5PCIE_RXN5PCIE_RXP6PCIE_RXN6PCIE_RXP7PCIE_RXN7PCIE_RXP8PCIE_RXN8PCIE_RXP9PCIE_RXN9PCIE_RXP10PCIE_RXN10PCIE_RXP11PCIE_RXN11PCIE_RXP12PCIE_RXN12PCIE_RXP13PCIE_RXN13PCIE_RXP14PCIE_RXN14PCIE_RXP15PCIE_RXN15AF30AE31AE29AD28AD30AC31AC29AB28AB30AA31AA29Y28Y30W31W29V28V30U31U29T28T30R31R29P28P30N31N29M28M30L31L29K30PCIE_RX0PPCIE_RX0NPCIE_RX1PPCIE_RX1NPCIE_RX2PPCIE_RX2NPCIE_RX3PPCIE_RX3NPCIE_RX4PPCIE_RX4NPCIE_RX5PPCIE_RX5NPCIE_RX6PPCIE_RX6NPCIE_RX7PPCIE_RX7NPCIE_RX8PPCIE_RX8NPCIE_RX9PPCIE_RX9NPCIE_RX10PPCIE_RX10NPCIE_RX11PPCIE_RX11NPCIE_RX12PPCIE_RX12NPCIE_RX13PPCIE_RX13NPCIE_RX14PPCIE_RX14NPCIE_RX15PPCIE_RX15NPCIE_TX0PPCIE_TX0NPCIE_TX1PPCIE_TX1NPCIE_TX2PPCIE_TX2NPCIE_TX3PPCIE_TX3NPCIE_TX4PPCIE_TX4NPCIE_TX5PPCIE_TX5NPCIE_TX6PPCIE_TX6NPCIE_TX7PPCIE_TX7NPCIE_TX8PPCIE_TX8NPCIE_TX9PPCIE_TX9NPCIE_TX10PPCIE_TX10NPCIE_TX11PPCIE_TX11NPCIE_TX12PPCIE_TX12NPCIE_TX13PPCIE_TX13NPCIE_TX14PPCIE_TX14NPCIE_TX15PPCIE_TX15NAH30AG31AG29AF28AF27AF26AD27AD26AC25AB25Y23Y24AB27AB26Y27Y26W24W23V27U26U24U23T26T27T24T23P27P26P24P23M27N26PCIE_TXP0PCIE_TXN0PCIE_TXP1PCIE_TXN1PCIE_TXP2PCIE_TXN2PCIE_TXP3PCIE_TXN3PCIE_TXP4PCIE_TXN4PCIE_TXP5PCIE_TXN5PCIE_TXP6PCIE_TXN6PCIE_TXP7PCIE_TXN7PCIE_TXP8PCIE_TXN8PCIE_TXP9PCIE_TXN9PCIE_TXP10PCIE_TXN10PCIE_TXP11PCIE_TXN11PCIE_TXP12PCIE_TXN12PCIE_TXP13PCIE_TXN13PCIE_TXP14PCIE_TXN14PCIE_TXP15PCIE_TXN15C(7)PCIE_RXP[15..0](7)PCIE_RXN[15..0](7)PCIE_TXP[15..0]CPCIE_RXP[15..0]PCIE_RXN[15..0]PCIE_TXP[15..0]PCIE_TXN[15..0](7)PCIE_TXN[15..0]PCI EXPRESS INTERFACEBBCLOCKPCIE_REFCLKPPCIE_REFCLKNAK30AK32PCIE_REFCLKPPCIE_REFCLKNCALIBRATIONPCIE_CALRPR71111KPWRGOOD_GPUPCIE_RST#N10AL27PWRGOODPERSTBPark-S3PCIE_CALRNY22PCIE_CALRPAA22PCIE_CALRNR10091.27KR10102.0K+1.0V_REG(7)PCIE_RST#AACONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.© 2007 Advanced Micro DevicesAdvanced Micro Devices AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
1 Commerce Valley Drive Eastwith AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
Markham, Ontarioother than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
Date:Wednesday, February 24, 2010regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
Sheet1purpose, and disclaims responsibility forany consequences resulting
of12from use of the information included 1Title5432Cedar DDR3 MxM3.01Doc No.105-C077xx-00B
54321U1BU1FR6216Y11AE9L9N9AE8AD9AC10AD7AC8AC7AB9AB8AB7AB4AB2Y8Y7TXCAP_DPA3PTXCAM_DPA3NDVCLKDVCNTL_0DVCNTL_1DVCNTL_2DVDATA_12DVDATA_11DVDATA_10DVDATA_9DVDATA_8DVDATA_7DVDATA_6DVDATA_5DVDATA_4DVDATA_3DVDATA_2DVDATA_1DVDATA_0TX0P_DPA2PTX0M_DPA2NTX1P_DPA1PTX1M_DPA1NTX2P_DPA0PTX2M_DPA0NTXCBP_DPB3PTXCBM_DPB3NTX3P_DPB2PTX3M_DPB2NTX4P_DPB1PTX4M_DPB1NTX5P_DPB0PTX5M_DPB0NW6V6AC6AC5AA5AA6DPC_PVDDDPC_PVSSDPC_VDD18#1DPC_VDD18#2DPC_VDD10#1DPC_VDD10#2DPCTXCCP_DPC3PTXCCM_DPC3NTX0P_DPC2PTX0M_DPC2NTX1P_DPC1PTX1M_DPC1NU1W1U3Y6AA1DPC_VSSR#1DPC_VSSR#2DPC_VSSR#3DPC_VSSR#4DPC_VSSR#5TX2P_DPC0PTX2M_DPC0NDPC_CALRV4U5W3V2Y4W5AA3Y2J8AF2AF4AG3AG5AH3AH1AK3AK1AK5AM3AK6AM5AJ7AH6AK8AL7TXCAP_DPA3P(7)TXCAM_DPA3N(7)TX0P_DPA2P(7)TX0M_DPA2N(7)TX1P_DPA1P(7)TX1M_DPA1N(7)TX2P_DPA0P(7)TX2M_DPA0N(7)TXCBP_DPB3P(7)TXCBM_DPB3N(7)TX3P_DPB2P(7)TX3M_DPB2N(7)TX4P_DPB1P(7)TX4M_DPB1N(7)TX5P_DPB0P(7)TX5M_DPB0N(7)LVDS CONTROLVARY_BLDIGONAB11AB1210KBLON_PWM(7)FPVCC(4,7)DVODPATXCLK_UP_DPF3PTXCLK_UN_DPF3NTXOUT_U0P_DPF2PTXOUT_U0N_DPF2NTXOUT_U1P_DPF1PTXOUT_U1N_DPF1NTXOUT_U2P_DPF0PTXOUT_U2N_DPF0NTXOUT_U3PTXOUT_U3NLVTMDPTXCLK_LP_DPE3PTXCLK_LN_DPE3NTXOUT_L0P_DPE2PTXOUT_L0N_DPE2NTXOUT_L1P_DPE1PTXOUT_L1N_DPE1NTXOUT_L2P_DPE0PTXOUT_L2N_DPE0NTXOUT_L3PTXOUT_L3NAH20AJ19AL21AK20AH22AJ21AL23AK22AK24AJ23TXCLK_U+(7)TXCLK_U-(7)TXOUT_U0+(7)TXOUT_U0-(7)TXOUT_U1+(7)TXOUT_U1-(7)TXOUT_U2+(7)TXOUT_U2-(7)TXOUT_U3+(7)TXOUT_U3-(7)D+1.8V_REGDR608810KR608710KMEM_ID1MEM_ID0DPBDVPDATA[1:0] = 0x0 for Hynix 23E22387MR12DVPDATA[1:0] = 0x1 for Samsung 23E42387ME12AL15AK14AH16AJ15AL17AK16AH18AJ17AL19AK18TXCLK_L+(7)TXCLK_L-(7)TXOUT_L0+(7)TXOUT_L0-(7)TXOUT_L1+(7)TXOUT_L1-(7)TXOUT_L2+(7)TXOUT_L2-(7)TXOUT_L3+(7)TXOUT_L3-(7)Park-S3I2C+3VRUNR1R3SCLSDAGENERAL PURPOSE I/O(7,8)GPIO0(7,8)GPIO1(8)GPIO2(7)GPIO3_SMBDATA(7)GPIO4_SMBCLK(7)GPIO5_AC_BATTGPIO19_CTFR2610K(7)GPIO7_BLON(8)GPIO9(8)GPIO11(8)GPIO12(8)GPIO13(7)GPIO14_HPD2(8,9)GPIO15_PCNTL0(7)GPIO17_THERMAL_INT(7)GPIO18_HPD3(8,9)GPIO20_PCNTL1(8)GPIO22TP13TP14TP15TP16TP1735mil35mil35mil35mil35milR4310KGPIO0GPIO1GPIO2GPIO3_SMBDATGPIO4_SMBCLKGPIO5_AC_BATTGPIO7_BLONGPIO8GPIO8_ROMSOGPIO9GPIO9_ROMSIGPIO10GPIO10_ROMSCKGPIO11GPIO12GPIO13GPIO14_HPD2GPIO15_PCNTL0GPIO17_THERMAL_INTGPIO18_HPD3GPIO19_CTFGPIO20_PCNTL1GPIO22GPIO22_ROMCSBGPIO24_TRSTBGPIO25_TDIGPIO26_TCKGPIO27_TMSGPIO28_TDOTESTENU6U10T10U8U7T9T8T7P10P4P2N6N5N3Y9N1M4R6W10M2P8P7N8N7L6L5L3L1K4K7AF24AB13W8W9W7AD10AC14AB16GPIO_0GPIO_1GPIO_2GPIO_3_SMBDATAGPIO_4_SMBCLKGPIO_5_AC_BATTGPIO_6GPIO_7_BLONGPIO_8_ROMSOGPIO_9_ROMSIGPIO_10_ROMSCKGPIO_11GPIO_12GPIO_13GPIO_14_HPD2GPIO_15_PWRCNTL_0GPIO_16_SSINGPIO_17_THERMAL_INTGPIO_18_HPD3GPIO_19_CTFGPIO_20_PWRCNTL_1GPIO_21_BB_ENGPIO_22_ROMCSBGPIO_23_CLKREQBJTAG_TRSTBJTAG_TDIJTAG_TCKJTAG_TMSJTAG_TDOTESTENTESTEN_LEGACYGENERICAGENERICBGENERICCGENERICDGENERICE_HPD4HPD1PX_ENDAC2H2SYNCV2SYNCVDD2DIVSS2DIA2VDD+VDDR3A2VDDQ+1.8V_REGA2VSSQR5675R586C5685499RVREFAC16249R100nF_6.3VVREFGR2SETAL13AJ13AD19AC19AE20AE17AE19AG13HSYNC_DAC2(8)VSYNC_DAC2(8)BCR6097100K(7)CTFb3Q2612N7002_NL2RRBGGBBBBHSYNCVSYNCRSETAVDDAVSSQVDD1DIVSS1DIR2R2BG2G2BB2B2BCYCOMPAM26AK26AL25AJ25AH24AG25AH26AJ27AD22AG24AE22AE23AD23AM12AK12AL11AJ11AK10AL9AH12AM10AJ9RSETHSYNC_DAC1(7,8)VSYNC_DAC1(7,8)R5623499RR6118150RR6119150RR6120150RVGA_RED(7)VGA_GRN(7)VGA_BLU(7)CDAC1PLACE RGBTERMINATIONRESISTORS CLOSETO ASICAVDD(AVDD:70mA @ 1.8V)C56271uF_6.3VC56284.7uF_6.3V+1.8V_REGB10063BLM15BD121SN1VDD1DI(VDD1DI: 45mA @ 1.8V)C56101uF_6.3VC57084.7uF_6.3VB10064BLM15BD121SN1JTAG DEBUG PORTB(7)MB_GPIO0(7)MB_GPIO1(7)MB_GPIO2R5631R5632R56330RDNI0RDNI0RDNIGENERICAGENERICBGENERICCR562710KDNIR562810KDNIR562910KDNI(7)HPD1PLACE VREFGDIVIDER AND CAPCLOSE TO ASIC+1.8V_REGB10098BLM15BD121SN1DDC/AUX(DPLL_PVDD: 75mA @ 1.8V)C5784C57854.7uF_6.3V1uF_6.3VC5786100nF_6.3VDPLL_PVDDAF14AE14AD14XTALINXTALOUTAM28AK28AC22AB22PLL/CLOCKDPLL_PVDDDPLL_PVSSDPLL_VDDCXTALINXTALOUTXO_INXO_IN2DDC1CLKDDC1DATAAUX1PAUX1NDDC2CLKDDC2DATAAUX2PAUX2NAE6AE5AD2AD4AC11AC13AD13AD11AD20AC20AE16AD16AC1AC3ADDCCLK_AUX1P(7)DDCDATA_AUX1N(7)DPA+VDDR3BIOS1C5613100nF_6.3VU5508GPIO22GPIO81234CE#SOWP#GNDVCCHOLD#SCKSI8765GPIO10GPIO9113-C077xx-xxxVIDEO BIOSFIRMWAREBIOSDDCCLK_AUX2P(7)DDCDATA_AUX2N(7)DDCCLK_AUX3P(7)DDCDATA_AUX3N(7)DDC5CLK(7)DDC5DATA(7)DPB+1.0V_REGB10099BLM15BD121SN1(DPLL_VDDC: 125mA @ 1.0V)C57881uF_6.3VC5789100nF_6.3VDPLL_VDDCR6092211M43DDCCLK_AUX3PDDCDATA_AUX3NDDCCLK_AUX5PDDCDATA_AUX5NLVDSVGAPM25LV512A-100SCEC5973Y1C597412pF_50V27.000MHz_10PPM_30R12pF_50VT4T2DPLUSDMINUSTS_FDOTSVDDTSVSSTHERMALADDC6CLKDDC6DATA+1.8V_REG(TSVDD: 5mA @ 1.8V)C59241uF_6.3VTSVDDR5AD17AC17SERIAL EEPROM 512K/1MCONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.© 2007 Advanced Micro DevicesAdvanced Micro Devices AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
1 Commerce Valley Drive Eastwith AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
Markham, Ontarioother than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
Date:Wednesday, February 24, 2010regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
Sheet2purpose, and disclaims responsibility forany consequences resulting
of12from use of the information included 2280007900G for 1Mbit (PM25LV010A-100SCE)Park-S3Rev1TitleCedar DDR3 MxM3.054321Doc No.105-C077xx-00B
54321U1DMEM I/ODU1EPCIEPCIE_VDDRAB23AC23AD24AE24AE25AE26AF25AG26PCIE_VDDCPCIE_VDDC#1PCIE_VDDC#2PCIE_VDDC#3PCIE_VDDC#4PCIE_VDDC#5PCIE_VDDC#6PCIE_VDDC#7PCIE_VDDC#8PCIE_VDDC#9PCIE_VDDC#10PCIE_VDDC#11PCIE_VDDC#12VDDC#1VDDC#2VDDC#3VDDC#4VDDC#5VDDC#6VDDC#7VDDC#8VDDC#9VDDC#10VDDC#11VDDC#12VDDC#13VDDC#14VDDC#15VDDC#16VDDC#17VDDC#18VDDC#19VDDC#20VDDC#21VDDC#22VDDC#23L23L24L25L26M22N22N23N24R22T22U22V22AA15N15N17R13R16R18Y21T12T15T17T20U13U16U18V21V15V17V20Y13Y16Y18M11M12+MVDD(VDDR1: 1.8A @ 1.5V)C60641uF_6.3VC60651uF_6.3VC60661uF_6.3VC60671uF_6.3VC60681uF_6.3VC60691uF_6.3VC60701uF_6.3VC60711uF_6.3VC607410uF_4VC607510uF_4VC607610uF_4VH13H16H19J10J23J24J9K10K23K24K9L11L12L13L20L21L22(PCIE_VDDR: 400mA @ 1.8V)C59281uF_6.3VC59291uF_6.3VC58001uF_6.3V+1.8V_REGAA27AB24AB32AC24AC26AC27AD25AD32AE27AF32AG27AH32K28K32L27M32N25N27P25P32R27T25T32U25U27V32W25W26W27Y25Y32PCIE_VSS#1PCIE_VSS#2PCIE_VSS#3PCIE_VSS#4PCIE_VSS#5PCIE_VSS#6PCIE_VSS#7PCIE_VSS#8PCIE_VSS#9PCIE_VSS#10PCIE_VSS#11PCIE_VSS#12PCIE_VSS#13PCIE_VSS#14PCIE_VSS#15PCIE_VSS#16PCIE_VSS#17PCIE_VSS#18PCIE_VSS#19PCIE_VSS#20PCIE_VSS#21PCIE_VSS#22PCIE_VSS#23PCIE_VSS#24PCIE_VSS#25PCIE_VSS#26PCIE_VSS#27PCIE_VSS#28PCIE_VSS#29PCIE_VSS#30PCIE_VSS#31GND#1GND#2GND#3GND#4GND#5GND#6GND#7GND#8GND#9GND#10GND#11GND#12GND#13GND#14GND#15GND#16GND#17GND#18GND#19GND#20GND#21GND#22GND#23GND#24GND#25GND#26GND#27GND#28GND#29GND#30GND#31GND#32GND#33GND#34GND#35GND#36GND#37GND#38GND#39GND#40GND#41GND#42GND#43GND#44GND#45GND#46GND#47GND#48GND#49GND#50GND#51GND#52GND#53GND#54GND#55A3A30AA13AA16AB10AB15AB6AC9AD6AD8AE7AG12AH10AH28B10B12B14B16B18B20B22B24B26B6B8C1C32E28F10F12F14F16F18F2F20F22F24F26F6F8G10G27G31G8H14H17H2H20H6J27J31K11K2K22K6DVDDR1#1VDDR1#2VDDR1#3VDDR1#4VDDR1#5VDDR1#6VDDR1#7VDDR1#8VDDR1#9VDDR1#10VDDR1#11VDDR1#12VDDR1#13VDDR1#14VDDR1#15VDDR1#16VDDR1#17PCIE_VDDR#1PCIE_VDDR#2PCIE_VDDR#3PCIE_VDDR#4PCIE_VDDR#5PCIE_VDDR#6PCIE_VDDR#7PCIE_VDDR#8C58024.7uF_6.3V(PCIE_VDDC: 2.0A @ 1.0V)C9831uF_6.3VC9721uF_6.3VC9731uF_6.3VC59301uF_6.3V+1.0V_REGC16684.7uF_6.3V+1.8V_REGB10100BLM15BD121SN1(VDD_CT: 17mA @ 1.8V)C58211uF_6.3V+VDDR3VDD_CTAA20AA21AB20AB21LEVELTRANSLATIONVDD_CT#1VDD_CT#2VDD_CT#3VDD_CT#4I/OAA17AA18AB17AB18VDDR3#1VDDR3#2VDDR3#3VDDR3#4VDDR4#1VDDR4#2VDDR4#3NC#1NC#2NC#3NC#4(VDDC: TBDmA @ TBDV)C2511uF_6.3VC2521uF_6.3VC2531uF_6.3VC2551uF_6.3VC2601uF_6.3VC2611uF_6.3VC2581uF_6.3VC2591uF_6.3V+VDDCCORE(VDDR3: 60mA @ 3.3V)VDDR3C55911uF_6.3V(VDDR4: TBDmA @ 1.8V)CVDDR4V12Y12U12AA11AA12V11U11C1611uF_6.3VC1621uF_6.3VC1631uF_6.3VC1641uF_6.3VC1651uF_6.3VC1661uF_6.3VC1671uF_6.3VC1681uF_6.3VC59321uF_6.3VC19110uF_4VC19210uF_4VC19310uF_4VC19410uF_4VMEM CLKL17L16NC_VDDRHANC_VSSRHAPLL
AM30MPV18L8NC_MPV18PCIE_PVDDB10105BLM15BD121SN1(PCIE_PVDD: 40mA @ 1.8V)C5832C58334.7uF_6.3V1uF_6.3VC5834100nF_6.3VPCIE_PVDDBIF_VDDC#1BIF_VDDC#2R21U21SPV18H7+1.8V_REGB10128BLM15BD121SN1ISOLATEDCORE I/OSPV18(MPV18: 75mA @ 1.8V)SPV10C5950C59514.7uF_6.3V1uF_6.3VC5954100nF_6.3VH8J7SPV10SPVSSVDDCI#1VDDCI#2VDDCI#3VDDCI#4VDDCI#5VDDCI#6VDDCI#7VDDCI#8M13M15M16M17M18M20M21N20(VDDCI : TBDmA @ VDDC)C58361uF_6.3VC58351uF_6.3VC59701uF_6.3VC59711uF_6.3VC597210uF_4V+VDDCM6N11N12N13N16N18N21P6P9R12R15R17R20T13T16T18T21T6U15U17U20U9V13V16V18Y10Y15Y17Y20R11T11GND#56GND#57GND#58GND#59GND#60GND#61GND#62GND#63GND#64GND#65GND#66GND#67GND#68GND#69GND#70GND#71GND#72GND#73GND#74GND#75GND#76GND#77GND#78GND#79GND#80GND#81GND#82GND#83GND#84GND#85GND#86CGNDPOWERVSS_MECH#1VSS_MECH#2VSS_MECH#3A32AM1AM32Park-S3BB10127BLM15BD121SN1(SPV18: 50mA @ 1.8V)C5947C59484.7uF_6.3V1uF_6.3VC5949100nF_6.3VPark-S3B+1.0V_REGB10124BLM15BD121SN1(SPV10: 100mA @ 1.0V)C56141uF_6.3VC5615100nF_6.3V+VDDC+1.8V_REGC11uF_6.3VC21uF_6.3VC31uF_6.3VC41uF_6.3VC51uF_6.3VC61uF_6.3V+VDDR3+MVDDC7C8+PWR_SRC1uF_6.3V1uF_6.3VC91uF_6.3VC101uF_6.3VAACONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.© 2007 Advanced Micro DevicesAdvanced Micro Devices AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
1 Commerce Valley Drive Eastwith AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
Markham, Ontarioother than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
Date:Wednesday, February 24, 2010regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
Sheet3purpose, and disclaims responsibility forany consequences resulting
of12from use of the information included 1Title5432Cedar DDR3 MxM3.01Doc No.105-C077xx-00B
54321DD+5VRUN+1.8V_REG351C27100nF2U27474HCT1G126GW3Q27NDS335N2DPEF_VDD18(2,7)FPVCC1U1GDP E/F POWER+1.8V_REGB10113BLM15AG121SN1DDP A/B POWERDPA_VDD18#1DPA_VDD18#2AE11AF11DPAB_VDD10AG20AG21C(DPEF_VDD18: 400mA @ 1.8V)C5855C58564.7uF_6.3V1uF_6.3VDPEF_VDD18AG15AG16DPEF_VDD10DPE_VDD10#1DPE_VDD10#2DPE_VSSR#1DPE_VSSR#2DPE_VSSR#3DPE_VSSR#4DPE_VSSR#5DPA_VDD10#1DPA_VDD10#2DPA_VSSR#1DPA_VSSR#2DPA_VSSR#3DPA_VSSR#4DPA_VSSR#5AF6AF7DPE_VDD18#1DPE_VDD18#2DPAB_VDD18(DPAB_VDD18: 260mA @ 1.8V)C59571uF_6.3VC59554.7uF_6.3V+1.8V_REGB10130BLM15AG121SN1DC+1.0V_REGB10115120R_450mA(DPEF_VDD10: 240mA @ 1.0V)C5861C58624.7uF_6.3V1uF_6.3VAG14AH14AM14AM16AM18DPEF_VDD18AF16AG17DPEF_VDD10AF22AG22AF23AG23AM20AM22AM24AE1AE3AG1AG6AH5DPAB_VDD18(DPAB_VDD10: 220mA @ 1.0V)C58411uF_6.3V+1.0V_REGB10108120R_450mAC58404.7uF_6.3VDPF_VDD18#1DPF_VDD18#2DPB_VDD18#1DPB_VDD18#2AE13AF13DPAB_VDD10DPF_VDD10#1DPF_VDD10#2DPF_VSSR#1DPF_VSSR#2DPF_VSSR#3DPF_VSSR#4DPF_VSSR#5DPB_VDD10#1DPB_VDD10#2DPB_VSSR#1DPB_VSSR#2DPB_VSSR#3DPB_VSSR#4DPB_VSSR#5AF8AF9AF10AG9AH8AM6AM8R6080150RAF17DPEF_CALRDPEF_CALRDPAB_CALRAE10DPAB_CALRR6079150R(DPEF_PVDD: 40mA @ 1.8V)DPEF_PVDDAG18AF19DPEF_PVDDDPE_PVDDDPE_PVSSDP PLL POWERDPAB_PVDDDPA_PVDDDPA_PVSSAG8AG7DPAB_PVDD(DPAB_PVDD: 40mA @ 1.8V)BAG19AF20DPF_PVDDDPF_PVSSDPB_PVDDDPB_PVSSAG10AG11BPark-S3AACONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.© 2007 Advanced Micro DevicesAdvanced Micro Devices AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
1 Commerce Valley Drive Eastwith AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
Markham, Ontarioother than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
Date:Wednesday, February 24, 2010regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
Sheet4purpose, and disclaims responsibility forany consequences resulting
of12from use of the information included 1Title5432Cedar DDR3 MxM3.01Doc No.105-C077xx-00B
12345678AAU1C(6)M_MDA[63..0]M_MDA0M_MDA1M_MDA2M_MDA3M_MDA4M_MDA5M_MDA6M_MDA7M_MDA8M_MDA9M_MDA10M_MDA11M_MDA12M_MDA13M_MDA14M_MDA15M_MDA16M_MDA17M_MDA18M_MDA19M_MDA20M_MDA21M_MDA22M_MDA23M_MDA24M_MDA25M_MDA26M_MDA27M_MDA28M_MDA29M_MDA30M_MDA31M_MDA32M_MDA33M_MDA34M_MDA35M_MDA36M_MDA37M_MDA38M_MDA39M_MDA40M_MDA41M_MDA42M_MDA43M_MDA44M_MDA45M_MDA46M_MDA47M_MDA48M_MDA49M_MDA50M_MDA51M_MDA52M_MDA53M_MDA54M_MDA55M_MDA56M_MDA57M_MDA58M_MDA59M_MDA60M_MDA61M_MDA62M_MDA63MVREFxA+MVDDR292100RR302R301243R243RMEM_CALRN0MEM_CALRN1J25K25K27J29H30H32G29F28F32F30C30F27A28C28E27G26D26F25A25C25E25D24E23F23D22F21E21D20F19A19D18F17A17C17E17D16F15A15D14F13A13C13E11A11C11F11A9C9F9D8E7A7C7F7A5E5C3E1G7G6G1G3J6J1J3J5K26J26DQA_0DQA_1DQA_2DQA_3DQA_4DQA_5DQA_6DQA_7DQA_8DQA_9DQA_10DQA_11DQA_12DQA_13DQA_14DQA_15DQA_16DQA_17DQA_18DQA_19DQA_20DQA_21DQA_22DQA_23DQA_24DQA_25DQA_26DQA_27DQA_28DQA_29DQA_30DQA_31DQA_32DQA_33DQA_34DQA_35DQA_36DQA_37DQA_38DQA_39DQA_40DQA_41DQA_42DQA_43DQA_44DQA_45DQA_46DQA_47DQA_48DQA_49DQA_50DQA_51DQA_52DQA_53DQA_54DQA_55DQA_56DQA_57DQA_58DQA_59DQA_60DQA_61DQA_62DQA_63MVREFDAMVREFSAMEM_CALRN0MEM_CALRP0MAA_0MAA_1MAA_2MAA_3MAA_4MAA_5MAA_6MAA_7MAA_8MAA_9MAA_10MAA_11MAA_12MAA_13/BA2MAA_14/BA0MAA_15/BA1DQMA_0DQMA_1DQMA_2DQMA_3DQMA_4DQMA_5DQMA_6DQMA_7RDQSA_0RDQSA_1RDQSA_2RDQSA_3RDQSA_4RDQSA_5RDQSA_6RDQSA_7WDQSA_0WDQSA_1WDQSA_2WDQSA_3WDQSA_4WDQSA_5WDQSA_6WDQSA_7ODTA0ODTA1CLKA0CLKA0BCLKA1CLKA1BRASA0BRASA1BCASA0BCASA1BCSA0B_0CSA0B_1CSA1B_0CSA1B_1CKEA0CKEA1WEA0BWEA1BRSVD#2RSVD#3DRAM_RSTCLKTESTACLKTESTBPark-S3M_MAA[14..0](6)K17J20H23G23G24H24J19K19J14K14J11J13H11G11J16L15E32E30A21C21E13D12E3F4H28C27A23E19E15D10D6G5H27A27C23C19C15E9C5H4L18K16H26H25G9H9G22G17G19G16H22J22G13K13K20J17G25H10G14G20M_MAA0M_MAA1M_MAA2M_MAA3M_MAA4M_MAA5M_MAA6M_MAA7M_MAA8M_MAA9M_MAA10M_MAA11M_MAA12BA2BA0BA1M_DQMA#0M_DQMA#1M_DQMA#2M_DQMA#3M_DQMA#4M_DQMA#5M_DQMA#6M_DQMA#7M_QSA0M_QSA1M_QSA2M_QSA3M_QSA4M_QSA5M_QSA6M_QSA7M_QSA#0M_QSA#1M_QSA#2M_QSA#3M_QSA#4M_QSA#5M_QSA#6M_QSA#7ODTA0ODTA1CLKA0CLKA#0CLKA1CLKA#1RASA0#RASA1#CASA0#CASA1#CSA#0_0CSA#1_0CKEA0CKEA1WEA0#WEA1#M_MAA14M_MAA13ODTA0(6)ODTA1(6)CLKA0(6)CLKA#0(6)CLKA1(6)CLKA#1(6)RASA#0(6)RASA#1(6)CASA#0(6)CASA#1(6)CSA#0_0(6)CSA#1_0(6)CKEA0(6)CKEA1(6)WEA#0(6)WEA#1(6)M_MAA[14..0](6)MEMORY
INTERFACEBA2(6)BA0(6)BA1(6)M_DQMA#[7..0](6)M_QSA[7..0](6)BBM_QSA#[7..0](6)+MVDDR29140.2RCCL10K8L7CLKTESTACLKTESTB35mil35milTP7TP8R295R2945.1K10RR296C299120pF_50V51.1RMEM_RST(6)Place close to ASICDDCONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.© 2007 Advanced Micro DevicesAdvanced Micro Devices AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
1 Commerce Valley Drive Eastwith AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
Markham, Ontarioother than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
Date:Wednesday, February 24, 2010regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
Sheet5purpose, and disclaims responsibility forany consequences resulting
of12from use of the information included 1TitleCedar DDR3 MxM3.01234567Doc No.8105-C077xx-00B
54321(5)M_MDA[63..0]M_MDA0M_MDA1M_MDA2M_MDA3M_MDA4M_MDA5M_MDA6M_MDA7M_MDA8M_MDA9M_MDA10M_MDA11M_MDA12M_MDA13M_MDA14M_MDA15M_MDA16M_MDA17M_MDA18M_MDA19M_MDA20M_MDA21M_MDA22M_MDA23M_MDA24M_MDA25M_MDA26M_MDA27M_MDA28M_MDA29M_MDA30M_MDA31M_MDA32M_MDA33M_MDA34M_MDA35M_MDA36M_MDA37M_MDA38M_MDA39M_MDA40M_MDA41M_MDA42M_MDA43M_MDA44M_MDA45M_MDA46M_MDA47M_MDA48M_MDA49M_MDA50M_MDA51M_MDA52M_MDA53M_MDA54M_MDA55M_MDA56M_MDA57M_MDA58M_MDA59M_MDA60M_MDA61M_MDA62M_MDA63(5)M_MAA[14..0]M_MAA0M_MAA1M_MAA2M_MAA3M_MAA4M_MAA5M_MAA6M_MAA7M_MAA8M_MAA9M_MAA10M_MAA11M_MAA12M_MAA13M_MAA14U201VREFC_U201VREFD_U201M_MAA0M_MAA1M_MAA2M_MAA3M_MAA4M_MAA5M_MAA6M_MAA7M_MAA8M_MAA9M_MAA10M_MAA11M_MAA12M_MAA13M_MAA14M8H1N3P7P3N2P8P2R8R2T8R3L7R7N7T3T7M7M2N8M3VREFCAVREFDQA0A1A2A3A4A5A6A7A8A9A10/APA11A12/BCA13A14A15BA0BA1BA2DQL0DQL1DQL2DQL3DQL4DQL5DQL6DQL7DQU0DQU1DQU2DQU3DQU4DQU5DQU6DQU7E3F7F2F8H3H8G2H7D7C3C8C2A7A2B8A3M_MDA10M_MDA12M_MDA11M_MDA13M_MDA8M_MDA15M_MDA9M_MDA14M_MDA4M_MDA0M_MDA7M_MDA1M_MDA6M_MDA2M_MDA5M_MDA3CHANNEL A: 256MB/512MB DDR3U202VREFC_U202VREFD_U202M_MAA0M_MAA1M_MAA2M_MAA3M_MAA4M_MAA5M_MAA6M_MAA7M_MAA8M_MAA9M_MAA10M_MAA11M_MAA12M_MAA13M_MAA14+MVDD(5)BA0(5)BA1(5)BA2BA0BA1BA2VDD#B2VDD#D9VDD#G7VDD#K2VDD#K8VDD#N1VDD#N9VDD#R1VDD#R9VDDQ#A1VDDQ#A8VDDQ#C1VDDQ#C9VDDQ#D2VDDQ#E9VDDQ#F1VDDQ#H2VDDQ#H9VSS#A9VSS#B3VSS#E1VSS#G8VSS#J2VSS#J8VSS#M1VSS#M9VSS#P1VSS#P9VSS#T1VSS#T9VSSQ#B1VSSQ#B9VSSQ#D1VSSQ#D8VSSQ#E2VSSQ#E8VSSQ#F9VSSQ#G1VSSQ#G9B2D9G7K2K8N1N9R1R9A1A8C1C9D2E9F1H2H9A9B3E1G8J2J8M1M9P1P9T1T9B1B9D1D8E2E8F9G1G9(5)BA0(5)BA1(5)BA2M2N8M3BA0BA1BA2VDD#B2VDD#D9VDD#G7VDD#K2VDD#K8VDD#N1VDD#N9VDD#R1VDD#R9VDDQ#A1VDDQ#A8VDDQ#C1VDDQ#C9VDDQ#D2VDDQ#E9VDDQ#F1VDDQ#H2VDDQ#H9VSS#A9VSS#B3VSS#E1VSS#G8VSS#J2VSS#J8VSS#M1VSS#M9VSS#P1VSS#P9VSS#T1VSS#T9VSSQ#B1VSSQ#B9VSSQ#D1VSSQ#D8VSSQ#E2VSSQ#E8VSSQ#F9VSSQ#G1VSSQ#G9B2D9G7K2K8N1N9R1R9A1A8C1C9D2E9F1H2H9A9B3E1G8J2J8M1M9P1P9T1T9B1B9D1D8E2E8F9G1G9M8H1N3P7P3N2P8P2R8R2T8R3L7R7N7T3T7M7VREFCAVREFDQA0A1A2A3A4A5A6A7A8A9A10/APA11A12/BCA13A14A15DQL0DQL1DQL2DQL3DQL4DQL5DQL6DQL7DQU0DQU1DQU2DQU3DQU4DQU5DQU6DQU7E3F7F2F8H3H8G2H7D7C3C8C2A7A2B8A3M_MDA27M_MDA28M_MDA26M_MDA29M_MDA24M_MDA31M_MDA25M_MDA30M_MDA21M_MDA19M_MDA23M_MDA17M_MDA20M_MDA16M_MDA22M_MDA18+MVDD(5)BA0(5)BA1(5)BA2M2N8M3BA0BA1BA2VDD#B2VDD#D9VDD#G7VDD#K2VDD#K8VDD#N1VDD#N9VDD#R1VDD#R9VDDQ#A1VDDQ#A8VDDQ#C1VDDQ#C9VDDQ#D2VDDQ#E9VDDQ#F1VDDQ#H2VDDQ#H9VSS#A9VSS#B3VSS#E1VSS#G8VSS#J2VSS#J8VSS#M1VSS#M9VSS#P1VSS#P9VSS#T1VSS#T9VSSQ#B1VSSQ#B9VSSQ#D1VSSQ#D8VSSQ#E2VSSQ#E8VSSQ#F9VSSQ#G1VSSQ#G9B2D9G7K2K8N1N9R1R9A1A8C1C9D2E9F1H2H9A9B3E1G8J2J8M1M9P1P9T1T9B1B9D1D8E2E8F9G1G9VREFC_U401VREFD_U401M_MAA0M_MAA1M_MAA2M_MAA3M_MAA4M_MAA5M_MAA6M_MAA7M_MAA8M_MAA9M_MAA10M_MAA11M_MAA12M_MAA13M_MAA14M8H1N3P7P3N2P8P2R8R2T8R3L7R7N7T3T7M7U401VREFCAVREFDQA0A1A2A3A4A5A6A7A8A9A10/APA11A12/BCA13A14A15DQL0DQL1DQL2DQL3DQL4DQL5DQL6DQL7DQU0DQU1DQU2DQU3DQU4DQU5DQU6DQU7E3F7F2F8H3H8G2H7D7C3C8C2A7A2B8A3M_MDA35M_MDA39M_MDA34M_MDA38M_MDA32M_MDA37M_MDA33M_MDA36M_MDA45M_MDA43M_MDA46M_MDA41M_MDA44M_MDA42M_MDA47M_MDA40+MVDD(5)BA0(5)BA1(5)BA2M2N8M3BA0BA1BA2VDD#B2VDD#D9VDD#G7VDD#K2VDD#K8VDD#N1VDD#N9VDD#R1VDD#R9VDDQ#A1VDDQ#A8VDDQ#C1VDDQ#C9VDDQ#D2VDDQ#E9VDDQ#F1VDDQ#H2VDDQ#H9VSS#A9VSS#B3VSS#E1VSS#G8VSS#J2VSS#J8VSS#M1VSS#M9VSS#P1VSS#P9VSS#T1VSS#T9VSSQ#B1VSSQ#B9VSSQ#D1VSSQ#D8VSSQ#E2VSSQ#E8VSSQ#F9VSSQ#G1VSSQ#G9B2D9G7K2K8N1N9R1R9A1A8C1C9D2E9F1H2H9A9B3E1G8J2J8M1M9P1P9T1T9B1B9D1D8E2E8F9G1G9VREFC_U402VREFD_U402M_MAA0M_MAA1M_MAA2M_MAA3M_MAA4M_MAA5M_MAA6M_MAA7M_MAA8M_MAA9M_MAA10M_MAA11M_MAA12M_MAA13M_MAA14M8H1N3P7P3N2P8P2R8R2T8R3L7R7N7T3T7M7U402VREFCAVREFDQA0A1A2A3A4A5A6A7A8A9A10/APA11A12/BCA13A14A15DQL0DQL1DQL2DQL3DQL4DQL5DQL6DQL7DQU0DQU1DQU2DQU3DQU4DQU5DQU6DQU7E3F7F2F8H3H8G2H7D7C3C8C2A7A2B8A3M_MDA48M_MDA52M_MDA50M_MDA54M_MDA51M_MDA55M_MDA49M_MDA53M_MDA56M_MDA63M_MDA59M_MDA60M_MDA57M_MDA62M_MDA58M_MDA61+MVDDDD(5)CLKA0(5)CLKA#0(5)CKEA0(5)ODTA0(5)CSA#0_0(5)RASA#0(5)CASA#0(5)WEA#0M_QSA1M_QSA0M_DQMA#1M_DQMA#0M_QSA#1M_QSA#0J7K7K9K1L2J3K3L3F3C7E7D3G3B7CKCKCKEODTCSRASCASWEDQSLDQSUDMLDMUDQSLDQSU(5)CLKA0(5)CLKA#0(5)CKEA0(5)ODTA0(5)CSA#0_0(5)RASA#0(5)CASA#0(5)WEA#0M_QSA3M_QSA2M_DQMA#3M_DQMA#2M_QSA#3M_QSA#2J7K7K9K1L2J3K3L3F3C7E7D3G3B7CKCKCKEODTCSRASCASWEDQSLDQSUDMLDMUDQSLDQSU(5)CLKA1(5)CLKA#1(5)CKEA1(5)ODTA1(5)CSA#1_0(5)RASA#1(5)CASA#1(5)WEA#1M_QSA4M_QSA5M_DQMA#4M_DQMA#5M_QSA#4M_QSA#5J7K7K9K1L2J3K3L3F3C7E7D3G3B7CKCKCKEODTCSRASCASWEDQSLDQSUDMLDMUDQSLDQSU(5)CLKA1(5)CLKA#1(5)CKEA1(5)ODTA1(5)CSA#1_0(5)RASA#1(5)CASA#1(5)WEA#1M_QSA6M_QSA7M_DQMA#6M_DQMA#7M_QSA#6M_QSA#7J7K7K9K1L2J3K3L3F3C7E7D3G3B7CKCKCKEODTCSRASCASWEDQSLDQSUDMLDMUDQSLDQSUCC(5)MEM_RSTT2L8R217243RRESETZQ(5)MEM_RSTT2L8R218243RRESETZQ(5)MEM_RSTT2L8R219243RRESETZQ(5)MEM_RSTT2L8R220243RRESETZQJ1L1J9L9NC#J1NC#L1NC#J9NC#L9J1L1J9L9NC#J1NC#L1NC#J9NC#L9J1L1J9L9NC#J1NC#L1NC#J9NC#L9J1L1J9L9NC#J1NC#L1NC#J9NC#L9100-BALLSDRAM DDR3128Mx16 DDR3+MVDD100-BALLSDRAM DDR3128Mx16 DDR3+MVDD100-BALLSDRAM DDR3128Mx16 DDR3+MVDD100-BALLSDRAM DDR3128Mx16 DDR3+MVDD+MVDDR1RP1ARP1BRP1CRP1DRP3ARP3BRP3CRP3DRP5ARP5BRP5CRP5DRP7ARP7BRP7CRP7DR94587658765120R120R120R120R120R120R120R120R120R120R120R120R120R120R120R120R120R120RM_MAA10BA2M_MAA11M_MAA12BA1M_MAA9M_MAA6M_MAA8M_MAA4M_MAA14M_MAA1BA0M_MAA0M_MAA13M_MAA2M_MAA3M_MAA7M_MAA5R2RP2ARP2BRP2CRP2DRP4ARP4BRP4CRP4DRP6ARP6BRP6CRP6DRP8ARP8BRP8CRP8DR76587658765120R120R120R120R120R120R120R120R120R120R120R120R120R120R120R120R120R120RR2014.99KVREFC_U201R2024.99KC201100nF_6.3VR2034.99KVREFC_U202R2054.99KVREFC_U401R2074.99KVREFC_U402R2084.99KC204100nF_6.3V(5)M_DQMA#[7..0]M_DQMA#0M_DQMA#1M_DQMA#2M_DQMA#3M_DQMA#4M_DQMA#5M_DQMA#6M_DQMA#7(5)M_QSA[7..0]M_QSA0M_QSA1M_QSA2M_QSA3M_QSA4M_QSA5M_QSA6M_QSA7(5)M_QSA#[7..0]M_QSA#0M_QSA#1M_QSA#2M_QSA#3M_QSA#4M_QSA#5M_QSA#6M_QSA#7R2044.99KC202100nF_6.3VR2064.99KC203100nF_6.3VBB+MVDD+MVDD+MVDD+MVDDR2094.99KVREFD_U201R2104.99KC205100nF_6.3VR2114.99KVREFD_U202R2134.99KVREFD_U401R2154.99KVREFD_U402R2164.99KC208100nF_6.3VR2124.99KC206100nF_6.3VR2144.99KC207100nF_6.3V+MVDDC3011uF_6.3VC3021uF_6.3VC3031uF_6.3VC3041uF_6.3VC3051uF_6.3VC351100nF_6.3VC352100nF_6.3VC353100nF_6.3V+MVDD+MVDDC3111uF_6.3VC3121uF_6.3VC3131uF_6.3VC3141uF_6.3VC3151uF_6.3VC356100nF_6.3VC357100nF_6.3VC358100nF_6.3VC3211uF_6.3VC3221uF_6.3VC3231uF_6.3VC3241uF_6.3VC3251uF_6.3VC361100nF_6.3VC362100nF_6.3VC363100nF_6.3V+MVDDC3311uF_6.3VC3321uF_6.3VC3331uF_6.3VC3341uF_6.3VC3351uF_6.3VC366100nF_6.3VC367100nF_6.3VC368100nF_6.3V(5)CLKA0R22156RR22256RAC20910nF+MVDD+MVDDMC381MC382MC383MC384+MVDD+MVDDMC391MC392MC393MC394A(5)CLKA#0C381C382C383C384C391C392C393C394(5)CLKA1R22356RR22456R(5)CLKA#1C21010nFCONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.© 2007 Advanced Micro DevicesAdvanced Micro Devices AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
1 Commerce Valley Drive Eastwith AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
Markham, Ontarioother than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
Date:Wednesday, February 24, 2010regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
Sheet6purpose, and disclaims responsibility forany consequences resulting
of12from use of the information included herein.4.7uF_6.3V4.7uF_6.3V4.7uF_6.3V4.7uF_6.3V4.7uF_6.3V4.7uF_6.3V4.7uF_6.3V4.7uF_6.3V10uF_4VOverlap10uF_4V10uF_4V10uF_4V10uF_4VOverlap10uF_4V10uF_4V10uF_4VRev1Title2Cedar DDR3 MxM3.01Doc No.105-C077xx-00B543
54321PLACE CAPS ON THIS PAGE AS CLOSE TO CONNECTOR AS POSSIBLE+PWR_SRCC5976100nF_50V+VDDR3+5VRUNR6227100KDNI63C59801uF_6.3VC5981100nF_6.3VPEX_STD_SW#Q5536A2142N7002DNI2N7002DNIQ5536B5DVI_HPD(2)DDCDATA_AUX3N(2)DDCCLK_AUX3PR62254.7KSTRAP OPTIONS FROM MOTEHRBOARD+VDDR3PCIE_TXN15PCIE_TXP15PCIE_TXN14PCIE_TXP14PCIE_TXN13PCIE_TXP13PCIE_TXN12PCIE_TXP12PCIE_TXN11PCIE_TXP11PCIE_TXN10PCIE_TXP10PCIE_TXN9PCIE_TXP9PCIE_TXN8PCIE_TXP8PCIE_TXN7PCIE_TXP7CJ1AE1E3C59791nF729343454749563656769783858789975975379759222923392449255926692779281PWR_SRC_E1GND_E3Part 1 of 2+VDDR3PWR_SRC_E2GND_E4PRSNT_R#_2WAKE#_4PWR_GOOD_6PWR_EN_8RSVD_10RSVD_12RSVD_14RSVD_16PWR_LEVEL_18TH_OVERT#_20TH_ALERT#_22TH_PWM_24GPIO0_26GPIO1_28GPIO2_30SMB_DAT_32SMB_CLK_34GND_36OEM_38OEM_40OEM_42OEM_44GND_46PEX_TX15#_48PEX_TX15_50GND_52PEX_TX14#_54PEX_TX14_56GND_58PEX_TX13#_60PEX_TX13_62GND_64PEX_TX12#_66PEX_TX12_68GND_70PEX_TX11#_72PEX_TX11_74GND_76PEX_TX10#_78PEX_TX10_80GND_82PEX_TX9#_84PEX_TX9_86GND_88PEX_TX8#_90PEX_TX8_92GND_94PEX_TX7#_96PEX_TX7_98GND_100PEX_TX6#_102PEX_TX6_104GND_106PEX_TX5#_108PEX_TX5_110GND_112PEX_TX4#_114PEX_TX4_116GND_118PEX_TX3#_120PEX_TX3_122GND_124GND_134PEX_TX2#_136PEX_TX2_138GND_140PEX_TX1#_142PEX_TX1_144GND_146PEX_TX0#_148PEX_TX0_150GND_152CLK_REQ#_154PEX_RST#_156VGA_DDC_DAT_158VGA_DDC_CLK_160VGA_VSYC_162VGA_HSYC_164GND_166VGA_RED_168VGA_GREEN_170VGA_BLUE_172GND_174LVDS_LCLK#_176LVDS_LCLK_178GND_180LVDS_LTX3#_182LVDS_LTX3_184GND_186LVDS_LTX2#_188LVDS_LTX2_190GND_192LVDS_LTX1#_194LVDS_LTX1_196GND_198LVDS_LTX0#_200LVDS_LTX0_202GND_204DP_D_L0#_206DP_D_L0_208GND_210DP_D_L1#_212DP_D_L1_214GND_216DP_D_L2#_218DP_D_L2_220GND_222DP_D_L3#_224DP_D_L3_226GND_228DP_D_AUX#_230DP_D_AUX_232DP_C_HPD_234DP_D_HPD_236RSVD_238RSVD_240RSVD_242GND_244DP_B_L0#_246DP_B_L0_248GND_250DP_B_L1#_252DP_B_L1_254GND_256DP_B_L2#_258DP_B_L2_260GND_262DP_B_L3#_264DP_B_L3_266GND_268DP_B_AUX#_270DP_B_AUX_272DP_B_HPD_274DP_A_HPD_2763V3_2783V3_280E2E424684464852646668728486889888238248258268278280R6095100KPWRGOOD(8)RUNPWROK(8,9,10)+VDDR3100KR1130+VDDR3100KR6125GPIO5_AC_BATT(2)CTFb(2)GPIO17_THERMAL_INT(2)MB_GPIO0MB_GPIO1MB_GPIO2SMB_DATSMB_CLKMB_GPIO0(2)MB_GPIO1(2)MB_GPIO2(2)D(2,8)GPIO0(2,8)GPIO1(2,4)FPVCCDPNL_PWR_ENPNL_BL_ENPNL_BL_PWMR62264.7KPCIE_TXN6PCIE_TXP6(1)PCIE_REFCLKP(1)PCIE_REFCLKN(1)PCIE_RXP[15..0](1)PCIE_RXN[15..0](1)PCIE_TXP[15..0](1)PCIE_TXN[15..0]PCIE_REFCLKPPCIE_REFCLKNPCIE_RXP[15..0]PCIE_RXN[15..0]PCIE_TXP[15..0]PCIE_TXN[15..0]PCIE_TXN2PCIE_TXP2PCIE_TXN1PCIE_TXP1PCIE_TXN0PCIE_TXP0(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)TXOUT_L0-TXOUT_L0+TXOUT_L1-TXOUT_L1+TXOUT_L2-TXOUT_L2+TXOUT_L3-TXOUT_L3+TXCLK_L-TXCLK_L+TXOUT_U0-TXOUT_U0+TXOUT_U1-TXOUT_U1+TXOUT_U2-TXOUT_U2+TXOUT_U3-TXOUT_U3+TXCLK_U-TXCLK_U+TXOUT_L0-TXOUT_L0+TXOUT_L1-TXOUT_L1+TXOUT_L2-TXOUT_L2+TXOUT_L3-TXOUT_L3+TXCLK_L-TXCLK_L+TXOUT_U0-TXOUT_U0+TXOUT_U1-TXOUT_U1+TXOUT_U2-TXOUT_U2+TXOUT_U3-TXOUT_U3+TXCLK_U-TXCLK_U+PCIE_REFCLKNPCIE_REFCLKPPCIE_TXN5PCIE_TXP5PCIE_TXN4PCIE_TXP4PCIE_TXN3PCIE_TXP35V_15V_35V_55V_75V_9GND_11GND_13GND_15GND_17PEX_STD_SW#_19VGA_DISABLE#_21PNL_PWR_EN_23PNL_BL_EN_25PNL_PWM_27HDMI_CEC_29DVI_HPD_31LVDS_DDC_DAT_33LVDS_DDC_CLK_35GND_37OEM_39OEM_41OEM_43OEM_45GND_47PEX_RX15#_49PEX_RX15_51GND_53PEX_RX14#_55PEX_RX14_57GND_59PEX_RX13#_61PEX_RX13_63GND_65PEX_RX12#_67PEX_RX12_69GND_71PEX_RX11#_73PEX_RX11_75GND_77PEX_RX10#_79PEX_RX10_81GND_83PEX_RX9#_85PEX_RX9_87GND_89PEX_RX8#_91PEX_RX8_93GND_95PEX_RX7#_97PEX_RX7_99GND_101PEX_RX6#_103PEX_RX6_105GND_107PEX_RX5#_109PEX_RX5_111GND_113PEX_RX4#_115PEX_RX4_117GND_119PEX_RX3#_121PEX_RX3_123GND_125GND_133PEX_RX2#_135PEX_RX2_137GND_139PEX_RX1#_141PEX_RX1_143GND_145PEX_RX0#_147PEX_RX0_149GND_151PEX_REFCLK#_153PEX_REFCLK_155GND_157RSVD_159RSVD_161RSVD_163RSVD_165RSVD_167LVDS_UCLK#_169LVDS_UCLK_171GND_173LVDS_UTX3#_175LVDS_UTX3_177GND_179LVDS_UTX2#_181LVDS_UTX2_183GND_185LVDS_UTX1#_187LVDS_UTX1_189GND_191LVDS_UTX0#_193LVDS_UTX0_195GND_197DP_C_L0#_199DP_C_L0_201GND_203DP_C_L1#_205DP_C_L1_207GND_209DP_C_L2#_211DP_C_L2_213GND_215DP_C_L3#_217DP_C_L3_219GND_221DP_C_AUX#_223DP_C_AUX_225RSVD_227RSVD_229RSVD_231RSVD_233RSVD_235RSVD_237RSVD_239RSVD_241RSVD_243RSVD_245RSVD_247RSVD_249GND_251DP_A_L0#_253DP_A_L0_255GND_257DP_A_L1#_259DP_A_L1_261GND_263DP_A_L2#_265DP_A_L2_267GND_269DP_A_L3#_271DP_A_L3_273GND_275DP_A_AUX#_277DP_A_AUX_279PRSNT_L#_281MXM 3 EDGECONNPCIE_RXN15PCIE_RXP15PCIE_RXN14PCIE_RXP14PCIE_RXN13PCIE_RXP13PCIE_RXN12PCIE_RXP12PCIE_RXN11PCIE_RXP11PCIE_RXN10PCIE_RXP10PCIE_RXN9PCIE_RXP9PCIE_RXN8PCIE_RXP8PCIE_RXN7PCIE_RXP7PCIE_RXN6PCIE_RXP6PCIE_RXN5PCIE_RXP5PCIE_RXN4PCIE_RXP4PCIE_RXN3PCIE_RXP3CPNL_BL_PWMPNL_BL_ENR6103MR6104R61040R0RDNI0RBLON_PWM(2)GPIO7_BLON(2)Mechanical KeyPCIE_RXN2PCIE_RXP2PCIE_RXN1PCIE_RXP1PCIE_RXN0PCIE_RXP0CLK_REQ#PCIE_RST#(1)DDC5DATA(2)DDC5CLK(2)VSYNC_DAC1(2,8)HSYNC_DAC1(2,8)VGA_REDVGA_GRNVGA_BLUTXCLK_L-TXCLK_L+TXOUT_L3-TXOUT_L3+TXOUT_L2-TXOUT_L2+TXOUT_L1-TXOUT_L1++VDDR3TXOUT_L0-TXOUT_L0+R526100KSMB_CLK+VDDR3R527100KSMB_DATDP_C_HPDR71230RDNIGPIO3_SMBDATA(2)R71220RDNIGPIO4_SMBCLK(2)VGA_RED(2)VGA_GRN(2)VGA_BLU(2)R61214.7KR61224.7KTXCLK_U-TXCLK_U+TXOUT_U3-TXOUT_U3+TXOUT_U2-TXOUT_U2+TXOUT_U1-TXOUT_U1+TXOUT_U0-TXOUT_U0+(2)TX5M_DPB0N(2)TX5P_DPB0P(2)TX4M_DPB1N(2)TX4P_DPB1P(2)TX3M_DPB2N(2)TX3P_DPB2P(2)TXCBM_DPB3N(2)TXCBP_DPB3P(2)DDCDATA_AUX2N(2)DDCCLK_AUX2P+VDDR3BB(2)HPD1R6124100KDP_A_HPD(2)GPIO14_HPD2R6116100KDP_C_HPDA(2)TX2M_DPA0N(2)TX2P_DPA0P(2)TX1M_DPA1N(2)TX1P_DPA1PA(2)GPIO18_HPD3R6102100KDVI_HPD(2)TX0M_DPA2N(2)TX0P_DPA2P(2)TXCAM_DPA3N(2)TXCAP_DPA3P(2)DDCDATA_AUX1N(2)DDCCLK_AUX1PJ1BMTG1MTG2MTG3MTG4MTG5MTG6Part 2 of 2DP_A_HPD+3VRUNC6016C601710uF_X6S1uF_6.3VMTG1MTG2MTG3MTG4MTG5MTG6MXM 3 EDGECONNCONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.© 2007 Advanced Micro DevicesAdvanced Micro Devices AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
1 Commerce Valley Drive Eastwith AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
Markham, Ontarioother than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
Date:Wednesday, February 24, 2010regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
Sheet7purpose, and disclaims responsibility forany consequences resulting
of12from use of the information included 1Title5432Cedar DDR3 MxM3.01Doc No.105-C077xx-00B
54321Voltage Settings and Power Play+3VRUND+3VRUNDR124010K(2,9)GPIO20_PCNTL1(2,9)GPIO15_PCNTL0R124110KDNI(10)VID1_MVDD(10)VID0_MVDDR124210KDNIR124310KDNILDO1Vin = +1.5V +/-2%Vout = +1.0V +/- 2%Iout = 1.5A RMS MAX (TBV)PCB: 50 to 70mm sq. copper area for coolingMR1240MR124110K10KDNIMR1242MR124310K10KU851PWRGOODLDO1_EN+MVDD+5VRUN1234POKGND#8ENFBVINVOUTCNTLREFINGND#9uP7706U8+5VRUN+1.0V_REG+MVDDR85310KMU851C87659LDO1_FB+1.0V_REGMR851+1.0V_REGB8510RDNI220R_2ADNI+VDDC Overlap
R187659LDO1_FBR8552.67K(7)PWRGOODLDO1_EN1234POKGND#8ENFBVINVOUTCNTLREFINGND#9UP7706ADC8C85533pF_50VC85110uF_X6SC854100nF_6.3VOverlapPIN STRAPS+VDDR3(2,7)GPIO0(2,7)GPIO1GPIO0GPIO1GPIO2GPIO9GPIO11GPIO12GPIO13GPIO22V1SYNCH1SYNCV2SYNCH2SYNCR6134R6135R6136R6138R6139R6140R6141R6147R6142R6143R6145R614610K10K10K10K10K10K10K10KBIF_GEN2_EN_A(2,7)VSYNC_DAC1(2,7)HSYNC_DAC110K10KBIF_VGA DIS10K10KDNIROMIDCFG[2:0]GPIO[13:11]GPIO9VGA Control0: VGA controller capacity enabled1: VGA controller capacity disabled
(for multi-GPU)CR20603/0802Overlap
footprintsC8581uF_6.3VMC856C85610uF_6.3V10uF_X6SR85410.2KCONFIGURATION STRAPSALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESETDNIDNIDNITX_DEEMPH_ENGPIO1STRAPSTX_PWRS_ENBPINGPIO0DESCRIPTION OF DEFAULT SETTINGSTransmitter Power Savings EnableGPIO0 and GPIO1 pull
ups need to be stuffedwith Q5536 if systemPCIE Transmitter De-emphasis Enableboard is controlling the0: Tx de-emphasis disabledPCIE swing.0: 50% Tx output swing1: Full Tx output swing1: Tx de-emphasis enabledVout = Vref x (1 + R1/R2)Vref = 0.8V(2)GPIO2(2)GPIO9(2)GPIO11(2)GPIO12(2)GPIO13(2)GPIO22DefaultSetting11GPIO2PCIE Gen2 Enable0: Advertises the PCIE device as 2.5GT/s capable at power-on1: Advertises the PCIE device as 5.0GT/s capable at power-on1LDO2Vin = +3.3V +/-6%Vout = +1.8V +/- 2%Iout = 0.8A RMS MAX (TBV)(2)VSYNC_DAC2(2)HSYNC_DAC2PCB: 50 to 70mm sq. copper area for coolingBGPIO9 pull up needsto be stuffed withQ5537 if systemboard is controllingthe VGA capacity0Serial ROM type or Memory Aperture Size SelectIf GPIO22 = 0, defines memory aperture sizeIf GPIO22 = 1, defines ROM type100 - 512Kbit M25P05A (ST)101 - 1Mbit M25P10A (ST)101 - 2Mbit M25P20 (ST)101 - 4Mbit M25P40 (ST)101 - 8Mbit M25P80 (ST)100 - 512Kbit Pm25LV512 (Chingis)101 - 1Mbit Pm25LV010 (Chingis)XXXBMU861+3VRUNPWRGOODVDDC_POKLDO2_VIN+5VRUNMR868R8682.4R_1210_0.5W1R+5VRUN1234POKGND#8ENFBVINVOUTCNTLREFINGND#987659LDO2_FB+1.8V_REGBIOS_ROM_ENGPIO22Enable external BIOS ROM device0: Disabled1: Enabled1+3VRUNUP7706ADC8+1.8V_REG+1.8V_REGAUD[1]AUD[0]HSYNCVSYNCOverlap
footprintsUse two 2.4R 1/2W <=5%MR869R8692.4R_1210_0.5W1RR86110K Overlap
U861R587659LDO2_FBR86513.0K(7)PWRGOOD(9)VDDC_POKLDO2_VIN1234POKGND#8ENFBVINVOUTCNTLREFINGND#9uP7706U8C86533pF_50VC86110uF_X6SC864100nF_6.3VVDDR3 GATINGVIP_DEVICE_STRAP_DISV2SYNC00 - No audio function01 - Audio for DP only10 - Audio for DP and HDMI if dongle is detected11 - Audio for both DP and HDMIHDMI must only be enabled on systems that are legally entitled. It is the
responsibility of the system designer to ensure that the system is entitled to
support this Device Strap Disable0: Slave VIP host port devices present1: No slave VIP host port devices reporting presence1R4R6194R86410.2K+3VRUN20RDNISMS_EN_HARD+VDDR3Q55313Si2301BDSH2SYNCReserved00603/0802Overlap
footprintsMC866C86610uF_6.3V10uF_X6SC8681uF_6.3VVout = Vref x (1 + R5/R4)Vref = 0.8VR6196100K3A1Q5534MMBT3904A(7,9,10)RUNPWROKR61995.1K1C60531uF_6.3V2CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.© 2007 Advanced Micro DevicesAdvanced Micro Devices AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
1 Commerce Valley Drive Eastwith AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
Markham, Ontarioother than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
Date:Wednesday, February 24, 2010regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
Sheet8purpose, and disclaims responsibility forany consequences resulting
of12from use of the information included 1Title5432Cedar DDR3 MxM3.01Doc No.105-C077xx-00B
87654321DINPUT CAP+PWR_SRC+PWR_SRC+PWR_SRC+PWR_SRC+PWR_SRC+PWR_SRCMR607C6642.2uF_16VX7R, 12061.3mm HiC6842.2uF_16VX7R, 12061.3mm HiC6832.2uF_16VX7R, 12061.3mm HiC6422.2uF_16VX7R, 12061.3mm HiC6822.2uF_16VX7R, 12061.3mm Hi+5VRUNR6072R2OR6000R2R2Dshare pad+VCCTop Side Hmax=1.5mmTop Side Hmax=1.5mm+PW_VDDC_LGDR6158.06K+PW_VDDC_MC607100nF603C605100nF0603+PWR_SRC+5VRUN2D601R6180R1BAT54KFILMBOOT11917U6012018OC602100nF603CSPR6041KCurrent SensingC604100nF_6.3VC606100nF_6.3VCSN15CSNR605221RR62010KEN/PSMC60915nFR62110KRUNPWROK(7,8,10)Cshare pad+VDDAVDDC_CCSPVDDC_CCSN Differential trace from InductorLGDROOPPHASEBOOTCQ601BSC120N03LSG95678+PW_VDDC_HGD2VCCCSP16UGEN/PSM144321+VDDCL6010.56UHSunken Inductor10x10mmR603(8)VDDC_POK3POKVID113GPIO20_PCNTL1(2,8)GPIO15_PCNTL0(2,8)+PWR_SRCOC6006.8nF_25VOR601VDDC_COMPC6116.8nF_25V8.06KVDDC_VIN21NS605NS_VIASense Point+PW_VDDC_HGD8.06KVDDC_RSET3UR6020RVDDC_RSET24+PW_VDDC_MRSET3VID012C60315nF22R602NS603NS_VIA11Sense Point8.06K5MODE/RSET2REFIN/RSET1COMP11RTVDDC_RSET16VDDC_RSET078VDDC_FBRTN9Route like
differential pairPlace across
Q613, Q614VDDC_RTQ602BSC030N03LS G603PISCES_MR_DR10C6081UF_16V95678FBGND2GND1FBRTNRSET0R619300R805NS604NS_VIAC60215nF2221Type IIICompensationR6128.06KR6140RR6133.65KVDDC_FBUR6050RR611RFB1C612150PFR6090RReserve for
Loop TestVDDC_CCSNVDDC_CCSP+PW_VDDC_LGDRC snubber values shownare for reference only,tuning is requiredC6136.8nF_25V10K4321+VDDC12R6018.06KR600R616UR600OC601VDDC_SVC60115nFC60015nFC61615nFR6060R603VDDC_FB_TRACENS_VIANS601Sense PointB0R8.06K8.06K15nFB+PW_VDDC_MOUTPUT CAP+VDDCC639330uFSP/POSCAP,
SMT 7343Max 1.5mm_HC640330uFSP/POSCAP,
SMT 7343Max 1.5mm_HC641220UF_2VSP/POSCAP,
SMT 7343Max 1.2mm_HTop Side Hmax=1.5mmLOW PROFILE POSCAP+VDDCBottom Side Hmax=1.2mmAC64415nF402C64315nF402AMLCCCONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.© 2007 Advanced Micro DevicesAdvanced Micro Devices AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
1 Commerce Valley Drive Eastwith AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
Markham, Ontarioother than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
Date:Wednesday, February 24, 2010regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
Sheet9purpose, and disclaims responsibility forany consequences resulting
of12from use of the information included 1Title876543Cedar DDR3 MxM3.02Doc No.1105-C077xx-00B
87654321DINPUT CAP+PWR_SRC+PWR_SRC+PWR_SRC+PWR_SRC+PWR_SRCDMR707+5VRUNR707C7212.2uF_16VX7R, 12061.3mm HiC7232.2uF_16VX7R, 12061.3mm HiC7322.2uF_16VX7R, 12061.3mm HiC7251uF_16VX7R, 12060.95mm Hi+PW_MVDDC_LGDTop Side Hmax=1.5mmBottom Side Hmax=1.2mm+PW_MVDDC_MC707100nF603C705100nF0603R7180R2D7011BAT54KFILMBOOT120192R22R2OR7000Rshare padR7158.06K402share padOC702100nF603CSPR7041KCurrent SensingMVDDC_CCSPMVDDC_CCSN Differential trace from InductorC706100nF_6.3VCSN15CSNR705221RR72010KEN/PSMC70915nFR72110KC17U7011816+VDDA+VCCLGDROOPPHASE+5VRUNVCCCSPC704100nF_6.3VBOOTRUNPWROK(7,8,9)+PWR_SRC+PW_MVDDC_HGD2UGEN/PSM14C395678Q701BSC120N03LSGPOKVID113VID1_MVDD(8)VID0_MVDD(8)+PWR_SRCOC7006.8nF_25VOR701MVDDC_COMPC7116.8nF_25V8.06KMVDDC_VIN21NS705NS_VIASense PointR7038.06KMVDD_RSET3UR7020RMVDD_RSET24RSET3VID012C70315nFSMML701L7011.5uH_11A+MVDD+PW_MVDDC_M2.2uH_8AOverlapR7028.06K5MODE/RSET2REFIN/RSET1COMP114321C70215nF2221GND2GND1+PW_MVDDC_HGDFBRTNRSET0Type IIICompensationRTFBMVDD_RSET16MVDD_RSET07MVDD_FBRTN9PISCES_MR_DRR719300R805C7081UF_16V603R7128.06KR7140RR7133.65KMVDDC_FBUR7050RR711RFB1C712150PFR7090RReserve for
Loop Test8NS704NS_VIA11NS703NS_VIASense PointMVDD_RT221095678C7136.8nF_25V10K+MVDD12R701R700R716UR700OC701MVDDC_SVC70115nFC70015nFC71615nFQ702BSC030N03LS GR7060R603MVDDC_FB_TRACENS_VIANS701Sense Point0R8.06K8.06K8.06K15nFPlace across
Q613, Q614Route like
differential pair4321+PW_MVDDC_MBMVDDC_CCSNMVDDC_CCSP+PW_MVDDC_LGDRC snubber values shownare for reference only,tuning is requiredBOUTPUT CAP+MVDD+MVDDC737330uFSP/POSCAP,
SMT 7343Max 1.5mm_HC74115nF402Top Side Hmax=1.5mmMLCCLOW PROFILE POSCAPAACONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.© 2007 Advanced Micro DevicesAdvanced Micro Devices AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
1 Commerce Valley Drive Eastwith AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
Markham, Ontarioother than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
Date:Wednesday, February 24, 2010regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
Sheet10purpose, and disclaims responsibility forany consequences resulting
of12from use of the information included 1Title876543Cedar DDR3 MxM3.02Doc No.1105-C077xx-00B
54321MEMORY CHANNEL ADDR3 4pcs 64Mx16DDCH ALVTMDPDL LVDSDPE/FDDCAUX3LVDSLVDS_LTXx/LTXx#LVDS_UTXx/UTXx#LVDS_DDC_CLK/DATDVI_HPDPOWER REGULATORSFrom +PWR_SRC+VDDC, +MVDDHPD3TMDPABDP_ADPADP_A_Lx/Lx#DP_A_AUX/AUX#DP_A_HPDCFrom +3VRUN+1.8V_REG, VDDR3CDDCAUX1From +VDDCVDDC, VDDCIFrom +MVDD+1.0V_REG, VDDR1, MVDDQ/CFrom +1.8V_REG
VDDR4, VDD_CT, TSVDD,
PCIE_VDDR, PCIE_PVDD,
DPLL_PVDD, DPx_PVDD,
DPx_VDD18, MPV18, SPV18,
AVDD, VDD1DIStrapsGPIOHPD1DP_CBIOSROMDPBDDCAUX2HPD2DP_C_Lx/Lx#DP_C_AUX/AUX#DP_C_HPDXTALXTALIN/OUTDAC2CRT DAC1VGAVGA_RED/GREEN/BLUEVGA_DDC_CLK/DATFrom +1.0V_REGPCIE_VDDC, DPLL_VDDC,DPx_VDD10, SPV10Dynamic VDDCGPIO20/15DDC5V/HSyncVGA_VSYNC/HSYNCPOWER DELIVERYMxM3.0 Source+3VRUNBThermalGPIO3, GPIO4SMB_CLK/DATB+5VRUN+PWR_SRCCedar3V3 delayed circuitGPIO17TH_ALERT#GPIO19_CTFTH_OVERT#PCIESMPS EnableCircuit3VRUN5VRUNPWR_SRCMxM3.0 ConnectorMxM3.0 Cedar DDR3 512MBDP DP DL-LVDS VGAAACONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.© 2007 Advanced Micro DevicesAdvanced Micro Devices AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
1 Commerce Valley Drive Eastwith AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
Markham, Ontarioother than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
Date:Wednesday, February 24, 2010regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
Sheet11purpose, and disclaims responsibility forany consequences resulting
of12from use of the information included 1Title5432Cedar DDR3 MxM3.01Doc No.105-C077xx-00B
54321TitleSchematic :Wednesday, February 24, 2010RevCedar DDR3 MxM3.0REVISION HISTORYD105-C077xx-00BNOTE:This schematic represents the PCB, it does not represent any specific Stuffing options (component values, DNI’s, …) please consult the product specific contact AMD representative to obtain latest BOM closest to the application desired.1SchRev01PCBRev00A00BDDate09/10/0610/02/24Initial design for Cedar DDR3 MxM3.0 Type A-4LREVISION DESCRIPTIONLayout change only (Move GPIO4_SMBCLK to the bottom layer)CCBBAA54321
2024年2月20日发(作者：不语柳)
54321DDU1A(7)PCIE_REFCLKP(7)PCIE_REFCLKNPCIE_REFCLKPPCIE_REFCLKNPCIE_RXP0PCIE_RXN0PCIE_RXP1PCIE_RXN1PCIE_RXP2PCIE_RXN2PCIE_RXP3PCIE_RXN3PCIE_RXP4PCIE_RXN4PCIE_RXP5PCIE_RXN5PCIE_RXP6PCIE_RXN6PCIE_RXP7PCIE_RXN7PCIE_RXP8PCIE_RXN8PCIE_RXP9PCIE_RXN9PCIE_RXP10PCIE_RXN10PCIE_RXP11PCIE_RXN11PCIE_RXP12PCIE_RXN12PCIE_RXP13PCIE_RXN13PCIE_RXP14PCIE_RXN14PCIE_RXP15PCIE_RXN15AF30AE31AE29AD28AD30AC31AC29AB28AB30AA31AA29Y28Y30W31W29V28V30U31U29T28T30R31R29P28P30N31N29M28M30L31L29K30PCIE_RX0PPCIE_RX0NPCIE_RX1PPCIE_RX1NPCIE_RX2PPCIE_RX2NPCIE_RX3PPCIE_RX3NPCIE_RX4PPCIE_RX4NPCIE_RX5PPCIE_RX5NPCIE_RX6PPCIE_RX6NPCIE_RX7PPCIE_RX7NPCIE_RX8PPCIE_RX8NPCIE_RX9PPCIE_RX9NPCIE_RX10PPCIE_RX10NPCIE_RX11PPCIE_RX11NPCIE_RX12PPCIE_RX12NPCIE_RX13PPCIE_RX13NPCIE_RX14PPCIE_RX14NPCIE_RX15PPCIE_RX15NPCIE_TX0PPCIE_TX0NPCIE_TX1PPCIE_TX1NPCIE_TX2PPCIE_TX2NPCIE_TX3PPCIE_TX3NPCIE_TX4PPCIE_TX4NPCIE_TX5PPCIE_TX5NPCIE_TX6PPCIE_TX6NPCIE_TX7PPCIE_TX7NPCIE_TX8PPCIE_TX8NPCIE_TX9PPCIE_TX9NPCIE_TX10PPCIE_TX10NPCIE_TX11PPCIE_TX11NPCIE_TX12PPCIE_TX12NPCIE_TX13PPCIE_TX13NPCIE_TX14PPCIE_TX14NPCIE_TX15PPCIE_TX15NAH30AG31AG29AF28AF27AF26AD27AD26AC25AB25Y23Y24AB27AB26Y27Y26W24W23V27U26U24U23T26T27T24T23P27P26P24P23M27N26PCIE_TXP0PCIE_TXN0PCIE_TXP1PCIE_TXN1PCIE_TXP2PCIE_TXN2PCIE_TXP3PCIE_TXN3PCIE_TXP4PCIE_TXN4PCIE_TXP5PCIE_TXN5PCIE_TXP6PCIE_TXN6PCIE_TXP7PCIE_TXN7PCIE_TXP8PCIE_TXN8PCIE_TXP9PCIE_TXN9PCIE_TXP10PCIE_TXN10PCIE_TXP11PCIE_TXN11PCIE_TXP12PCIE_TXN12PCIE_TXP13PCIE_TXN13PCIE_TXP14PCIE_TXN14PCIE_TXP15PCIE_TXN15C(7)PCIE_RXP[15..0](7)PCIE_RXN[15..0](7)PCIE_TXP[15..0]CPCIE_RXP[15..0]PCIE_RXN[15..0]PCIE_TXP[15..0]PCIE_TXN[15..0](7)PCIE_TXN[15..0]PCI EXPRESS INTERFACEBBCLOCKPCIE_REFCLKPPCIE_REFCLKNAK30AK32PCIE_REFCLKPPCIE_REFCLKNCALIBRATIONPCIE_CALRPR71111KPWRGOOD_GPUPCIE_RST#N10AL27PWRGOODPERSTBPark-S3PCIE_CALRNY22PCIE_CALRPAA22PCIE_CALRNR10091.27KR10102.0K+1.0V_REG(7)PCIE_RST#AACONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.© 2007 Advanced Micro DevicesAdvanced Micro Devices AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
1 Commerce Valley Drive Eastwith AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
Markham, Ontarioother than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
Date:Wednesday, February 24, 2010regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
Sheet1purpose, and disclaims responsibility forany consequences resulting
of12from use of the information included 1Title5432Cedar DDR3 MxM3.01Doc No.105-C077xx-00B
54321U1BU1FR6216Y11AE9L9N9AE8AD9AC10AD7AC8AC7AB9AB8AB7AB4AB2Y8Y7TXCAP_DPA3PTXCAM_DPA3NDVCLKDVCNTL_0DVCNTL_1DVCNTL_2DVDATA_12DVDATA_11DVDATA_10DVDATA_9DVDATA_8DVDATA_7DVDATA_6DVDATA_5DVDATA_4DVDATA_3DVDATA_2DVDATA_1DVDATA_0TX0P_DPA2PTX0M_DPA2NTX1P_DPA1PTX1M_DPA1NTX2P_DPA0PTX2M_DPA0NTXCBP_DPB3PTXCBM_DPB3NTX3P_DPB2PTX3M_DPB2NTX4P_DPB1PTX4M_DPB1NTX5P_DPB0PTX5M_DPB0NW6V6AC6AC5AA5AA6DPC_PVDDDPC_PVSSDPC_VDD18#1DPC_VDD18#2DPC_VDD10#1DPC_VDD10#2DPCTXCCP_DPC3PTXCCM_DPC3NTX0P_DPC2PTX0M_DPC2NTX1P_DPC1PTX1M_DPC1NU1W1U3Y6AA1DPC_VSSR#1DPC_VSSR#2DPC_VSSR#3DPC_VSSR#4DPC_VSSR#5TX2P_DPC0PTX2M_DPC0NDPC_CALRV4U5W3V2Y4W5AA3Y2J8AF2AF4AG3AG5AH3AH1AK3AK1AK5AM3AK6AM5AJ7AH6AK8AL7TXCAP_DPA3P(7)TXCAM_DPA3N(7)TX0P_DPA2P(7)TX0M_DPA2N(7)TX1P_DPA1P(7)TX1M_DPA1N(7)TX2P_DPA0P(7)TX2M_DPA0N(7)TXCBP_DPB3P(7)TXCBM_DPB3N(7)TX3P_DPB2P(7)TX3M_DPB2N(7)TX4P_DPB1P(7)TX4M_DPB1N(7)TX5P_DPB0P(7)TX5M_DPB0N(7)LVDS CONTROLVARY_BLDIGONAB11AB1210KBLON_PWM(7)FPVCC(4,7)DVODPATXCLK_UP_DPF3PTXCLK_UN_DPF3NTXOUT_U0P_DPF2PTXOUT_U0N_DPF2NTXOUT_U1P_DPF1PTXOUT_U1N_DPF1NTXOUT_U2P_DPF0PTXOUT_U2N_DPF0NTXOUT_U3PTXOUT_U3NLVTMDPTXCLK_LP_DPE3PTXCLK_LN_DPE3NTXOUT_L0P_DPE2PTXOUT_L0N_DPE2NTXOUT_L1P_DPE1PTXOUT_L1N_DPE1NTXOUT_L2P_DPE0PTXOUT_L2N_DPE0NTXOUT_L3PTXOUT_L3NAH20AJ19AL21AK20AH22AJ21AL23AK22AK24AJ23TXCLK_U+(7)TXCLK_U-(7)TXOUT_U0+(7)TXOUT_U0-(7)TXOUT_U1+(7)TXOUT_U1-(7)TXOUT_U2+(7)TXOUT_U2-(7)TXOUT_U3+(7)TXOUT_U3-(7)D+1.8V_REGDR608810KR608710KMEM_ID1MEM_ID0DPBDVPDATA[1:0] = 0x0 for Hynix 23E22387MR12DVPDATA[1:0] = 0x1 for Samsung 23E42387ME12AL15AK14AH16AJ15AL17AK16AH18AJ17AL19AK18TXCLK_L+(7)TXCLK_L-(7)TXOUT_L0+(7)TXOUT_L0-(7)TXOUT_L1+(7)TXOUT_L1-(7)TXOUT_L2+(7)TXOUT_L2-(7)TXOUT_L3+(7)TXOUT_L3-(7)Park-S3I2C+3VRUNR1R3SCLSDAGENERAL PURPOSE I/O(7,8)GPIO0(7,8)GPIO1(8)GPIO2(7)GPIO3_SMBDATA(7)GPIO4_SMBCLK(7)GPIO5_AC_BATTGPIO19_CTFR2610K(7)GPIO7_BLON(8)GPIO9(8)GPIO11(8)GPIO12(8)GPIO13(7)GPIO14_HPD2(8,9)GPIO15_PCNTL0(7)GPIO17_THERMAL_INT(7)GPIO18_HPD3(8,9)GPIO20_PCNTL1(8)GPIO22TP13TP14TP15TP16TP1735mil35mil35mil35mil35milR4310KGPIO0GPIO1GPIO2GPIO3_SMBDATGPIO4_SMBCLKGPIO5_AC_BATTGPIO7_BLONGPIO8GPIO8_ROMSOGPIO9GPIO9_ROMSIGPIO10GPIO10_ROMSCKGPIO11GPIO12GPIO13GPIO14_HPD2GPIO15_PCNTL0GPIO17_THERMAL_INTGPIO18_HPD3GPIO19_CTFGPIO20_PCNTL1GPIO22GPIO22_ROMCSBGPIO24_TRSTBGPIO25_TDIGPIO26_TCKGPIO27_TMSGPIO28_TDOTESTENU6U10T10U8U7T9T8T7P10P4P2N6N5N3Y9N1M4R6W10M2P8P7N8N7L6L5L3L1K4K7AF24AB13W8W9W7AD10AC14AB16GPIO_0GPIO_1GPIO_2GPIO_3_SMBDATAGPIO_4_SMBCLKGPIO_5_AC_BATTGPIO_6GPIO_7_BLONGPIO_8_ROMSOGPIO_9_ROMSIGPIO_10_ROMSCKGPIO_11GPIO_12GPIO_13GPIO_14_HPD2GPIO_15_PWRCNTL_0GPIO_16_SSINGPIO_17_THERMAL_INTGPIO_18_HPD3GPIO_19_CTFGPIO_20_PWRCNTL_1GPIO_21_BB_ENGPIO_22_ROMCSBGPIO_23_CLKREQBJTAG_TRSTBJTAG_TDIJTAG_TCKJTAG_TMSJTAG_TDOTESTENTESTEN_LEGACYGENERICAGENERICBGENERICCGENERICDGENERICE_HPD4HPD1PX_ENDAC2H2SYNCV2SYNCVDD2DIVSS2DIA2VDD+VDDR3A2VDDQ+1.8V_REGA2VSSQR5675R586C5685499RVREFAC16249R100nF_6.3VVREFGR2SETAL13AJ13AD19AC19AE20AE17AE19AG13HSYNC_DAC2(8)VSYNC_DAC2(8)BCR6097100K(7)CTFb3Q2612N7002_NL2RRBGGBBBBHSYNCVSYNCRSETAVDDAVSSQVDD1DIVSS1DIR2R2BG2G2BB2B2BCYCOMPAM26AK26AL25AJ25AH24AG25AH26AJ27AD22AG24AE22AE23AD23AM12AK12AL11AJ11AK10AL9AH12AM10AJ9RSETHSYNC_DAC1(7,8)VSYNC_DAC1(7,8)R5623499RR6118150RR6119150RR6120150RVGA_RED(7)VGA_GRN(7)VGA_BLU(7)CDAC1PLACE RGBTERMINATIONRESISTORS CLOSETO ASICAVDD(AVDD:70mA @ 1.8V)C56271uF_6.3VC56284.7uF_6.3V+1.8V_REGB10063BLM15BD121SN1VDD1DI(VDD1DI: 45mA @ 1.8V)C56101uF_6.3VC57084.7uF_6.3VB10064BLM15BD121SN1JTAG DEBUG PORTB(7)MB_GPIO0(7)MB_GPIO1(7)MB_GPIO2R5631R5632R56330RDNI0RDNI0RDNIGENERICAGENERICBGENERICCR562710KDNIR562810KDNIR562910KDNI(7)HPD1PLACE VREFGDIVIDER AND CAPCLOSE TO ASIC+1.8V_REGB10098BLM15BD121SN1DDC/AUX(DPLL_PVDD: 75mA @ 1.8V)C5784C57854.7uF_6.3V1uF_6.3VC5786100nF_6.3VDPLL_PVDDAF14AE14AD14XTALINXTALOUTAM28AK28AC22AB22PLL/CLOCKDPLL_PVDDDPLL_PVSSDPLL_VDDCXTALINXTALOUTXO_INXO_IN2DDC1CLKDDC1DATAAUX1PAUX1NDDC2CLKDDC2DATAAUX2PAUX2NAE6AE5AD2AD4AC11AC13AD13AD11AD20AC20AE16AD16AC1AC3ADDCCLK_AUX1P(7)DDCDATA_AUX1N(7)DPA+VDDR3BIOS1C5613100nF_6.3VU5508GPIO22GPIO81234CE#SOWP#GNDVCCHOLD#SCKSI8765GPIO10GPIO9113-C077xx-xxxVIDEO BIOSFIRMWAREBIOSDDCCLK_AUX2P(7)DDCDATA_AUX2N(7)DDCCLK_AUX3P(7)DDCDATA_AUX3N(7)DDC5CLK(7)DDC5DATA(7)DPB+1.0V_REGB10099BLM15BD121SN1(DPLL_VDDC: 125mA @ 1.0V)C57881uF_6.3VC5789100nF_6.3VDPLL_VDDCR6092211M43DDCCLK_AUX3PDDCDATA_AUX3NDDCCLK_AUX5PDDCDATA_AUX5NLVDSVGAPM25LV512A-100SCEC5973Y1C597412pF_50V27.000MHz_10PPM_30R12pF_50VT4T2DPLUSDMINUSTS_FDOTSVDDTSVSSTHERMALADDC6CLKDDC6DATA+1.8V_REG(TSVDD: 5mA @ 1.8V)C59241uF_6.3VTSVDDR5AD17AC17SERIAL EEPROM 512K/1MCONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.© 2007 Advanced Micro DevicesAdvanced Micro Devices AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
1 Commerce Valley Drive Eastwith AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
Markham, Ontarioother than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
Date:Wednesday, February 24, 2010regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
Sheet2purpose, and disclaims responsibility forany consequences resulting
of12from use of the information included 2280007900G for 1Mbit (PM25LV010A-100SCE)Park-S3Rev1TitleCedar DDR3 MxM3.054321Doc No.105-C077xx-00B
54321U1DMEM I/ODU1EPCIEPCIE_VDDRAB23AC23AD24AE24AE25AE26AF25AG26PCIE_VDDCPCIE_VDDC#1PCIE_VDDC#2PCIE_VDDC#3PCIE_VDDC#4PCIE_VDDC#5PCIE_VDDC#6PCIE_VDDC#7PCIE_VDDC#8PCIE_VDDC#9PCIE_VDDC#10PCIE_VDDC#11PCIE_VDDC#12VDDC#1VDDC#2VDDC#3VDDC#4VDDC#5VDDC#6VDDC#7VDDC#8VDDC#9VDDC#10VDDC#11VDDC#12VDDC#13VDDC#14VDDC#15VDDC#16VDDC#17VDDC#18VDDC#19VDDC#20VDDC#21VDDC#22VDDC#23L23L24L25L26M22N22N23N24R22T22U22V22AA15N15N17R13R16R18Y21T12T15T17T20U13U16U18V21V15V17V20Y13Y16Y18M11M12+MVDD(VDDR1: 1.8A @ 1.5V)C60641uF_6.3VC60651uF_6.3VC60661uF_6.3VC60671uF_6.3VC60681uF_6.3VC60691uF_6.3VC60701uF_6.3VC60711uF_6.3VC607410uF_4VC607510uF_4VC607610uF_4VH13H16H19J10J23J24J9K10K23K24K9L11L12L13L20L21L22(PCIE_VDDR: 400mA @ 1.8V)C59281uF_6.3VC59291uF_6.3VC58001uF_6.3V+1.8V_REGAA27AB24AB32AC24AC26AC27AD25AD32AE27AF32AG27AH32K28K32L27M32N25N27P25P32R27T25T32U25U27V32W25W26W27Y25Y32PCIE_VSS#1PCIE_VSS#2PCIE_VSS#3PCIE_VSS#4PCIE_VSS#5PCIE_VSS#6PCIE_VSS#7PCIE_VSS#8PCIE_VSS#9PCIE_VSS#10PCIE_VSS#11PCIE_VSS#12PCIE_VSS#13PCIE_VSS#14PCIE_VSS#15PCIE_VSS#16PCIE_VSS#17PCIE_VSS#18PCIE_VSS#19PCIE_VSS#20PCIE_VSS#21PCIE_VSS#22PCIE_VSS#23PCIE_VSS#24PCIE_VSS#25PCIE_VSS#26PCIE_VSS#27PCIE_VSS#28PCIE_VSS#29PCIE_VSS#30PCIE_VSS#31GND#1GND#2GND#3GND#4GND#5GND#6GND#7GND#8GND#9GND#10GND#11GND#12GND#13GND#14GND#15GND#16GND#17GND#18GND#19GND#20GND#21GND#22GND#23GND#24GND#25GND#26GND#27GND#28GND#29GND#30GND#31GND#32GND#33GND#34GND#35GND#36GND#37GND#38GND#39GND#40GND#41GND#42GND#43GND#44GND#45GND#46GND#47GND#48GND#49GND#50GND#51GND#52GND#53GND#54GND#55A3A30AA13AA16AB10AB15AB6AC9AD6AD8AE7AG12AH10AH28B10B12B14B16B18B20B22B24B26B6B8C1C32E28F10F12F14F16F18F2F20F22F24F26F6F8G10G27G31G8H14H17H2H20H6J27J31K11K2K22K6DVDDR1#1VDDR1#2VDDR1#3VDDR1#4VDDR1#5VDDR1#6VDDR1#7VDDR1#8VDDR1#9VDDR1#10VDDR1#11VDDR1#12VDDR1#13VDDR1#14VDDR1#15VDDR1#16VDDR1#17PCIE_VDDR#1PCIE_VDDR#2PCIE_VDDR#3PCIE_VDDR#4PCIE_VDDR#5PCIE_VDDR#6PCIE_VDDR#7PCIE_VDDR#8C58024.7uF_6.3V(PCIE_VDDC: 2.0A @ 1.0V)C9831uF_6.3VC9721uF_6.3VC9731uF_6.3VC59301uF_6.3V+1.0V_REGC16684.7uF_6.3V+1.8V_REGB10100BLM15BD121SN1(VDD_CT: 17mA @ 1.8V)C58211uF_6.3V+VDDR3VDD_CTAA20AA21AB20AB21LEVELTRANSLATIONVDD_CT#1VDD_CT#2VDD_CT#3VDD_CT#4I/OAA17AA18AB17AB18VDDR3#1VDDR3#2VDDR3#3VDDR3#4VDDR4#1VDDR4#2VDDR4#3NC#1NC#2NC#3NC#4(VDDC: TBDmA @ TBDV)C2511uF_6.3VC2521uF_6.3VC2531uF_6.3VC2551uF_6.3VC2601uF_6.3VC2611uF_6.3VC2581uF_6.3VC2591uF_6.3V+VDDCCORE(VDDR3: 60mA @ 3.3V)VDDR3C55911uF_6.3V(VDDR4: TBDmA @ 1.8V)CVDDR4V12Y12U12AA11AA12V11U11C1611uF_6.3VC1621uF_6.3VC1631uF_6.3VC1641uF_6.3VC1651uF_6.3VC1661uF_6.3VC1671uF_6.3VC1681uF_6.3VC59321uF_6.3VC19110uF_4VC19210uF_4VC19310uF_4VC19410uF_4VMEM CLKL17L16NC_VDDRHANC_VSSRHAPLL
AM30MPV18L8NC_MPV18PCIE_PVDDB10105BLM15BD121SN1(PCIE_PVDD: 40mA @ 1.8V)C5832C58334.7uF_6.3V1uF_6.3VC5834100nF_6.3VPCIE_PVDDBIF_VDDC#1BIF_VDDC#2R21U21SPV18H7+1.8V_REGB10128BLM15BD121SN1ISOLATEDCORE I/OSPV18(MPV18: 75mA @ 1.8V)SPV10C5950C59514.7uF_6.3V1uF_6.3VC5954100nF_6.3VH8J7SPV10SPVSSVDDCI#1VDDCI#2VDDCI#3VDDCI#4VDDCI#5VDDCI#6VDDCI#7VDDCI#8M13M15M16M17M18M20M21N20(VDDCI : TBDmA @ VDDC)C58361uF_6.3VC58351uF_6.3VC59701uF_6.3VC59711uF_6.3VC597210uF_4V+VDDCM6N11N12N13N16N18N21P6P9R12R15R17R20T13T16T18T21T6U15U17U20U9V13V16V18Y10Y15Y17Y20R11T11GND#56GND#57GND#58GND#59GND#60GND#61GND#62GND#63GND#64GND#65GND#66GND#67GND#68GND#69GND#70GND#71GND#72GND#73GND#74GND#75GND#76GND#77GND#78GND#79GND#80GND#81GND#82GND#83GND#84GND#85GND#86CGNDPOWERVSS_MECH#1VSS_MECH#2VSS_MECH#3A32AM1AM32Park-S3BB10127BLM15BD121SN1(SPV18: 50mA @ 1.8V)C5947C59484.7uF_6.3V1uF_6.3VC5949100nF_6.3VPark-S3B+1.0V_REGB10124BLM15BD121SN1(SPV10: 100mA @ 1.0V)C56141uF_6.3VC5615100nF_6.3V+VDDC+1.8V_REGC11uF_6.3VC21uF_6.3VC31uF_6.3VC41uF_6.3VC51uF_6.3VC61uF_6.3V+VDDR3+MVDDC7C8+PWR_SRC1uF_6.3V1uF_6.3VC91uF_6.3VC101uF_6.3VAACONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.© 2007 Advanced Micro DevicesAdvanced Micro Devices AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
1 Commerce Valley Drive Eastwith AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
Markham, Ontarioother than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
Date:Wednesday, February 24, 2010regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
Sheet3purpose, and disclaims responsibility forany consequences resulting
of12from use of the information included 1Title5432Cedar DDR3 MxM3.01Doc No.105-C077xx-00B
54321DD+5VRUN+1.8V_REG351C27100nF2U27474HCT1G126GW3Q27NDS335N2DPEF_VDD18(2,7)FPVCC1U1GDP E/F POWER+1.8V_REGB10113BLM15AG121SN1DDP A/B POWERDPA_VDD18#1DPA_VDD18#2AE11AF11DPAB_VDD10AG20AG21C(DPEF_VDD18: 400mA @ 1.8V)C5855C58564.7uF_6.3V1uF_6.3VDPEF_VDD18AG15AG16DPEF_VDD10DPE_VDD10#1DPE_VDD10#2DPE_VSSR#1DPE_VSSR#2DPE_VSSR#3DPE_VSSR#4DPE_VSSR#5DPA_VDD10#1DPA_VDD10#2DPA_VSSR#1DPA_VSSR#2DPA_VSSR#3DPA_VSSR#4DPA_VSSR#5AF6AF7DPE_VDD18#1DPE_VDD18#2DPAB_VDD18(DPAB_VDD18: 260mA @ 1.8V)C59571uF_6.3VC59554.7uF_6.3V+1.8V_REGB10130BLM15AG121SN1DC+1.0V_REGB10115120R_450mA(DPEF_VDD10: 240mA @ 1.0V)C5861C58624.7uF_6.3V1uF_6.3VAG14AH14AM14AM16AM18DPEF_VDD18AF16AG17DPEF_VDD10AF22AG22AF23AG23AM20AM22AM24AE1AE3AG1AG6AH5DPAB_VDD18(DPAB_VDD10: 220mA @ 1.0V)C58411uF_6.3V+1.0V_REGB10108120R_450mAC58404.7uF_6.3VDPF_VDD18#1DPF_VDD18#2DPB_VDD18#1DPB_VDD18#2AE13AF13DPAB_VDD10DPF_VDD10#1DPF_VDD10#2DPF_VSSR#1DPF_VSSR#2DPF_VSSR#3DPF_VSSR#4DPF_VSSR#5DPB_VDD10#1DPB_VDD10#2DPB_VSSR#1DPB_VSSR#2DPB_VSSR#3DPB_VSSR#4DPB_VSSR#5AF8AF9AF10AG9AH8AM6AM8R6080150RAF17DPEF_CALRDPEF_CALRDPAB_CALRAE10DPAB_CALRR6079150R(DPEF_PVDD: 40mA @ 1.8V)DPEF_PVDDAG18AF19DPEF_PVDDDPE_PVDDDPE_PVSSDP PLL POWERDPAB_PVDDDPA_PVDDDPA_PVSSAG8AG7DPAB_PVDD(DPAB_PVDD: 40mA @ 1.8V)BAG19AF20DPF_PVDDDPF_PVSSDPB_PVDDDPB_PVSSAG10AG11BPark-S3AACONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.© 2007 Advanced Micro DevicesAdvanced Micro Devices AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
1 Commerce Valley Drive Eastwith AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
Markham, Ontarioother than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
Date:Wednesday, February 24, 2010regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
Sheet4purpose, and disclaims responsibility forany consequences resulting
of12from use of the information included 1Title5432Cedar DDR3 MxM3.01Doc No.105-C077xx-00B
12345678AAU1C(6)M_MDA[63..0]M_MDA0M_MDA1M_MDA2M_MDA3M_MDA4M_MDA5M_MDA6M_MDA7M_MDA8M_MDA9M_MDA10M_MDA11M_MDA12M_MDA13M_MDA14M_MDA15M_MDA16M_MDA17M_MDA18M_MDA19M_MDA20M_MDA21M_MDA22M_MDA23M_MDA24M_MDA25M_MDA26M_MDA27M_MDA28M_MDA29M_MDA30M_MDA31M_MDA32M_MDA33M_MDA34M_MDA35M_MDA36M_MDA37M_MDA38M_MDA39M_MDA40M_MDA41M_MDA42M_MDA43M_MDA44M_MDA45M_MDA46M_MDA47M_MDA48M_MDA49M_MDA50M_MDA51M_MDA52M_MDA53M_MDA54M_MDA55M_MDA56M_MDA57M_MDA58M_MDA59M_MDA60M_MDA61M_MDA62M_MDA63MVREFxA+MVDDR292100RR302R301243R243RMEM_CALRN0MEM_CALRN1J25K25K27J29H30H32G29F28F32F30C30F27A28C28E27G26D26F25A25C25E25D24E23F23D22F21E21D20F19A19D18F17A17C17E17D16F15A15D14F13A13C13E11A11C11F11A9C9F9D8E7A7C7F7A5E5C3E1G7G6G1G3J6J1J3J5K26J26DQA_0DQA_1DQA_2DQA_3DQA_4DQA_5DQA_6DQA_7DQA_8DQA_9DQA_10DQA_11DQA_12DQA_13DQA_14DQA_15DQA_16DQA_17DQA_18DQA_19DQA_20DQA_21DQA_22DQA_23DQA_24DQA_25DQA_26DQA_27DQA_28DQA_29DQA_30DQA_31DQA_32DQA_33DQA_34DQA_35DQA_36DQA_37DQA_38DQA_39DQA_40DQA_41DQA_42DQA_43DQA_44DQA_45DQA_46DQA_47DQA_48DQA_49DQA_50DQA_51DQA_52DQA_53DQA_54DQA_55DQA_56DQA_57DQA_58DQA_59DQA_60DQA_61DQA_62DQA_63MVREFDAMVREFSAMEM_CALRN0MEM_CALRP0MAA_0MAA_1MAA_2MAA_3MAA_4MAA_5MAA_6MAA_7MAA_8MAA_9MAA_10MAA_11MAA_12MAA_13/BA2MAA_14/BA0MAA_15/BA1DQMA_0DQMA_1DQMA_2DQMA_3DQMA_4DQMA_5DQMA_6DQMA_7RDQSA_0RDQSA_1RDQSA_2RDQSA_3RDQSA_4RDQSA_5RDQSA_6RDQSA_7WDQSA_0WDQSA_1WDQSA_2WDQSA_3WDQSA_4WDQSA_5WDQSA_6WDQSA_7ODTA0ODTA1CLKA0CLKA0BCLKA1CLKA1BRASA0BRASA1BCASA0BCASA1BCSA0B_0CSA0B_1CSA1B_0CSA1B_1CKEA0CKEA1WEA0BWEA1BRSVD#2RSVD#3DRAM_RSTCLKTESTACLKTESTBPark-S3M_MAA[14..0](6)K17J20H23G23G24H24J19K19J14K14J11J13H11G11J16L15E32E30A21C21E13D12E3F4H28C27A23E19E15D10D6G5H27A27C23C19C15E9C5H4L18K16H26H25G9H9G22G17G19G16H22J22G13K13K20J17G25H10G14G20M_MAA0M_MAA1M_MAA2M_MAA3M_MAA4M_MAA5M_MAA6M_MAA7M_MAA8M_MAA9M_MAA10M_MAA11M_MAA12BA2BA0BA1M_DQMA#0M_DQMA#1M_DQMA#2M_DQMA#3M_DQMA#4M_DQMA#5M_DQMA#6M_DQMA#7M_QSA0M_QSA1M_QSA2M_QSA3M_QSA4M_QSA5M_QSA6M_QSA7M_QSA#0M_QSA#1M_QSA#2M_QSA#3M_QSA#4M_QSA#5M_QSA#6M_QSA#7ODTA0ODTA1CLKA0CLKA#0CLKA1CLKA#1RASA0#RASA1#CASA0#CASA1#CSA#0_0CSA#1_0CKEA0CKEA1WEA0#WEA1#M_MAA14M_MAA13ODTA0(6)ODTA1(6)CLKA0(6)CLKA#0(6)CLKA1(6)CLKA#1(6)RASA#0(6)RASA#1(6)CASA#0(6)CASA#1(6)CSA#0_0(6)CSA#1_0(6)CKEA0(6)CKEA1(6)WEA#0(6)WEA#1(6)M_MAA[14..0](6)MEMORY
INTERFACEBA2(6)BA0(6)BA1(6)M_DQMA#[7..0](6)M_QSA[7..0](6)BBM_QSA#[7..0](6)+MVDDR29140.2RCCL10K8L7CLKTESTACLKTESTB35mil35milTP7TP8R295R2945.1K10RR296C299120pF_50V51.1RMEM_RST(6)Place close to ASICDDCONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.© 2007 Advanced Micro DevicesAdvanced Micro Devices AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
1 Commerce Valley Drive Eastwith AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
Markham, Ontarioother than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
Date:Wednesday, February 24, 2010regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
Sheet5purpose, and disclaims responsibility forany consequences resulting
of12from use of the information included 1TitleCedar DDR3 MxM3.01234567Doc No.8105-C077xx-00B
54321(5)M_MDA[63..0]M_MDA0M_MDA1M_MDA2M_MDA3M_MDA4M_MDA5M_MDA6M_MDA7M_MDA8M_MDA9M_MDA10M_MDA11M_MDA12M_MDA13M_MDA14M_MDA15M_MDA16M_MDA17M_MDA18M_MDA19M_MDA20M_MDA21M_MDA22M_MDA23M_MDA24M_MDA25M_MDA26M_MDA27M_MDA28M_MDA29M_MDA30M_MDA31M_MDA32M_MDA33M_MDA34M_MDA35M_MDA36M_MDA37M_MDA38M_MDA39M_MDA40M_MDA41M_MDA42M_MDA43M_MDA44M_MDA45M_MDA46M_MDA47M_MDA48M_MDA49M_MDA50M_MDA51M_MDA52M_MDA53M_MDA54M_MDA55M_MDA56M_MDA57M_MDA58M_MDA59M_MDA60M_MDA61M_MDA62M_MDA63(5)M_MAA[14..0]M_MAA0M_MAA1M_MAA2M_MAA3M_MAA4M_MAA5M_MAA6M_MAA7M_MAA8M_MAA9M_MAA10M_MAA11M_MAA12M_MAA13M_MAA14U201VREFC_U201VREFD_U201M_MAA0M_MAA1M_MAA2M_MAA3M_MAA4M_MAA5M_MAA6M_MAA7M_MAA8M_MAA9M_MAA10M_MAA11M_MAA12M_MAA13M_MAA14M8H1N3P7P3N2P8P2R8R2T8R3L7R7N7T3T7M7M2N8M3VREFCAVREFDQA0A1A2A3A4A5A6A7A8A9A10/APA11A12/BCA13A14A15BA0BA1BA2DQL0DQL1DQL2DQL3DQL4DQL5DQL6DQL7DQU0DQU1DQU2DQU3DQU4DQU5DQU6DQU7E3F7F2F8H3H8G2H7D7C3C8C2A7A2B8A3M_MDA10M_MDA12M_MDA11M_MDA13M_MDA8M_MDA15M_MDA9M_MDA14M_MDA4M_MDA0M_MDA7M_MDA1M_MDA6M_MDA2M_MDA5M_MDA3CHANNEL A: 256MB/512MB DDR3U202VREFC_U202VREFD_U202M_MAA0M_MAA1M_MAA2M_MAA3M_MAA4M_MAA5M_MAA6M_MAA7M_MAA8M_MAA9M_MAA10M_MAA11M_MAA12M_MAA13M_MAA14+MVDD(5)BA0(5)BA1(5)BA2BA0BA1BA2VDD#B2VDD#D9VDD#G7VDD#K2VDD#K8VDD#N1VDD#N9VDD#R1VDD#R9VDDQ#A1VDDQ#A8VDDQ#C1VDDQ#C9VDDQ#D2VDDQ#E9VDDQ#F1VDDQ#H2VDDQ#H9VSS#A9VSS#B3VSS#E1VSS#G8VSS#J2VSS#J8VSS#M1VSS#M9VSS#P1VSS#P9VSS#T1VSS#T9VSSQ#B1VSSQ#B9VSSQ#D1VSSQ#D8VSSQ#E2VSSQ#E8VSSQ#F9VSSQ#G1VSSQ#G9B2D9G7K2K8N1N9R1R9A1A8C1C9D2E9F1H2H9A9B3E1G8J2J8M1M9P1P9T1T9B1B9D1D8E2E8F9G1G9(5)BA0(5)BA1(5)BA2M2N8M3BA0BA1BA2VDD#B2VDD#D9VDD#G7VDD#K2VDD#K8VDD#N1VDD#N9VDD#R1VDD#R9VDDQ#A1VDDQ#A8VDDQ#C1VDDQ#C9VDDQ#D2VDDQ#E9VDDQ#F1VDDQ#H2VDDQ#H9VSS#A9VSS#B3VSS#E1VSS#G8VSS#J2VSS#J8VSS#M1VSS#M9VSS#P1VSS#P9VSS#T1VSS#T9VSSQ#B1VSSQ#B9VSSQ#D1VSSQ#D8VSSQ#E2VSSQ#E8VSSQ#F9VSSQ#G1VSSQ#G9B2D9G7K2K8N1N9R1R9A1A8C1C9D2E9F1H2H9A9B3E1G8J2J8M1M9P1P9T1T9B1B9D1D8E2E8F9G1G9M8H1N3P7P3N2P8P2R8R2T8R3L7R7N7T3T7M7VREFCAVREFDQA0A1A2A3A4A5A6A7A8A9A10/APA11A12/BCA13A14A15DQL0DQL1DQL2DQL3DQL4DQL5DQL6DQL7DQU0DQU1DQU2DQU3DQU4DQU5DQU6DQU7E3F7F2F8H3H8G2H7D7C3C8C2A7A2B8A3M_MDA27M_MDA28M_MDA26M_MDA29M_MDA24M_MDA31M_MDA25M_MDA30M_MDA21M_MDA19M_MDA23M_MDA17M_MDA20M_MDA16M_MDA22M_MDA18+MVDD(5)BA0(5)BA1(5)BA2M2N8M3BA0BA1BA2VDD#B2VDD#D9VDD#G7VDD#K2VDD#K8VDD#N1VDD#N9VDD#R1VDD#R9VDDQ#A1VDDQ#A8VDDQ#C1VDDQ#C9VDDQ#D2VDDQ#E9VDDQ#F1VDDQ#H2VDDQ#H9VSS#A9VSS#B3VSS#E1VSS#G8VSS#J2VSS#J8VSS#M1VSS#M9VSS#P1VSS#P9VSS#T1VSS#T9VSSQ#B1VSSQ#B9VSSQ#D1VSSQ#D8VSSQ#E2VSSQ#E8VSSQ#F9VSSQ#G1VSSQ#G9B2D9G7K2K8N1N9R1R9A1A8C1C9D2E9F1H2H9A9B3E1G8J2J8M1M9P1P9T1T9B1B9D1D8E2E8F9G1G9VREFC_U401VREFD_U401M_MAA0M_MAA1M_MAA2M_MAA3M_MAA4M_MAA5M_MAA6M_MAA7M_MAA8M_MAA9M_MAA10M_MAA11M_MAA12M_MAA13M_MAA14M8H1N3P7P3N2P8P2R8R2T8R3L7R7N7T3T7M7U401VREFCAVREFDQA0A1A2A3A4A5A6A7A8A9A10/APA11A12/BCA13A14A15DQL0DQL1DQL2DQL3DQL4DQL5DQL6DQL7DQU0DQU1DQU2DQU3DQU4DQU5DQU6DQU7E3F7F2F8H3H8G2H7D7C3C8C2A7A2B8A3M_MDA35M_MDA39M_MDA34M_MDA38M_MDA32M_MDA37M_MDA33M_MDA36M_MDA45M_MDA43M_MDA46M_MDA41M_MDA44M_MDA42M_MDA47M_MDA40+MVDD(5)BA0(5)BA1(5)BA2M2N8M3BA0BA1BA2VDD#B2VDD#D9VDD#G7VDD#K2VDD#K8VDD#N1VDD#N9VDD#R1VDD#R9VDDQ#A1VDDQ#A8VDDQ#C1VDDQ#C9VDDQ#D2VDDQ#E9VDDQ#F1VDDQ#H2VDDQ#H9VSS#A9VSS#B3VSS#E1VSS#G8VSS#J2VSS#J8VSS#M1VSS#M9VSS#P1VSS#P9VSS#T1VSS#T9VSSQ#B1VSSQ#B9VSSQ#D1VSSQ#D8VSSQ#E2VSSQ#E8VSSQ#F9VSSQ#G1VSSQ#G9B2D9G7K2K8N1N9R1R9A1A8C1C9D2E9F1H2H9A9B3E1G8J2J8M1M9P1P9T1T9B1B9D1D8E2E8F9G1G9VREFC_U402VREFD_U402M_MAA0M_MAA1M_MAA2M_MAA3M_MAA4M_MAA5M_MAA6M_MAA7M_MAA8M_MAA9M_MAA10M_MAA11M_MAA12M_MAA13M_MAA14M8H1N3P7P3N2P8P2R8R2T8R3L7R7N7T3T7M7U402VREFCAVREFDQA0A1A2A3A4A5A6A7A8A9A10/APA11A12/BCA13A14A15DQL0DQL1DQL2DQL3DQL4DQL5DQL6DQL7DQU0DQU1DQU2DQU3DQU4DQU5DQU6DQU7E3F7F2F8H3H8G2H7D7C3C8C2A7A2B8A3M_MDA48M_MDA52M_MDA50M_MDA54M_MDA51M_MDA55M_MDA49M_MDA53M_MDA56M_MDA63M_MDA59M_MDA60M_MDA57M_MDA62M_MDA58M_MDA61+MVDDDD(5)CLKA0(5)CLKA#0(5)CKEA0(5)ODTA0(5)CSA#0_0(5)RASA#0(5)CASA#0(5)WEA#0M_QSA1M_QSA0M_DQMA#1M_DQMA#0M_QSA#1M_QSA#0J7K7K9K1L2J3K3L3F3C7E7D3G3B7CKCKCKEODTCSRASCASWEDQSLDQSUDMLDMUDQSLDQSU(5)CLKA0(5)CLKA#0(5)CKEA0(5)ODTA0(5)CSA#0_0(5)RASA#0(5)CASA#0(5)WEA#0M_QSA3M_QSA2M_DQMA#3M_DQMA#2M_QSA#3M_QSA#2J7K7K9K1L2J3K3L3F3C7E7D3G3B7CKCKCKEODTCSRASCASWEDQSLDQSUDMLDMUDQSLDQSU(5)CLKA1(5)CLKA#1(5)CKEA1(5)ODTA1(5)CSA#1_0(5)RASA#1(5)CASA#1(5)WEA#1M_QSA4M_QSA5M_DQMA#4M_DQMA#5M_QSA#4M_QSA#5J7K7K9K1L2J3K3L3F3C7E7D3G3B7CKCKCKEODTCSRASCASWEDQSLDQSUDMLDMUDQSLDQSU(5)CLKA1(5)CLKA#1(5)CKEA1(5)ODTA1(5)CSA#1_0(5)RASA#1(5)CASA#1(5)WEA#1M_QSA6M_QSA7M_DQMA#6M_DQMA#7M_QSA#6M_QSA#7J7K7K9K1L2J3K3L3F3C7E7D3G3B7CKCKCKEODTCSRASCASWEDQSLDQSUDMLDMUDQSLDQSUCC(5)MEM_RSTT2L8R217243RRESETZQ(5)MEM_RSTT2L8R218243RRESETZQ(5)MEM_RSTT2L8R219243RRESETZQ(5)MEM_RSTT2L8R220243RRESETZQJ1L1J9L9NC#J1NC#L1NC#J9NC#L9J1L1J9L9NC#J1NC#L1NC#J9NC#L9J1L1J9L9NC#J1NC#L1NC#J9NC#L9J1L1J9L9NC#J1NC#L1NC#J9NC#L9100-BALLSDRAM DDR3128Mx16 DDR3+MVDD100-BALLSDRAM DDR3128Mx16 DDR3+MVDD100-BALLSDRAM DDR3128Mx16 DDR3+MVDD100-BALLSDRAM DDR3128Mx16 DDR3+MVDD+MVDDR1RP1ARP1BRP1CRP1DRP3ARP3BRP3CRP3DRP5ARP5BRP5CRP5DRP7ARP7BRP7CRP7DR94587658765120R120R120R120R120R120R120R120R120R120R120R120R120R120R120R120R120R120RM_MAA10BA2M_MAA11M_MAA12BA1M_MAA9M_MAA6M_MAA8M_MAA4M_MAA14M_MAA1BA0M_MAA0M_MAA13M_MAA2M_MAA3M_MAA7M_MAA5R2RP2ARP2BRP2CRP2DRP4ARP4BRP4CRP4DRP6ARP6BRP6CRP6DRP8ARP8BRP8CRP8DR76587658765120R120R120R120R120R120R120R120R120R120R120R120R120R120R120R120R120R120RR2014.99KVREFC_U201R2024.99KC201100nF_6.3VR2034.99KVREFC_U202R2054.99KVREFC_U401R2074.99KVREFC_U402R2084.99KC204100nF_6.3V(5)M_DQMA#[7..0]M_DQMA#0M_DQMA#1M_DQMA#2M_DQMA#3M_DQMA#4M_DQMA#5M_DQMA#6M_DQMA#7(5)M_QSA[7..0]M_QSA0M_QSA1M_QSA2M_QSA3M_QSA4M_QSA5M_QSA6M_QSA7(5)M_QSA#[7..0]M_QSA#0M_QSA#1M_QSA#2M_QSA#3M_QSA#4M_QSA#5M_QSA#6M_QSA#7R2044.99KC202100nF_6.3VR2064.99KC203100nF_6.3VBB+MVDD+MVDD+MVDD+MVDDR2094.99KVREFD_U201R2104.99KC205100nF_6.3VR2114.99KVREFD_U202R2134.99KVREFD_U401R2154.99KVREFD_U402R2164.99KC208100nF_6.3VR2124.99KC206100nF_6.3VR2144.99KC207100nF_6.3V+MVDDC3011uF_6.3VC3021uF_6.3VC3031uF_6.3VC3041uF_6.3VC3051uF_6.3VC351100nF_6.3VC352100nF_6.3VC353100nF_6.3V+MVDD+MVDDC3111uF_6.3VC3121uF_6.3VC3131uF_6.3VC3141uF_6.3VC3151uF_6.3VC356100nF_6.3VC357100nF_6.3VC358100nF_6.3VC3211uF_6.3VC3221uF_6.3VC3231uF_6.3VC3241uF_6.3VC3251uF_6.3VC361100nF_6.3VC362100nF_6.3VC363100nF_6.3V+MVDDC3311uF_6.3VC3321uF_6.3VC3331uF_6.3VC3341uF_6.3VC3351uF_6.3VC366100nF_6.3VC367100nF_6.3VC368100nF_6.3V(5)CLKA0R22156RR22256RAC20910nF+MVDD+MVDDMC381MC382MC383MC384+MVDD+MVDDMC391MC392MC393MC394A(5)CLKA#0C381C382C383C384C391C392C393C394(5)CLKA1R22356RR22456R(5)CLKA#1C21010nFCONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.© 2007 Advanced Micro DevicesAdvanced Micro Devices AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
1 Commerce Valley Drive Eastwith AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
Markham, Ontarioother than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
Date:Wednesday, February 24, 2010regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
Sheet6purpose, and disclaims responsibility forany consequences resulting
of12from use of the information included herein.4.7uF_6.3V4.7uF_6.3V4.7uF_6.3V4.7uF_6.3V4.7uF_6.3V4.7uF_6.3V4.7uF_6.3V4.7uF_6.3V10uF_4VOverlap10uF_4V10uF_4V10uF_4V10uF_4VOverlap10uF_4V10uF_4V10uF_4VRev1Title2Cedar DDR3 MxM3.01Doc No.105-C077xx-00B543
54321PLACE CAPS ON THIS PAGE AS CLOSE TO CONNECTOR AS POSSIBLE+PWR_SRCC5976100nF_50V+VDDR3+5VRUNR6227100KDNI63C59801uF_6.3VC5981100nF_6.3VPEX_STD_SW#Q5536A2142N7002DNI2N7002DNIQ5536B5DVI_HPD(2)DDCDATA_AUX3N(2)DDCCLK_AUX3PR62254.7KSTRAP OPTIONS FROM MOTEHRBOARD+VDDR3PCIE_TXN15PCIE_TXP15PCIE_TXN14PCIE_TXP14PCIE_TXN13PCIE_TXP13PCIE_TXN12PCIE_TXP12PCIE_TXN11PCIE_TXP11PCIE_TXN10PCIE_TXP10PCIE_TXN9PCIE_TXP9PCIE_TXN8PCIE_TXP8PCIE_TXN7PCIE_TXP7CJ1AE1E3C59791nF729343454749563656769783858789975975379759222923392449255926692779281PWR_SRC_E1GND_E3Part 1 of 2+VDDR3PWR_SRC_E2GND_E4PRSNT_R#_2WAKE#_4PWR_GOOD_6PWR_EN_8RSVD_10RSVD_12RSVD_14RSVD_16PWR_LEVEL_18TH_OVERT#_20TH_ALERT#_22TH_PWM_24GPIO0_26GPIO1_28GPIO2_30SMB_DAT_32SMB_CLK_34GND_36OEM_38OEM_40OEM_42OEM_44GND_46PEX_TX15#_48PEX_TX15_50GND_52PEX_TX14#_54PEX_TX14_56GND_58PEX_TX13#_60PEX_TX13_62GND_64PEX_TX12#_66PEX_TX12_68GND_70PEX_TX11#_72PEX_TX11_74GND_76PEX_TX10#_78PEX_TX10_80GND_82PEX_TX9#_84PEX_TX9_86GND_88PEX_TX8#_90PEX_TX8_92GND_94PEX_TX7#_96PEX_TX7_98GND_100PEX_TX6#_102PEX_TX6_104GND_106PEX_TX5#_108PEX_TX5_110GND_112PEX_TX4#_114PEX_TX4_116GND_118PEX_TX3#_120PEX_TX3_122GND_124GND_134PEX_TX2#_136PEX_TX2_138GND_140PEX_TX1#_142PEX_TX1_144GND_146PEX_TX0#_148PEX_TX0_150GND_152CLK_REQ#_154PEX_RST#_156VGA_DDC_DAT_158VGA_DDC_CLK_160VGA_VSYC_162VGA_HSYC_164GND_166VGA_RED_168VGA_GREEN_170VGA_BLUE_172GND_174LVDS_LCLK#_176LVDS_LCLK_178GND_180LVDS_LTX3#_182LVDS_LTX3_184GND_186LVDS_LTX2#_188LVDS_LTX2_190GND_192LVDS_LTX1#_194LVDS_LTX1_196GND_198LVDS_LTX0#_200LVDS_LTX0_202GND_204DP_D_L0#_206DP_D_L0_208GND_210DP_D_L1#_212DP_D_L1_214GND_216DP_D_L2#_218DP_D_L2_220GND_222DP_D_L3#_224DP_D_L3_226GND_228DP_D_AUX#_230DP_D_AUX_232DP_C_HPD_234DP_D_HPD_236RSVD_238RSVD_240RSVD_242GND_244DP_B_L0#_246DP_B_L0_248GND_250DP_B_L1#_252DP_B_L1_254GND_256DP_B_L2#_258DP_B_L2_260GND_262DP_B_L3#_264DP_B_L3_266GND_268DP_B_AUX#_270DP_B_AUX_272DP_B_HPD_274DP_A_HPD_2763V3_2783V3_280E2E424684464852646668728486889888238248258268278280R6095100KPWRGOOD(8)RUNPWROK(8,9,10)+VDDR3100KR1130+VDDR3100KR6125GPIO5_AC_BATT(2)CTFb(2)GPIO17_THERMAL_INT(2)MB_GPIO0MB_GPIO1MB_GPIO2SMB_DATSMB_CLKMB_GPIO0(2)MB_GPIO1(2)MB_GPIO2(2)D(2,8)GPIO0(2,8)GPIO1(2,4)FPVCCDPNL_PWR_ENPNL_BL_ENPNL_BL_PWMR62264.7KPCIE_TXN6PCIE_TXP6(1)PCIE_REFCLKP(1)PCIE_REFCLKN(1)PCIE_RXP[15..0](1)PCIE_RXN[15..0](1)PCIE_TXP[15..0](1)PCIE_TXN[15..0]PCIE_REFCLKPPCIE_REFCLKNPCIE_RXP[15..0]PCIE_RXN[15..0]PCIE_TXP[15..0]PCIE_TXN[15..0]PCIE_TXN2PCIE_TXP2PCIE_TXN1PCIE_TXP1PCIE_TXN0PCIE_TXP0(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)(2)TXOUT_L0-TXOUT_L0+TXOUT_L1-TXOUT_L1+TXOUT_L2-TXOUT_L2+TXOUT_L3-TXOUT_L3+TXCLK_L-TXCLK_L+TXOUT_U0-TXOUT_U0+TXOUT_U1-TXOUT_U1+TXOUT_U2-TXOUT_U2+TXOUT_U3-TXOUT_U3+TXCLK_U-TXCLK_U+TXOUT_L0-TXOUT_L0+TXOUT_L1-TXOUT_L1+TXOUT_L2-TXOUT_L2+TXOUT_L3-TXOUT_L3+TXCLK_L-TXCLK_L+TXOUT_U0-TXOUT_U0+TXOUT_U1-TXOUT_U1+TXOUT_U2-TXOUT_U2+TXOUT_U3-TXOUT_U3+TXCLK_U-TXCLK_U+PCIE_REFCLKNPCIE_REFCLKPPCIE_TXN5PCIE_TXP5PCIE_TXN4PCIE_TXP4PCIE_TXN3PCIE_TXP35V_15V_35V_55V_75V_9GND_11GND_13GND_15GND_17PEX_STD_SW#_19VGA_DISABLE#_21PNL_PWR_EN_23PNL_BL_EN_25PNL_PWM_27HDMI_CEC_29DVI_HPD_31LVDS_DDC_DAT_33LVDS_DDC_CLK_35GND_37OEM_39OEM_41OEM_43OEM_45GND_47PEX_RX15#_49PEX_RX15_51GND_53PEX_RX14#_55PEX_RX14_57GND_59PEX_RX13#_61PEX_RX13_63GND_65PEX_RX12#_67PEX_RX12_69GND_71PEX_RX11#_73PEX_RX11_75GND_77PEX_RX10#_79PEX_RX10_81GND_83PEX_RX9#_85PEX_RX9_87GND_89PEX_RX8#_91PEX_RX8_93GND_95PEX_RX7#_97PEX_RX7_99GND_101PEX_RX6#_103PEX_RX6_105GND_107PEX_RX5#_109PEX_RX5_111GND_113PEX_RX4#_115PEX_RX4_117GND_119PEX_RX3#_121PEX_RX3_123GND_125GND_133PEX_RX2#_135PEX_RX2_137GND_139PEX_RX1#_141PEX_RX1_143GND_145PEX_RX0#_147PEX_RX0_149GND_151PEX_REFCLK#_153PEX_REFCLK_155GND_157RSVD_159RSVD_161RSVD_163RSVD_165RSVD_167LVDS_UCLK#_169LVDS_UCLK_171GND_173LVDS_UTX3#_175LVDS_UTX3_177GND_179LVDS_UTX2#_181LVDS_UTX2_183GND_185LVDS_UTX1#_187LVDS_UTX1_189GND_191LVDS_UTX0#_193LVDS_UTX0_195GND_197DP_C_L0#_199DP_C_L0_201GND_203DP_C_L1#_205DP_C_L1_207GND_209DP_C_L2#_211DP_C_L2_213GND_215DP_C_L3#_217DP_C_L3_219GND_221DP_C_AUX#_223DP_C_AUX_225RSVD_227RSVD_229RSVD_231RSVD_233RSVD_235RSVD_237RSVD_239RSVD_241RSVD_243RSVD_245RSVD_247RSVD_249GND_251DP_A_L0#_253DP_A_L0_255GND_257DP_A_L1#_259DP_A_L1_261GND_263DP_A_L2#_265DP_A_L2_267GND_269DP_A_L3#_271DP_A_L3_273GND_275DP_A_AUX#_277DP_A_AUX_279PRSNT_L#_281MXM 3 EDGECONNPCIE_RXN15PCIE_RXP15PCIE_RXN14PCIE_RXP14PCIE_RXN13PCIE_RXP13PCIE_RXN12PCIE_RXP12PCIE_RXN11PCIE_RXP11PCIE_RXN10PCIE_RXP10PCIE_RXN9PCIE_RXP9PCIE_RXN8PCIE_RXP8PCIE_RXN7PCIE_RXP7PCIE_RXN6PCIE_RXP6PCIE_RXN5PCIE_RXP5PCIE_RXN4PCIE_RXP4PCIE_RXN3PCIE_RXP3CPNL_BL_PWMPNL_BL_ENR6103MR6104R61040R0RDNI0RBLON_PWM(2)GPIO7_BLON(2)Mechanical KeyPCIE_RXN2PCIE_RXP2PCIE_RXN1PCIE_RXP1PCIE_RXN0PCIE_RXP0CLK_REQ#PCIE_RST#(1)DDC5DATA(2)DDC5CLK(2)VSYNC_DAC1(2,8)HSYNC_DAC1(2,8)VGA_REDVGA_GRNVGA_BLUTXCLK_L-TXCLK_L+TXOUT_L3-TXOUT_L3+TXOUT_L2-TXOUT_L2+TXOUT_L1-TXOUT_L1++VDDR3TXOUT_L0-TXOUT_L0+R526100KSMB_CLK+VDDR3R527100KSMB_DATDP_C_HPDR71230RDNIGPIO3_SMBDATA(2)R71220RDNIGPIO4_SMBCLK(2)VGA_RED(2)VGA_GRN(2)VGA_BLU(2)R61214.7KR61224.7KTXCLK_U-TXCLK_U+TXOUT_U3-TXOUT_U3+TXOUT_U2-TXOUT_U2+TXOUT_U1-TXOUT_U1+TXOUT_U0-TXOUT_U0+(2)TX5M_DPB0N(2)TX5P_DPB0P(2)TX4M_DPB1N(2)TX4P_DPB1P(2)TX3M_DPB2N(2)TX3P_DPB2P(2)TXCBM_DPB3N(2)TXCBP_DPB3P(2)DDCDATA_AUX2N(2)DDCCLK_AUX2P+VDDR3BB(2)HPD1R6124100KDP_A_HPD(2)GPIO14_HPD2R6116100KDP_C_HPDA(2)TX2M_DPA0N(2)TX2P_DPA0P(2)TX1M_DPA1N(2)TX1P_DPA1PA(2)GPIO18_HPD3R6102100KDVI_HPD(2)TX0M_DPA2N(2)TX0P_DPA2P(2)TXCAM_DPA3N(2)TXCAP_DPA3P(2)DDCDATA_AUX1N(2)DDCCLK_AUX1PJ1BMTG1MTG2MTG3MTG4MTG5MTG6Part 2 of 2DP_A_HPD+3VRUNC6016C601710uF_X6S1uF_6.3VMTG1MTG2MTG3MTG4MTG5MTG6MXM 3 EDGECONNCONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.© 2007 Advanced Micro DevicesAdvanced Micro Devices AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
1 Commerce Valley Drive Eastwith AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
Markham, Ontarioother than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
Date:Wednesday, February 24, 2010regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
Sheet7purpose, and disclaims responsibility forany consequences resulting
of12from use of the information included 1Title5432Cedar DDR3 MxM3.01Doc No.105-C077xx-00B
54321Voltage Settings and Power Play+3VRUND+3VRUNDR124010K(2,9)GPIO20_PCNTL1(2,9)GPIO15_PCNTL0R124110KDNI(10)VID1_MVDD(10)VID0_MVDDR124210KDNIR124310KDNILDO1Vin = +1.5V +/-2%Vout = +1.0V +/- 2%Iout = 1.5A RMS MAX (TBV)PCB: 50 to 70mm sq. copper area for coolingMR1240MR124110K10KDNIMR1242MR124310K10KU851PWRGOODLDO1_EN+MVDD+5VRUN1234POKGND#8ENFBVINVOUTCNTLREFINGND#9uP7706U8+5VRUN+1.0V_REG+MVDDR85310KMU851C87659LDO1_FB+1.0V_REGMR851+1.0V_REGB8510RDNI220R_2ADNI+VDDC Overlap
R187659LDO1_FBR8552.67K(7)PWRGOODLDO1_EN1234POKGND#8ENFBVINVOUTCNTLREFINGND#9UP7706ADC8C85533pF_50VC85110uF_X6SC854100nF_6.3VOverlapPIN STRAPS+VDDR3(2,7)GPIO0(2,7)GPIO1GPIO0GPIO1GPIO2GPIO9GPIO11GPIO12GPIO13GPIO22V1SYNCH1SYNCV2SYNCH2SYNCR6134R6135R6136R6138R6139R6140R6141R6147R6142R6143R6145R614610K10K10K10K10K10K10K10KBIF_GEN2_EN_A(2,7)VSYNC_DAC1(2,7)HSYNC_DAC110K10KBIF_VGA DIS10K10KDNIROMIDCFG[2:0]GPIO[13:11]GPIO9VGA Control0: VGA controller capacity enabled1: VGA controller capacity disabled
(for multi-GPU)CR20603/0802Overlap
footprintsC8581uF_6.3VMC856C85610uF_6.3V10uF_X6SR85410.2KCONFIGURATION STRAPSALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESETDNIDNIDNITX_DEEMPH_ENGPIO1STRAPSTX_PWRS_ENBPINGPIO0DESCRIPTION OF DEFAULT SETTINGSTransmitter Power Savings EnableGPIO0 and GPIO1 pull
ups need to be stuffedwith Q5536 if systemPCIE Transmitter De-emphasis Enableboard is controlling the0: Tx de-emphasis disabledPCIE swing.0: 50% Tx output swing1: Full Tx output swing1: Tx de-emphasis enabledVout = Vref x (1 + R1/R2)Vref = 0.8V(2)GPIO2(2)GPIO9(2)GPIO11(2)GPIO12(2)GPIO13(2)GPIO22DefaultSetting11GPIO2PCIE Gen2 Enable0: Advertises the PCIE device as 2.5GT/s capable at power-on1: Advertises the PCIE device as 5.0GT/s capable at power-on1LDO2Vin = +3.3V +/-6%Vout = +1.8V +/- 2%Iout = 0.8A RMS MAX (TBV)(2)VSYNC_DAC2(2)HSYNC_DAC2PCB: 50 to 70mm sq. copper area for coolingBGPIO9 pull up needsto be stuffed withQ5537 if systemboard is controllingthe VGA capacity0Serial ROM type or Memory Aperture Size SelectIf GPIO22 = 0, defines memory aperture sizeIf GPIO22 = 1, defines ROM type100 - 512Kbit M25P05A (ST)101 - 1Mbit M25P10A (ST)101 - 2Mbit M25P20 (ST)101 - 4Mbit M25P40 (ST)101 - 8Mbit M25P80 (ST)100 - 512Kbit Pm25LV512 (Chingis)101 - 1Mbit Pm25LV010 (Chingis)XXXBMU861+3VRUNPWRGOODVDDC_POKLDO2_VIN+5VRUNMR868R8682.4R_1210_0.5W1R+5VRUN1234POKGND#8ENFBVINVOUTCNTLREFINGND#987659LDO2_FB+1.8V_REGBIOS_ROM_ENGPIO22Enable external BIOS ROM device0: Disabled1: Enabled1+3VRUNUP7706ADC8+1.8V_REG+1.8V_REGAUD[1]AUD[0]HSYNCVSYNCOverlap
footprintsUse two 2.4R 1/2W <=5%MR869R8692.4R_1210_0.5W1RR86110K Overlap
U861R587659LDO2_FBR86513.0K(7)PWRGOOD(9)VDDC_POKLDO2_VIN1234POKGND#8ENFBVINVOUTCNTLREFINGND#9uP7706U8C86533pF_50VC86110uF_X6SC864100nF_6.3VVDDR3 GATINGVIP_DEVICE_STRAP_DISV2SYNC00 - No audio function01 - Audio for DP only10 - Audio for DP and HDMI if dongle is detected11 - Audio for both DP and HDMIHDMI must only be enabled on systems that are legally entitled. It is the
responsibility of the system designer to ensure that the system is entitled to
support this Device Strap Disable0: Slave VIP host port devices present1: No slave VIP host port devices reporting presence1R4R6194R86410.2K+3VRUN20RDNISMS_EN_HARD+VDDR3Q55313Si2301BDSH2SYNCReserved00603/0802Overlap
footprintsMC866C86610uF_6.3V10uF_X6SC8681uF_6.3VVout = Vref x (1 + R5/R4)Vref = 0.8VR6196100K3A1Q5534MMBT3904A(7,9,10)RUNPWROKR61995.1K1C60531uF_6.3V2CONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.© 2007 Advanced Micro DevicesAdvanced Micro Devices AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
1 Commerce Valley Drive Eastwith AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
Markham, Ontarioother than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
Date:Wednesday, February 24, 2010regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
Sheet8purpose, and disclaims responsibility forany consequences resulting
of12from use of the information included 1Title5432Cedar DDR3 MxM3.01Doc No.105-C077xx-00B
87654321DINPUT CAP+PWR_SRC+PWR_SRC+PWR_SRC+PWR_SRC+PWR_SRC+PWR_SRCMR607C6642.2uF_16VX7R, 12061.3mm HiC6842.2uF_16VX7R, 12061.3mm HiC6832.2uF_16VX7R, 12061.3mm HiC6422.2uF_16VX7R, 12061.3mm HiC6822.2uF_16VX7R, 12061.3mm Hi+5VRUNR6072R2OR6000R2R2Dshare pad+VCCTop Side Hmax=1.5mmTop Side Hmax=1.5mm+PW_VDDC_LGDR6158.06K+PW_VDDC_MC607100nF603C605100nF0603+PWR_SRC+5VRUN2D601R6180R1BAT54KFILMBOOT11917U6012018OC602100nF603CSPR6041KCurrent SensingC604100nF_6.3VC606100nF_6.3VCSN15CSNR605221RR62010KEN/PSMC60915nFR62110KRUNPWROK(7,8,10)Cshare pad+VDDAVDDC_CCSPVDDC_CCSN Differential trace from InductorLGDROOPPHASEBOOTCQ601BSC120N03LSG95678+PW_VDDC_HGD2VCCCSP16UGEN/PSM144321+VDDCL6010.56UHSunken Inductor10x10mmR603(8)VDDC_POK3POKVID113GPIO20_PCNTL1(2,8)GPIO15_PCNTL0(2,8)+PWR_SRCOC6006.8nF_25VOR601VDDC_COMPC6116.8nF_25V8.06KVDDC_VIN21NS605NS_VIASense Point+PW_VDDC_HGD8.06KVDDC_RSET3UR6020RVDDC_RSET24+PW_VDDC_MRSET3VID012C60315nF22R602NS603NS_VIA11Sense Point8.06K5MODE/RSET2REFIN/RSET1COMP11RTVDDC_RSET16VDDC_RSET078VDDC_FBRTN9Route like
differential pairPlace across
Q613, Q614VDDC_RTQ602BSC030N03LS G603PISCES_MR_DR10C6081UF_16V95678FBGND2GND1FBRTNRSET0R619300R805NS604NS_VIAC60215nF2221Type IIICompensationR6128.06KR6140RR6133.65KVDDC_FBUR6050RR611RFB1C612150PFR6090RReserve for
Loop TestVDDC_CCSNVDDC_CCSP+PW_VDDC_LGDRC snubber values shownare for reference only,tuning is requiredC6136.8nF_25V10K4321+VDDC12R6018.06KR600R616UR600OC601VDDC_SVC60115nFC60015nFC61615nFR6060R603VDDC_FB_TRACENS_VIANS601Sense PointB0R8.06K8.06K15nFB+PW_VDDC_MOUTPUT CAP+VDDCC639330uFSP/POSCAP,
SMT 7343Max 1.5mm_HC640330uFSP/POSCAP,
SMT 7343Max 1.5mm_HC641220UF_2VSP/POSCAP,
SMT 7343Max 1.2mm_HTop Side Hmax=1.5mmLOW PROFILE POSCAP+VDDCBottom Side Hmax=1.2mmAC64415nF402C64315nF402AMLCCCONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.© 2007 Advanced Micro DevicesAdvanced Micro Devices AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
1 Commerce Valley Drive Eastwith AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
Markham, Ontarioother than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
Date:Wednesday, February 24, 2010regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
Sheet9purpose, and disclaims responsibility forany consequences resulting
of12from use of the information included 1Title876543Cedar DDR3 MxM3.02Doc No.1105-C077xx-00B
87654321DINPUT CAP+PWR_SRC+PWR_SRC+PWR_SRC+PWR_SRC+PWR_SRCDMR707+5VRUNR707C7212.2uF_16VX7R, 12061.3mm HiC7232.2uF_16VX7R, 12061.3mm HiC7322.2uF_16VX7R, 12061.3mm HiC7251uF_16VX7R, 12060.95mm Hi+PW_MVDDC_LGDTop Side Hmax=1.5mmBottom Side Hmax=1.2mm+PW_MVDDC_MC707100nF603C705100nF0603R7180R2D7011BAT54KFILMBOOT120192R22R2OR7000Rshare padR7158.06K402share padOC702100nF603CSPR7041KCurrent SensingMVDDC_CCSPMVDDC_CCSN Differential trace from InductorC706100nF_6.3VCSN15CSNR705221RR72010KEN/PSMC70915nFR72110KC17U7011816+VDDA+VCCLGDROOPPHASE+5VRUNVCCCSPC704100nF_6.3VBOOTRUNPWROK(7,8,9)+PWR_SRC+PW_MVDDC_HGD2UGEN/PSM14C395678Q701BSC120N03LSGPOKVID113VID1_MVDD(8)VID0_MVDD(8)+PWR_SRCOC7006.8nF_25VOR701MVDDC_COMPC7116.8nF_25V8.06KMVDDC_VIN21NS705NS_VIASense PointR7038.06KMVDD_RSET3UR7020RMVDD_RSET24RSET3VID012C70315nFSMML701L7011.5uH_11A+MVDD+PW_MVDDC_M2.2uH_8AOverlapR7028.06K5MODE/RSET2REFIN/RSET1COMP114321C70215nF2221GND2GND1+PW_MVDDC_HGDFBRTNRSET0Type IIICompensationRTFBMVDD_RSET16MVDD_RSET07MVDD_FBRTN9PISCES_MR_DRR719300R805C7081UF_16V603R7128.06KR7140RR7133.65KMVDDC_FBUR7050RR711RFB1C712150PFR7090RReserve for
Loop Test8NS704NS_VIA11NS703NS_VIASense PointMVDD_RT221095678C7136.8nF_25V10K+MVDD12R701R700R716UR700OC701MVDDC_SVC70115nFC70015nFC71615nFQ702BSC030N03LS GR7060R603MVDDC_FB_TRACENS_VIANS701Sense Point0R8.06K8.06K8.06K15nFPlace across
Q613, Q614Route like
differential pair4321+PW_MVDDC_MBMVDDC_CCSNMVDDC_CCSP+PW_MVDDC_LGDRC snubber values shownare for reference only,tuning is requiredBOUTPUT CAP+MVDD+MVDDC737330uFSP/POSCAP,
SMT 7343Max 1.5mm_HC74115nF402Top Side Hmax=1.5mmMLCCLOW PROFILE POSCAPAACONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.© 2007 Advanced Micro DevicesAdvanced Micro Devices AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
1 Commerce Valley Drive Eastwith AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
Markham, Ontarioother than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
Date:Wednesday, February 24, 2010regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
Sheet10purpose, and disclaims responsibility forany consequences resulting
of12from use of the information included 1Title876543Cedar DDR3 MxM3.02Doc No.1105-C077xx-00B
54321MEMORY CHANNEL ADDR3 4pcs 64Mx16DDCH ALVTMDPDL LVDSDPE/FDDCAUX3LVDSLVDS_LTXx/LTXx#LVDS_UTXx/UTXx#LVDS_DDC_CLK/DATDVI_HPDPOWER REGULATORSFrom +PWR_SRC+VDDC, +MVDDHPD3TMDPABDP_ADPADP_A_Lx/Lx#DP_A_AUX/AUX#DP_A_HPDCFrom +3VRUN+1.8V_REG, VDDR3CDDCAUX1From +VDDCVDDC, VDDCIFrom +MVDD+1.0V_REG, VDDR1, MVDDQ/CFrom +1.8V_REG
VDDR4, VDD_CT, TSVDD,
PCIE_VDDR, PCIE_PVDD,
DPLL_PVDD, DPx_PVDD,
DPx_VDD18, MPV18, SPV18,
AVDD, VDD1DIStrapsGPIOHPD1DP_CBIOSROMDPBDDCAUX2HPD2DP_C_Lx/Lx#DP_C_AUX/AUX#DP_C_HPDXTALXTALIN/OUTDAC2CRT DAC1VGAVGA_RED/GREEN/BLUEVGA_DDC_CLK/DATFrom +1.0V_REGPCIE_VDDC, DPLL_VDDC,DPx_VDD10, SPV10Dynamic VDDCGPIO20/15DDC5V/HSyncVGA_VSYNC/HSYNCPOWER DELIVERYMxM3.0 Source+3VRUNBThermalGPIO3, GPIO4SMB_CLK/DATB+5VRUN+PWR_SRCCedar3V3 delayed circuitGPIO17TH_ALERT#GPIO19_CTFTH_OVERT#PCIESMPS EnableCircuit3VRUN5VRUNPWR_SRCMxM3.0 ConnectorMxM3.0 Cedar DDR3 512MBDP DP DL-LVDS VGAAACONFIDENTIAL & PROPRIETARY TO ADVANCED MICRO DEVICES INC.© 2007 Advanced Micro DevicesAdvanced Micro Devices AMD Board schematic and design is the exclusive property of AMD,
and is provided only to entities under a non-disclosure agreement
1 Commerce Valley Drive Eastwith AMD for evaluation purposes. Further distribution or disclosure
is strictly prohibited. Use of this schematic and design for any purpose
Markham, Ontarioother than evaluation requires a Board Technology License Agreement
with AMD. AMD makes no representations or warranties of any kind
Date:Wednesday, February 24, 2010regarding this schematic and design, including, not limited to,
any implied warranty of merchantibility or fitness for a particular
Sheet11purpose, and disclaims responsibility forany consequences resulting
of12from use of the information included 1Title5432Cedar DDR3 MxM3.01Doc No.105-C077xx-00B
54321TitleSchematic :Wednesday, February 24, 2010RevCedar DDR3 MxM3.0REVISION HISTORYD105-C077xx-00BNOTE:This schematic represents the PCB, it does not represent any specific Stuffing options (component values, DNI’s, …) please consult the product specific contact AMD representative to obtain latest BOM closest to the application desired.1SchRev01PCBRev00A00BDDate09/10/0610/02/24Initial design for Cedar DDR3 MxM3.0 Type A-4LREVISION DESCRIPTIONLayout change only (Move GPIO4_SMBCLK to the bottom layer)CCBBAA54321