最新消息: USBMI致力于为网友们分享Windows、安卓、IOS等主流手机系统相关的资讯以及评测、同时提供相关教程、应用、软件下载等服务。

FPGA可编程逻辑器件芯片XC6SLX45T-2FGG484C中文规格书

IT圈 admin 38浏览 0评论

2024年2月24日发(作者:局振宇)

Date10/07/0911/09/09Version1.01.1Initial Xilinx on•Updated Figure1-17 and Figure1-23.•Changed speed grade from -2 to -3.•Miscellaneous typographical typographical edits to Table1-24 and d Figure1-2. Added Note 6 to Table1-11. Updated board connections for

SFP_TX_DISABLE in Table1-12. Added note about FMC LPC J63 connector in 18. VITA

57.1 FMC LPC Connector. Updated U1 FPGA Pin column for FMC_LA00_CC_P/N in

Table1-28. Updated description of PMBus Pod and TI Fusion Digital Power Software

GUI in Onboard Power Regulation. Updated AppendixB, VITA 57.1 FMC LPC

Connector Pinout, and AppendixC, Xilinx Design d 2. 128 MB DDR3 Component Memory. Added note 1 to d description of Fusion Digital Power Software in Onboard Power d oscillator manufacturer information from Epson to SiTime in Table1-1. Revised

oscillator manufacturer information from Epson to SiTime on page page26. Deleted note

on page 44 referring to J55: “Note: This header is not installed on the SP605 as built.”

Revised values for R50 and R216 in Figure1-12. Revised oscillator manufacturer

information from Epson to SiTime on page page69.02/01/1005/18/101.1.11.206/16/1009/24/1002/16/111.31.41.5SP605 Hardware User Guide

Detailed DescriptionTable 1-3:Termination Resistor Requirements (Cont’d)Signal NameMEM1_ODTMEM1_DQ[15:0]MEM1_UDQS[P,N], MEM1_LDQS[P,N]MEM1_UDM, MEM1_LDMMEM1_CK[P,N]Board Termination4.7KΩ to GND – – –100Ω differential at memory

componentOn-Die Termination –ODTODTODT –Notes:

l value of VTT for DDR3 interface is 1-4:FPGA On-Chip (OCT) Termination External Resistor RequirementsU1 FPGA PinZIORZQFPGA Pin NumberM7K7Board Connection for OCTNo Connect100Ω to GROUNDTable1-5 shows the connections and pin numbers for the DDR3 Component 1-5:DDR3 Component Memory ConnectionsU1 FPGA

PinK2K1K5M6H3M3L4K6G3G1J4E1F1J6H5J3J1H1Schematic Net NameMEM1_A0MEM1_A1MEM1_A2MEM1_A3MEM1_A4MEM1_A5MEM1_A6MEM1_A7MEM1_A8MEM1_A9MEM1_A10MEM1_A11MEM1_A12MEM1_A13MEM1_A14MEM1_BA0MEM1_BA1MEM1_BA2Memory U42Pin NumberN3P7P3N2P8P2R8R2T8R3L7R7N7T3T7M2N8M3Pin NameA0A1A2A3A4A5A6A7A8A9A10/APA11A12/BCNNC/A13NC/A14BA0BA1BA2SP605 Hardware User GuideUG526 (v1.9) February 14, 2019

Chapter 1:SP605 Evaluation BoardU1FPGA SPI InterfaceU32DIN, DOUT, CCLKJ17SPI x4FlashMemorySPIX4_CS_BWinbondW25Q64FVSFIG2ON = SPI X4 U32OFF = SPI EXT. J17SPI SelectJumperSPI_CS_B1J46SPI ProgramHeaderUG526_04_020819Figure 1-4:SPI Flash Interface TopologyTable 1-6:SPI x4 Memory ConnectionsU1 FPGA

PinAB2T14R13AA3AB20AA20Y20Schematic Net NameFPGA_PROG_BFPGA_D2_MISO3FPGA_D1_MISO2_RSPI_CS_BFPGA_MOSI_CSI_B_MISO0FPGA_D0_DIN_MISO_MISO1FPGA_CCLKSPI MEM U32Pin #Pin NameSPI HDR J17Pin #123456789 –Pin Name– – –

TMSTDITDOTCK– –19 –

15816IO3_HOLD_BIO2_WP_B –DINIO1_DOUTCLK – – –– –J46.2(1)Notes:

a U1 FPGA pinGNDVCC3V3–

–SPIX4_CS_B –7 –CS_BSee the Winbond Serial Flash Memory Data Sheet for more information. [Ref16]

See the XPS Serial Peripheral Interface Data Sheet (DS570) for more information. [Ref4]SP605 Hardware User GuideUG526 (v1.9) February 14, 2019

Detailed DescriptionU1 FPGA PinN22N20M22M21L19K20H22H21L17K17G22G20K18K19H20J19E22Schematic Net NameFLASH_A0FLASH_A1FLASH_A2FLASH_A3FLASH_A4FLASH_A5FLASH_A6FLASH_A7FLASH_A8FLASH_A9FLASH_A10FLASH_A11FLASH_A12FLASH_A13FLASH_A14FLASH_A15FLASH_A16U25 BPI FLASHPin Number29252423222125Pin NameA1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17SP605 Hardware User GuideUG526 (v1.9) February 14, 2019

Detailed DescriptionSP605 Hardware User GuideUG526 (v1.9) February 14, 2019

2024年2月24日发(作者:局振宇)

Date10/07/0911/09/09Version1.01.1Initial Xilinx on•Updated Figure1-17 and Figure1-23.•Changed speed grade from -2 to -3.•Miscellaneous typographical typographical edits to Table1-24 and d Figure1-2. Added Note 6 to Table1-11. Updated board connections for

SFP_TX_DISABLE in Table1-12. Added note about FMC LPC J63 connector in 18. VITA

57.1 FMC LPC Connector. Updated U1 FPGA Pin column for FMC_LA00_CC_P/N in

Table1-28. Updated description of PMBus Pod and TI Fusion Digital Power Software

GUI in Onboard Power Regulation. Updated AppendixB, VITA 57.1 FMC LPC

Connector Pinout, and AppendixC, Xilinx Design d 2. 128 MB DDR3 Component Memory. Added note 1 to d description of Fusion Digital Power Software in Onboard Power d oscillator manufacturer information from Epson to SiTime in Table1-1. Revised

oscillator manufacturer information from Epson to SiTime on page page26. Deleted note

on page 44 referring to J55: “Note: This header is not installed on the SP605 as built.”

Revised values for R50 and R216 in Figure1-12. Revised oscillator manufacturer

information from Epson to SiTime on page page69.02/01/1005/18/101.1.11.206/16/1009/24/1002/16/111.31.41.5SP605 Hardware User Guide

Detailed DescriptionTable 1-3:Termination Resistor Requirements (Cont’d)Signal NameMEM1_ODTMEM1_DQ[15:0]MEM1_UDQS[P,N], MEM1_LDQS[P,N]MEM1_UDM, MEM1_LDMMEM1_CK[P,N]Board Termination4.7KΩ to GND – – –100Ω differential at memory

componentOn-Die Termination –ODTODTODT –Notes:

l value of VTT for DDR3 interface is 1-4:FPGA On-Chip (OCT) Termination External Resistor RequirementsU1 FPGA PinZIORZQFPGA Pin NumberM7K7Board Connection for OCTNo Connect100Ω to GROUNDTable1-5 shows the connections and pin numbers for the DDR3 Component 1-5:DDR3 Component Memory ConnectionsU1 FPGA

PinK2K1K5M6H3M3L4K6G3G1J4E1F1J6H5J3J1H1Schematic Net NameMEM1_A0MEM1_A1MEM1_A2MEM1_A3MEM1_A4MEM1_A5MEM1_A6MEM1_A7MEM1_A8MEM1_A9MEM1_A10MEM1_A11MEM1_A12MEM1_A13MEM1_A14MEM1_BA0MEM1_BA1MEM1_BA2Memory U42Pin NumberN3P7P3N2P8P2R8R2T8R3L7R7N7T3T7M2N8M3Pin NameA0A1A2A3A4A5A6A7A8A9A10/APA11A12/BCNNC/A13NC/A14BA0BA1BA2SP605 Hardware User GuideUG526 (v1.9) February 14, 2019

Chapter 1:SP605 Evaluation BoardU1FPGA SPI InterfaceU32DIN, DOUT, CCLKJ17SPI x4FlashMemorySPIX4_CS_BWinbondW25Q64FVSFIG2ON = SPI X4 U32OFF = SPI EXT. J17SPI SelectJumperSPI_CS_B1J46SPI ProgramHeaderUG526_04_020819Figure 1-4:SPI Flash Interface TopologyTable 1-6:SPI x4 Memory ConnectionsU1 FPGA

PinAB2T14R13AA3AB20AA20Y20Schematic Net NameFPGA_PROG_BFPGA_D2_MISO3FPGA_D1_MISO2_RSPI_CS_BFPGA_MOSI_CSI_B_MISO0FPGA_D0_DIN_MISO_MISO1FPGA_CCLKSPI MEM U32Pin #Pin NameSPI HDR J17Pin #123456789 –Pin Name– – –

TMSTDITDOTCK– –19 –

15816IO3_HOLD_BIO2_WP_B –DINIO1_DOUTCLK – – –– –J46.2(1)Notes:

a U1 FPGA pinGNDVCC3V3–

–SPIX4_CS_B –7 –CS_BSee the Winbond Serial Flash Memory Data Sheet for more information. [Ref16]

See the XPS Serial Peripheral Interface Data Sheet (DS570) for more information. [Ref4]SP605 Hardware User GuideUG526 (v1.9) February 14, 2019

Detailed DescriptionU1 FPGA PinN22N20M22M21L19K20H22H21L17K17G22G20K18K19H20J19E22Schematic Net NameFLASH_A0FLASH_A1FLASH_A2FLASH_A3FLASH_A4FLASH_A5FLASH_A6FLASH_A7FLASH_A8FLASH_A9FLASH_A10FLASH_A11FLASH_A12FLASH_A13FLASH_A14FLASH_A15FLASH_A16U25 BPI FLASHPin Number29252423222125Pin NameA1A2A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17SP605 Hardware User GuideUG526 (v1.9) February 14, 2019

Detailed DescriptionSP605 Hardware User GuideUG526 (v1.9) February 14, 2019

发布评论

评论列表 (0)

  1. 暂无评论