2024年2月25日发(作者：盈飞翼)
(4) SPI Digital Timing Diagram
In SPI Mode (SPI_SE = 1), the 3-wire SPI interface is used to configure the frequency as well as
internal registers. Series data sequence of 3-wire SPI is shown in following Figure. This 25-bit
data stream consists of 4 address bits, 1 read/write control bit and 20 data bits. Data transfer is
LSB first.
During write cycle (R/W = 1), the chip will sample the SPIDATA on the rising edge of SPICLK.
Sampled data will be temporally stored in internal shift register. One the rising edge of SPILE, data in
shift register will be latched into specific register according to the address.
During read cycle (R/W = 0), address and read/write control bit are sampled at rising edge of
SPICLK, but the data bits are sent at the falling edge of SPICLK.
LSB
1st data
MSB 2nd data
Invalid Data
SPILE
SPIDATA
A0
A1
A2 A3
R/W
D0
D1
D18
D19
SPICLK
t 1
t 2
t 3
t 6
t 7
t
t 4 t 5
Figure 6.1 Series data sequence on SPI interface
Unit
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
Typ.
Max.
t1 20 - -
t2 20 - -
t3 30 - -
t4 30 - -
t5 100 - -
t6 20 - -
t7 100 - -
Note:
1.) On the rising edge of the SPICLK, one bit of data is transferred into the shift register.
2.) SPILE should be “L” when the data is transferred into the shift register.
Channel Selection Table
When pin 7 (SPI_SE) is set at low voltage, the chip works as in the easy channel selection mode and
the pins 4(SPIDATA/CS0), 5(SPILE/CS1), 6(SPICLK/CS2)，48(S) and 8(BX) are used for channel
selection. Channel frequencies refer to below table.
SPI_SE
Band
BX
S
0
1
X
X
5GHz
Band
0
0
0
1
A
B
E
SPI
0
0
1
X
000
5865M
5733M
5705M
001
5845M
5752M
5685M
010
5825M
CS[2:0]
011 100 101 110 111
5805M 5785M 5765M 5745M 5725M
5771M 5790M 5809M 5828M 5847M 5866M
5665M 5645M 5885M 5905M 5925M 5945M
three wire SPI control pins
SPI mode
When pin 7 (SPI_SE) is set at high (3.3V), the chip works as in the SPI mode and the pins
4(SPIDATA/CS0), 5(SPILE/CS1) and 6(SPICLK/CS2) are used for „SPI‟ inputs for 3-wire programming
Address 0x00: Synthesizer Register A
Bits 19 18 17 16 15
14 13 12 11 10 9 8 7 6 5 4
3
2
1
0
Name
5G Default
0
0
－
0
0
0
0 0
0
0
0
SYN_RF_R_REG [14:0]
0 0 0 0 0
0
1
0
0
0
SYN_RF_R_REG [14:0]:
Default
5.8GHz: 0010H
R-counter divider ratio control for RF Synthesizer.
For 5.8GHz Default: 00008H
Crystal clock (Fosc )=: 8MHz
Reference clock=crystal clock/R-counter=8MHz/8=1MHz
Address 0x01: Synthesizer Register B
11 10
9
8
7
6
5
4
2
0 Bits 19 18 17 16 15
14 13 12
3
1
Name
5G Default
0
0
0
0
SYN_RF_N_REG [12:0]
0
0
1
0
0
0
SYN_RF_A_REG [6:0]
0
0 1 0 1 0
0
1
0
1
Default
5.8GHz: 02A05H
Synthesizer counter default setting ( 5.8Ghz band:5865MHz)
For 5.8Ghz band, FLO = 2*(N*32+A)*(Fosc/R)
Example: default FRF=5865MHz, FLO=5865-479=5386MHz, Fosc=8MHz,
R=8 5385/2=(N*32+A)*8Mhz/8=2*(N*32+A)*1MHz
N=84(=1010100), A5(=0101)
For 5.8GHz default: 02A05H
SYN_RF_N_REG [12:0]: N counter divider ratio control for RF Synthesizer.
SYN_RF_A_REG [6:0]: A counter divider ratio control for RF Synthesizer.
Address 0x02: Synthesizer Register C
Bits 19
18 17 16 15
14
13 12 11 10 9
7 8
6 5
4
3 2 1
0
Name
AGC_6M
[2:0]
AGC_6M5
[2:0]
CC_VCO
[1:0]
CP_5GLO
[2:0]
CP_FT
[2:0]
SCCTL
MOUT
[1:0]
PRES_FT
[2:0]
Default
1
1
0
0
1 0 0
0
0 1 1
0
1
1
0
1
1
0
6M Audio Demodulator AGC control
6M5 Audio Demodulator AGC control
VCO current control
5G VCO buffer current control
Charge pump current control (from 50uA to 6mA, default=100uA)
CP current test control
1
1
Default: FFE44H
AGC_6M [2:0]
AGC_6M5 [2:0]
CC_VCO [1:0]
CP_5GLO [2:0]
CP_FT [2:0]
SC_CTL:
MOUT [1:0]
PRES_FT [2:0]
Multi-function output select
(RF R divider output, RF prescaler output, lock in detect)
Prescaler tail current control (20 ~ 140uA).
Address 0x03: Synthesizer Register D
7
6 5 4
3
2 Bits 19
18 17 16 15
14
13 12 11 10 9
8
SYN_C3
SYN_CZ
SYN_RZ
1
Name
－
0
[2:0]
[2:0]
0
[7:0]
Default 0
0 0 0 0
0
1
1
1 0
1 1
0 0
0
0
0 0
0
Loop filter C3 control
Loop filter CZ control
Loop filter RZ control
Default: 03980H
SYN_C3 [2:0]:
SYN_CZ [2:0]:
SYN_RZ [7:0]:
Address 0x04: VCO Switch-Cap Control Register
7
6
5
1 Bits 19
18 17 16 15
14
13 12 11 10 9
8
4
3 2
0
Name
RFVCO_EX_CAP
[4:0]
VCO480_EX_CAP
[4:0
]
VCO6M _EX_CAP
VCO6M5_EX_CAP
[4:0]
[4:0]
Default 0
0 0 1 1
1
1
0
0
0
0
1
1
1 0
0
1
1 1
0
For RF VCO adjustment
For IF VCOadjustment
For 6M VCOadjustment
For 6M5 VCOadjustment
Default: 7ABEFH
RFVCO_EX_CAP [4:0]:
480VCO_EX_CAP [4:0]:
6MVCO_EX_CAP [4:0]:
6M5VCO_EX_CAP [4:0]:
Address 0x05: DFC Control Register
Bits 19
18
17
16
15 14 13 12
11 10 9 8 7
6
5 4 3 2 1 0
_ENRECAL
_OKRF
_OKIF
_OK6M
Name
R [5:0]
_OK6M5
VCODFC_OVP DFC480_OVP AUDFC_OVP
[2:0]
[2:0]
[2:0]
Default
0
1
1
1
1 1
1
0
0
0
0
1
1
1 0
1
0
0
1
0
EN_RECAL:
R [5:0]:
OK_RF:
OK_IF:
OK_6M:
OK_6M5:
VCODFC_OVP [2:0]:
DFC480_OVP [2:0]:
AUDFC_OVP [2:0]:
DFC reference clock control, set default value to 63.
RF VCO fine tune
IF VCO fine tune
6M VCO fine tune
6M5 VCO fine tune
RF VCO setting
IF VCO setting
6M/6M5 VCO setting
Address 0x06: 6M Audio Demodulator Control Register
6
4 3
2
1
0
Bits 19
18
Name
16
15 14
6M_ICP [5:0]
17 13 12 11 10 9 8 7
6M_C3 [2:0]
6M_CZ [2:0]
5
6M_RZ [7:0]
Default 1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
0
Default: 82408H
6M_ICP [5:0]:
6M_C3 [2:0]:
6M_CZ [2:0]:
6M_RZ [7:0]:
6M Charge-Pump current control
6M Loop Filter Adjusting
6M Loop Filter Adjusting
6M Loop Filter Adjusting
Address 0x07: 6M5 Audio Demodulator Control Register
6
4 3
2
1
0
Bits 19
18
17
16
15 14 13 12 11 10 9 8 7
Name
6M5_ICP [5:0]
6M5_C3 [2:0] 6M5_CZ [2:0]
5
6M5_RZ [7:0]
Default 1
0
0
0
0
0
1
0
0
1
0
0
0
0
0 1 0 0 0
0
Default: 82408H
6M5_ICP [5:0]:
6M5_C3 [2:0]:
6M5_CZ [2:0]:
6M5_RZ [7:0]:
6M5 Charge-Pump current control
6M5 Loop Filter Adjusting
6M5 Loop Filter Adjusting
6M5 Loop Filter Adjusting
Address 0x08: Receiver Control Register 1
15 14 13 12 11 10
Bits 19
18 17 16 9
8 7 6 5 4 3 2 1 0
Name
－
Reserved
CP_MIXER
[2:0]
IFA_GN
[2:0]
VAMP_GN
[7:0]
Default
0
0
0
0
0
0
1
1
1
1
1
1
0
1
0
0
0
0
0
0
Default: 0FF80H
CP_MIXER [2:0]:
IFA_GN [2:0]:
VAMP_GN [7:0]:
RF Mixer current control
IFABF gain control
Video Amp gain control 2
Address 0x09: Receiver Control Register 2
Bits 19 18 17
16 15 14 13 12 11 10 9 8 7
6 5 4 3 2 1 0
Name
Default
IFAF_GN
[2:0]
REGBS_VADJ REGIF_VADJ
[2:0]
[2:0]
BC
[2:0]
RSSI_SQUELCH_D
[7:0]
1 0
1
1
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
Default: B2007H
IFAF_GN [2:0]:
REGBS_VADJ [2:0]:
REGIF_VADJ [2:0]:
BC [2:0]:
RSSI_SQUELCH_D [7:0]:
IFAAF gain control
BS regulator reference voltage adjust
IF regulator reference voltage adjust
BC adjust
RSSI & noise squelch control
Address 0x0A: Power Down Control Register
19
18 17 16 15 14 13 12 11
10 Bits 9
8 7 6 5 4 3 2 1 0
_PDVCLAMP
__PDIFDEMOD
__PDRSSISQUELCH
_PDREGBS
_PDREG1D8
_PDREGIF
Name
_PDPLL1D8
_PD5GVCO
_PDDIV4
_PDAU6M5
_PDVAMP
_PDIFAF
_PDMIXER
_PDIFABF
_PDAU6M
_PDDIV80
_PD6M5
_PDSYN
PDBC_
PD6M_
5G Default
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
1
0
0
1
1
Default:
5.8GHz: 10C13H
PD_VCLAMP:
PD_VAMP:
PD_IF_DEMOD:
PD_IFAF:
PD_RSSI_SQUELCH:
PD_REGBS:
PD_REGIF:
PD_BC:
PD_DIV4:
PD_5GVCO:
Video clamp power down control
Video amp power down control
IF demodulator power down control
IFAF power down control
RSSI & noise squelch power down control
BS regulator power down control
IF regulator power down control
BC power down control
Divide-by-4 power down control
5G VCO power down control
2024年2月25日发(作者：盈飞翼)
(4) SPI Digital Timing Diagram
In SPI Mode (SPI_SE = 1), the 3-wire SPI interface is used to configure the frequency as well as
internal registers. Series data sequence of 3-wire SPI is shown in following Figure. This 25-bit
data stream consists of 4 address bits, 1 read/write control bit and 20 data bits. Data transfer is
LSB first.
During write cycle (R/W = 1), the chip will sample the SPIDATA on the rising edge of SPICLK.
Sampled data will be temporally stored in internal shift register. One the rising edge of SPILE, data in
shift register will be latched into specific register according to the address.
During read cycle (R/W = 0), address and read/write control bit are sampled at rising edge of
SPICLK, but the data bits are sent at the falling edge of SPICLK.
LSB
1st data
MSB 2nd data
Invalid Data
SPILE
SPIDATA
A0
A1
A2 A3
R/W
D0
D1
D18
D19
SPICLK
t 1
t 2
t 3
t 6
t 7
t
t 4 t 5
Figure 6.1 Series data sequence on SPI interface
Unit
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
Typ.
Max.
t1 20 - -
t2 20 - -
t3 30 - -
t4 30 - -
t5 100 - -
t6 20 - -
t7 100 - -
Note:
1.) On the rising edge of the SPICLK, one bit of data is transferred into the shift register.
2.) SPILE should be “L” when the data is transferred into the shift register.
Channel Selection Table
When pin 7 (SPI_SE) is set at low voltage, the chip works as in the easy channel selection mode and
the pins 4(SPIDATA/CS0), 5(SPILE/CS1), 6(SPICLK/CS2)，48(S) and 8(BX) are used for channel
selection. Channel frequencies refer to below table.
SPI_SE
Band
BX
S
0
1
X
X
5GHz
Band
0
0
0
1
A
B
E
SPI
0
0
1
X
000
5865M
5733M
5705M
001
5845M
5752M
5685M
010
5825M
CS[2:0]
011 100 101 110 111
5805M 5785M 5765M 5745M 5725M
5771M 5790M 5809M 5828M 5847M 5866M
5665M 5645M 5885M 5905M 5925M 5945M
three wire SPI control pins
SPI mode
When pin 7 (SPI_SE) is set at high (3.3V), the chip works as in the SPI mode and the pins
4(SPIDATA/CS0), 5(SPILE/CS1) and 6(SPICLK/CS2) are used for „SPI‟ inputs for 3-wire programming
Address 0x00: Synthesizer Register A
Bits 19 18 17 16 15
14 13 12 11 10 9 8 7 6 5 4
3
2
1
0
Name
5G Default
0
0
－
0
0
0
0 0
0
0
0
SYN_RF_R_REG [14:0]
0 0 0 0 0
0
1
0
0
0
SYN_RF_R_REG [14:0]:
Default
5.8GHz: 0010H
R-counter divider ratio control for RF Synthesizer.
For 5.8GHz Default: 00008H
Crystal clock (Fosc )=: 8MHz
Reference clock=crystal clock/R-counter=8MHz/8=1MHz
Address 0x01: Synthesizer Register B
11 10
9
8
7
6
5
4
2
0 Bits 19 18 17 16 15
14 13 12
3
1
Name
5G Default
0
0
0
0
SYN_RF_N_REG [12:0]
0
0
1
0
0
0
SYN_RF_A_REG [6:0]
0
0 1 0 1 0
0
1
0
1
Default
5.8GHz: 02A05H
Synthesizer counter default setting ( 5.8Ghz band:5865MHz)
For 5.8Ghz band, FLO = 2*(N*32+A)*(Fosc/R)
Example: default FRF=5865MHz, FLO=5865-479=5386MHz, Fosc=8MHz,
R=8 5385/2=(N*32+A)*8Mhz/8=2*(N*32+A)*1MHz
N=84(=1010100), A5(=0101)
For 5.8GHz default: 02A05H
SYN_RF_N_REG [12:0]: N counter divider ratio control for RF Synthesizer.
SYN_RF_A_REG [6:0]: A counter divider ratio control for RF Synthesizer.
Address 0x02: Synthesizer Register C
Bits 19
18 17 16 15
14
13 12 11 10 9
7 8
6 5
4
3 2 1
0
Name
AGC_6M
[2:0]
AGC_6M5
[2:0]
CC_VCO
[1:0]
CP_5GLO
[2:0]
CP_FT
[2:0]
SCCTL
MOUT
[1:0]
PRES_FT
[2:0]
Default
1
1
0
0
1 0 0
0
0 1 1
0
1
1
0
1
1
0
6M Audio Demodulator AGC control
6M5 Audio Demodulator AGC control
VCO current control
5G VCO buffer current control
Charge pump current control (from 50uA to 6mA, default=100uA)
CP current test control
1
1
Default: FFE44H
AGC_6M [2:0]
AGC_6M5 [2:0]
CC_VCO [1:0]
CP_5GLO [2:0]
CP_FT [2:0]
SC_CTL:
MOUT [1:0]
PRES_FT [2:0]
Multi-function output select
(RF R divider output, RF prescaler output, lock in detect)
Prescaler tail current control (20 ~ 140uA).
Address 0x03: Synthesizer Register D
7
6 5 4
3
2 Bits 19
18 17 16 15
14
13 12 11 10 9
8
SYN_C3
SYN_CZ
SYN_RZ
1
Name
－
0
[2:0]
[2:0]
0
[7:0]
Default 0
0 0 0 0
0
1
1
1 0
1 1
0 0
0
0
0 0
0
Loop filter C3 control
Loop filter CZ control
Loop filter RZ control
Default: 03980H
SYN_C3 [2:0]:
SYN_CZ [2:0]:
SYN_RZ [7:0]:
Address 0x04: VCO Switch-Cap Control Register
7
6
5
1 Bits 19
18 17 16 15
14
13 12 11 10 9
8
4
3 2
0
Name
RFVCO_EX_CAP
[4:0]
VCO480_EX_CAP
[4:0
]
VCO6M _EX_CAP
VCO6M5_EX_CAP
[4:0]
[4:0]
Default 0
0 0 1 1
1
1
0
0
0
0
1
1
1 0
0
1
1 1
0
For RF VCO adjustment
For IF VCOadjustment
For 6M VCOadjustment
For 6M5 VCOadjustment
Default: 7ABEFH
RFVCO_EX_CAP [4:0]:
480VCO_EX_CAP [4:0]:
6MVCO_EX_CAP [4:0]:
6M5VCO_EX_CAP [4:0]:
Address 0x05: DFC Control Register
Bits 19
18
17
16
15 14 13 12
11 10 9 8 7
6
5 4 3 2 1 0
_ENRECAL
_OKRF
_OKIF
_OK6M
Name
R [5:0]
_OK6M5
VCODFC_OVP DFC480_OVP AUDFC_OVP
[2:0]
[2:0]
[2:0]
Default
0
1
1
1
1 1
1
0
0
0
0
1
1
1 0
1
0
0
1
0
EN_RECAL:
R [5:0]:
OK_RF:
OK_IF:
OK_6M:
OK_6M5:
VCODFC_OVP [2:0]:
DFC480_OVP [2:0]:
AUDFC_OVP [2:0]:
DFC reference clock control, set default value to 63.
RF VCO fine tune
IF VCO fine tune
6M VCO fine tune
6M5 VCO fine tune
RF VCO setting
IF VCO setting
6M/6M5 VCO setting
Address 0x06: 6M Audio Demodulator Control Register
6
4 3
2
1
0
Bits 19
18
Name
16
15 14
6M_ICP [5:0]
17 13 12 11 10 9 8 7
6M_C3 [2:0]
6M_CZ [2:0]
5
6M_RZ [7:0]
Default 1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
0
Default: 82408H
6M_ICP [5:0]:
6M_C3 [2:0]:
6M_CZ [2:0]:
6M_RZ [7:0]:
6M Charge-Pump current control
6M Loop Filter Adjusting
6M Loop Filter Adjusting
6M Loop Filter Adjusting
Address 0x07: 6M5 Audio Demodulator Control Register
6
4 3
2
1
0
Bits 19
18
17
16
15 14 13 12 11 10 9 8 7
Name
6M5_ICP [5:0]
6M5_C3 [2:0] 6M5_CZ [2:0]
5
6M5_RZ [7:0]
Default 1
0
0
0
0
0
1
0
0
1
0
0
0
0
0 1 0 0 0
0
Default: 82408H
6M5_ICP [5:0]:
6M5_C3 [2:0]:
6M5_CZ [2:0]:
6M5_RZ [7:0]:
6M5 Charge-Pump current control
6M5 Loop Filter Adjusting
6M5 Loop Filter Adjusting
6M5 Loop Filter Adjusting
Address 0x08: Receiver Control Register 1
15 14 13 12 11 10
Bits 19
18 17 16 9
8 7 6 5 4 3 2 1 0
Name
－
Reserved
CP_MIXER
[2:0]
IFA_GN
[2:0]
VAMP_GN
[7:0]
Default
0
0
0
0
0
0
1
1
1
1
1
1
0
1
0
0
0
0
0
0
Default: 0FF80H
CP_MIXER [2:0]:
IFA_GN [2:0]:
VAMP_GN [7:0]:
RF Mixer current control
IFABF gain control
Video Amp gain control 2
Address 0x09: Receiver Control Register 2
Bits 19 18 17
16 15 14 13 12 11 10 9 8 7
6 5 4 3 2 1 0
Name
Default
IFAF_GN
[2:0]
REGBS_VADJ REGIF_VADJ
[2:0]
[2:0]
BC
[2:0]
RSSI_SQUELCH_D
[7:0]
1 0
1
1
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
Default: B2007H
IFAF_GN [2:0]:
REGBS_VADJ [2:0]:
REGIF_VADJ [2:0]:
BC [2:0]:
RSSI_SQUELCH_D [7:0]:
IFAAF gain control
BS regulator reference voltage adjust
IF regulator reference voltage adjust
BC adjust
RSSI & noise squelch control
Address 0x0A: Power Down Control Register
19
18 17 16 15 14 13 12 11
10 Bits 9
8 7 6 5 4 3 2 1 0
_PDVCLAMP
__PDIFDEMOD
__PDRSSISQUELCH
_PDREGBS
_PDREG1D8
_PDREGIF
Name
_PDPLL1D8
_PD5GVCO
_PDDIV4
_PDAU6M5
_PDVAMP
_PDIFAF
_PDMIXER
_PDIFABF
_PDAU6M
_PDDIV80
_PD6M5
_PDSYN
PDBC_
PD6M_
5G Default
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
1
0
0
1
1
Default:
5.8GHz: 10C13H
PD_VCLAMP:
PD_VAMP:
PD_IF_DEMOD:
PD_IFAF:
PD_RSSI_SQUELCH:
PD_REGBS:
PD_REGIF:
PD_BC:
PD_DIV4:
PD_5GVCO:
Video clamp power down control
Video amp power down control
IF demodulator power down control
IFAF power down control
RSSI & noise squelch power down control
BS regulator power down control
IF regulator power down control
BC power down control
Divide-by-4 power down control
5G VCO power down control