2024年4月2日发(作者：步丰熙)
Pinout Tables
Summary
This chapter includes the pinout information tables for the following packages:
•
•
•
•
•
•
•
•
•
•
Table2-1, “FF323 Package—LX20T and LX30T,” on page21
Table2-2, “FF324 Package—LX30 and LX50,” on page32
Table2-3, “FF665 Package—LX30T, FX30T, LX50T, SX35T, SX50T, and FX70T,” on
page
42
Table2-4, “FF676 Package—LX30, LX50, LX85, and LX110,” on page63
Table2-5, “FF1136 Package—LX50T, FX70T, LX85T, LX110T, LX155T, SX50T, SX95T
and FX100T,” on page
84
Table2-6, “FF1153 Package—LX50, LX85, LX110, and LX155,” on page120
Table2-7, “FF1156 Package—TX150T,” on page156
Table2-8, “FF1738 Package—FX100T, LX110T, FX130T, LX155T, FX200T, LX220T,
SX240T, and LX330T,” on page
192
Table2-9, “FF1759 Package—TX150T and TX240T,” on page253
Table2-10, “FF1760 Package—LX110, LX155, LX220, and LX330,” on page307
FF323 Package—LX20T and LX30T
Table 2-1:FF323 Package—LX20T and LX30T
BankPin DescriptionPin NumberNo Connect (NC)
0
0
0
0
0
0
0
0
0
0
DXP_0
DXN_0
AVDD_0
AVSS_0
VP_0
VN_0
VREFP_0
VREFN_0
VBATT_0
PROGRAM_B_0
K10
K9
G10
G9
H10
J9
J10
H9
D5
E11
Virtex-5 FPGA Packaging and Pinout Specification
Chapter 2:Pinout Tables
Table 2-1:FF323 Package—LX20T and LX30T (Continued)
BankPin DescriptionPin NumberNo Connect (NC)
0
0
0
0
0
0
0
0
0
0
0
HSWAPEN_0
D_IN_0
DONE_0
CCLK_0
INIT_B_0
CS_B_0
RDWR_B_0
RSVD
(3)
RSVD
(3)
TCK_0
M0_0
F11
F6
F9
E10
B5
A4
E6
L9
L10
M6
G6
Virtex-5 FPGA Packaging and Pinout Specification UG195 (v4.9)
August 9, 2018
Chapter 2:Pinout Tables
Table 2-1:FF323 Package—LX20T and LX30T (Continued)
BankPin DescriptionPin NumberNo Connect (NC)
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
0
0
1
1
1
2
2
2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCO_0
VCCO_0
VCCO_1
VCCO_1
VCCO_1
VCCO_2
VCCO_2
VCCO_2
M17
M4
N14
N2
N9
P1
P6
R18
T10
T15
U12
U7
V4
G12
J13
K7
L6
L8
G8
H11
H7
J12
J6
J8
K11
K5
N4
A10
B7
E8
R3
T5
U2
Virtex-5 FPGA Packaging and Pinout Specification UG195 (v4.9)
August 9, 2018
FF324 Package—LX30 and LX50
Virtex-5 FPGA Packaging and Pinout Specification
Chapter 2:Pinout Tables
Virtex-5 FPGA Packaging and Pinout Specification UG195 (v4.9)
August 9, 2018
2024年4月2日发(作者：步丰熙)
Pinout Tables
Summary
This chapter includes the pinout information tables for the following packages:
•
•
•
•
•
•
•
•
•
•
Table2-1, “FF323 Package—LX20T and LX30T,” on page21
Table2-2, “FF324 Package—LX30 and LX50,” on page32
Table2-3, “FF665 Package—LX30T, FX30T, LX50T, SX35T, SX50T, and FX70T,” on
page
42
Table2-4, “FF676 Package—LX30, LX50, LX85, and LX110,” on page63
Table2-5, “FF1136 Package—LX50T, FX70T, LX85T, LX110T, LX155T, SX50T, SX95T
and FX100T,” on page
84
Table2-6, “FF1153 Package—LX50, LX85, LX110, and LX155,” on page120
Table2-7, “FF1156 Package—TX150T,” on page156
Table2-8, “FF1738 Package—FX100T, LX110T, FX130T, LX155T, FX200T, LX220T,
SX240T, and LX330T,” on page
192
Table2-9, “FF1759 Package—TX150T and TX240T,” on page253
Table2-10, “FF1760 Package—LX110, LX155, LX220, and LX330,” on page307
FF323 Package—LX20T and LX30T
Table 2-1:FF323 Package—LX20T and LX30T
BankPin DescriptionPin NumberNo Connect (NC)
0
0
0
0
0
0
0
0
0
0
DXP_0
DXN_0
AVDD_0
AVSS_0
VP_0
VN_0
VREFP_0
VREFN_0
VBATT_0
PROGRAM_B_0
K10
K9
G10
G9
H10
J9
J10
H9
D5
E11
Virtex-5 FPGA Packaging and Pinout Specification
Chapter 2:Pinout Tables
Table 2-1:FF323 Package—LX20T and LX30T (Continued)
BankPin DescriptionPin NumberNo Connect (NC)
0
0
0
0
0
0
0
0
0
0
0
HSWAPEN_0
D_IN_0
DONE_0
CCLK_0
INIT_B_0
CS_B_0
RDWR_B_0
RSVD
(3)
RSVD
(3)
TCK_0
M0_0
F11
F6
F9
E10
B5
A4
E6
L9
L10
M6
G6
Virtex-5 FPGA Packaging and Pinout Specification UG195 (v4.9)
August 9, 2018
Chapter 2:Pinout Tables
Table 2-1:FF323 Package—LX20T and LX30T (Continued)
BankPin DescriptionPin NumberNo Connect (NC)
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
0
0
1
1
1
2
2
2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCO_0
VCCO_0
VCCO_1
VCCO_1
VCCO_1
VCCO_2
VCCO_2
VCCO_2
M17
M4
N14
N2
N9
P1
P6
R18
T10
T15
U12
U7
V4
G12
J13
K7
L6
L8
G8
H11
H7
J12
J6
J8
K11
K5
N4
A10
B7
E8
R3
T5
U2
Virtex-5 FPGA Packaging and Pinout Specification UG195 (v4.9)
August 9, 2018
FF324 Package—LX30 and LX50
Virtex-5 FPGA Packaging and Pinout Specification
Chapter 2:Pinout Tables
Virtex-5 FPGA Packaging and Pinout Specification UG195 (v4.9)
August 9, 2018