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SL40N10原厂资料

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2024年4月3日发(作者:隽欣怿)

L 40N10

N-Channel Enhancement Mode Field Effect Transistor

Features

z 100V/40A

R

DS (ON)

= 33mΩ (Type) @ VGS=10V

R

DS (ON)

= 45mΩ (Type) @ VGS=4.5V

z Super High Dense Cell Design

z Reliable and Rugged

z TO-252 package

Pin Description

PIN1

Lead Free and Green Devices Available

(ROHS Compliant)

Applications

z Power Management in Notebook Computer,

Portable Equipment and Battery Powered System.

ABSOLUTE MAXIMUM RATINGS

(Ta = 25°C unless otherwise noted)

Symbol Parameter Value Unit

V

DSS

Drain-to-Source Voltage 100 V

V

GSS

Gate-to-Source Voltage ±20 V

Continuous Drain Current@ T

J

= 125℃

40 I

D

*

V

GS

=10V A

I

DM

* Pulsed Drain Current (tp ≤10us) 110

Diode Continuous Forward Current

I

S

* 1.25 A

TA = 25℃

50 W

P

D

* Total Power Dissipation

TA = 100℃

25 W

T

J

,

Operating and Storage Temperature Range -55 to 150 ℃

T

STG

Thermal Resistance,

Rth J

A

*

50 ℃/W

Junction-to-Ambient

Maximum Lead Temperature for

T

L

260 ℃

Soldering Purposes, 1/8″from case for 10 seconds

Note: *Surface Mounted on 1in

*

1in

pad

area, t

≤ 10 Secedes.

May 2011 Doc ID 0065 Rev 1 1/8

L 40N10

Electrical characteristics

Electrical characteristics

TCASE = 25 °C unless otherwise specified

Parameter Symbol Test Conditions Min. Typ.

z states

Drain-Source Breakdown Voltage

Zero Gate Voltage Drain Current

Gate-body leakage current

BVDSS

I

DSS

I

GSS

V

GS(th)

R

DS(ON)(a)

VSD

gFS

V

GS

=0V, I

DS

=250μA

V

DS

=80V, V

GS

=0V

V

GS

=±20V,V

DS

=0V

V

DS

=V

GS

,I

D

=250µA

V

GS

=10V,I

D

=20A

100

1

V

µA

nA ±100

Gate Threshold Voltage

Drain-Source On-state Resistance

Diode Forward Voltage

Forward Tran conductance

1.5 1.8 2.5 V

33 38

mΩ

V

GS

=4.5V,I

D

=10A

V

GS

=0V,IS=1.25A

V

GS

=7V,I

D

=1A

43

46

0.84 1.3

V

6

S

z Gate charge

Total gate charge

Gate-source charge

Input capacitance

Q

g

Q

gs

Q

g

V

DS

=15V,V

GS

=0V

f=1.0MHZ

V

DS

=15V,I

D

=1A ,

V

GS

=10V

18

2.4

nC

4.4

z Dynamic (b)

Input capacitance

Output capacitance

Reverse transfer capacitance

C

iss

C

oss

C

rss

1079

119

pF

70

z Switching times

Turn-On Delay Time

Rise Time

Turn-Off Delay Time

Fall Time

t

D(ON)

tr

t

D(OFF)

tf

V

DD

=15V,

I

D

=1A,

V

GEN

=10V

RL=10ohm ,

R

GEN

=10ohm

12

10

52

ns

28

Notes

(a). Surface Mounted on FR4 Board, t≦10sec

(b). Pulse Test: Pulse Width≦300Us, Duty≦2%

(c). Guaranteed by design, not subject to production testing.

May 2011

Doc ID 0065 Rev 1 2/8

2024年4月3日发(作者:隽欣怿)

L 40N10

N-Channel Enhancement Mode Field Effect Transistor

Features

z 100V/40A

R

DS (ON)

= 33mΩ (Type) @ VGS=10V

R

DS (ON)

= 45mΩ (Type) @ VGS=4.5V

z Super High Dense Cell Design

z Reliable and Rugged

z TO-252 package

Pin Description

PIN1

Lead Free and Green Devices Available

(ROHS Compliant)

Applications

z Power Management in Notebook Computer,

Portable Equipment and Battery Powered System.

ABSOLUTE MAXIMUM RATINGS

(Ta = 25°C unless otherwise noted)

Symbol Parameter Value Unit

V

DSS

Drain-to-Source Voltage 100 V

V

GSS

Gate-to-Source Voltage ±20 V

Continuous Drain Current@ T

J

= 125℃

40 I

D

*

V

GS

=10V A

I

DM

* Pulsed Drain Current (tp ≤10us) 110

Diode Continuous Forward Current

I

S

* 1.25 A

TA = 25℃

50 W

P

D

* Total Power Dissipation

TA = 100℃

25 W

T

J

,

Operating and Storage Temperature Range -55 to 150 ℃

T

STG

Thermal Resistance,

Rth J

A

*

50 ℃/W

Junction-to-Ambient

Maximum Lead Temperature for

T

L

260 ℃

Soldering Purposes, 1/8″from case for 10 seconds

Note: *Surface Mounted on 1in

*

1in

pad

area, t

≤ 10 Secedes.

May 2011 Doc ID 0065 Rev 1 1/8

L 40N10

Electrical characteristics

Electrical characteristics

TCASE = 25 °C unless otherwise specified

Parameter Symbol Test Conditions Min. Typ.

z states

Drain-Source Breakdown Voltage

Zero Gate Voltage Drain Current

Gate-body leakage current

BVDSS

I

DSS

I

GSS

V

GS(th)

R

DS(ON)(a)

VSD

gFS

V

GS

=0V, I

DS

=250μA

V

DS

=80V, V

GS

=0V

V

GS

=±20V,V

DS

=0V

V

DS

=V

GS

,I

D

=250µA

V

GS

=10V,I

D

=20A

100

1

V

µA

nA ±100

Gate Threshold Voltage

Drain-Source On-state Resistance

Diode Forward Voltage

Forward Tran conductance

1.5 1.8 2.5 V

33 38

mΩ

V

GS

=4.5V,I

D

=10A

V

GS

=0V,IS=1.25A

V

GS

=7V,I

D

=1A

43

46

0.84 1.3

V

6

S

z Gate charge

Total gate charge

Gate-source charge

Input capacitance

Q

g

Q

gs

Q

g

V

DS

=15V,V

GS

=0V

f=1.0MHZ

V

DS

=15V,I

D

=1A ,

V

GS

=10V

18

2.4

nC

4.4

z Dynamic (b)

Input capacitance

Output capacitance

Reverse transfer capacitance

C

iss

C

oss

C

rss

1079

119

pF

70

z Switching times

Turn-On Delay Time

Rise Time

Turn-Off Delay Time

Fall Time

t

D(ON)

tr

t

D(OFF)

tf

V

DD

=15V,

I

D

=1A,

V

GEN

=10V

RL=10ohm ,

R

GEN

=10ohm

12

10

52

ns

28

Notes

(a). Surface Mounted on FR4 Board, t≦10sec

(b). Pulse Test: Pulse Width≦300Us, Duty≦2%

(c). Guaranteed by design, not subject to production testing.

May 2011

Doc ID 0065 Rev 1 2/8

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