2024年4月4日发(作者：库绣梓)
Die Level Bank Numbering and Clock Pins Overview
Figure1-1 through Figure1-11 visually describe a die view of the FPGA bank numbering.
Table1-7 shows the I/O bank names and locations. Not all banks are bonded out in every
part/package combination.
Table 1-7:Virtex-6 FPGA Bank Numbering
Bank Name
IOCL
IOCR
IOOL
IOOR
Location
I/O center, left bank column
I/O center, right bank column
I/O outer, left bank column
I/O outer, right bank column
Description
Available in every device.
Available in every device.
Only available in all LX, LXT, and SXT
devices.
Device dependent, for LX, LXT, and SXT
devices only.
Bank 0
•
•
•
•
The center column contains Bank 0.
Bank 0 contains dedicated configuration pins.
Bank 0 is filled with CLB_LLs on the top and bottom.
The CMT (MMCM) column is adjacent to the right.
Horizontal Clock Row– HROW
•
•
HROW contains all clock tracks.
HROW is located in the center of a region/bank.
GTX/GTH Transceiver Bank Columns
•
•
One bank contains quad GTX or GTH transceiver banks which equals four GTXE1
primitives or one GTHE1_QUAD primitive.
In the LXT and SXT devices there is a single GTX column and the physical XY
locations for the GTXE1 transceivers always start at location X0Y0 with the lowest
bank number and then increment by one in the vertical Y direction for each GTXE1
transceiver (four Y locations for each quad).
Some HXT devices have two transceiver columns that can contain GTX and/or GTH
transceivers. The physical XY locations for the GTXE1 transceivers always start at
location X0Y0 and X1Y0 with the lowest bank number and then increment by one in
the vertical Y direction for each GTXE1 transceiver (four Y locations for each quad).
When present, GTHE1 transceivers are organized (instantiated) as quads under the
GTHE1_QUAD primitive and start at X0Y0 or X1Y0 (one location for four GTH
transceivers).
The physical XY locations for each IDELAYCNTRL start at X0Y0 in the bottom
left-most bank and then increment by one starting with the lowest bank number in
each column in the vertical Y direction and by one for each column in the horizontal X
direction. IDELAYCNTRLs are located in each of the HROWs.
•
•
Virtex-6 FPGA Packaging
UG365 (v2.6) October 3, 2018
Chapter 1:Packaging Overview
Virtex-6 FPGA Packaging
UG365 (v2.6) October 3, 2018
Chapter 1:Packaging Overview
Figure1-11 shows the I/O and transceiver banks for the XC6VHX565T. The black dots
denote the global clock banks.
GTX/GTH
Banks
108
108
107
HROW
IOCL
Banks
28
28
27
27
26
26
25
25
24
24
23
23
22
22
21
21
20
(2)
20
(2)
Center
Bank
CLB
CLB
CLB
CLB
CLB
CLB
0
CFG
0
CFG
0
CFG
0
CFG
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
MMCM17
IOCR
Banks
38
38
37
37
36
36
35
35
34
34
33
33
32
32
31
31
30
(2)
30
(2)
GTX/GTH
Banks
118
118
117
117
116
116
115
115
114
114
113
113
112
112
111
(1)
111
(1)
110
(1)
110
(1)
MGTAVTTRCAL
MGTRREF
Quad
GTX
Quad
GTH
CMT
MMCM16
MMCM15
CMT
MMCM14
MMCM13
107
106
106
CMT
MMCM12
MMCM11
MGTAVTTRCAL
MGTRREF
105
105
104
104
103
103
102
102
101
101
100
100
CMT
MMCM10
MMCM09
CMT
MMCM08
MMCM07
CMT
MMCM06
MMCM05
CMT
MMCM04
MMCM03
CMT
MMCM02
MMCM01
CMT
MMCM00
Note:
1. Unbonded GTX Quads in FF1923.
2. Unbonded banks in FF1924.
UG365_c1_11_111111
Figure 1-11:XC6VHX565T Banks
Virtex-6 FPGA Packaging
UG365 (v2.6) October 3, 2018
FF1156/RF1156 Package—LX130T, LX195T, LX240T, LX365T, SX315T, and SX475T
Table 2-5:FF1156/RF1156 Package—LX130T, LX195T, LX240T, LX365T, SX315T,
and SX475T (Cont’d)
Bank
22
22
22
22
22
22
22
22
22
22
22
22
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
Pin DescriptionPin Number
AC19
AD19
AM23
AL23
AK21
AJ21
AM22
AN22
AG20
AG21
AP22
AN23
AH27
AH28
AN30
AM30
AG25
AG26
AP30
AP31
AL29
AK29
AN29
AP29
AL28
AK28
AN28
AM28
AH25
AJ25
AN27
AM27
No Connect (NC)
IO_L14P_22
IO_L14N_VREF_22
IO_L15P_22
IO_L15N_22
IO_L16P_22
IO_L16N_22
IO_L17P_22
IO_L17N_22
IO_L18P_22
IO_L18N_22
IO_L19P_22
IO_L19N_22
IO_L0P_23
IO_L0N_23
IO_L1P_23
IO_L1N_23
IO_L2P_23
IO_L2N_23
IO_L3P_23
IO_L3N_23
IO_L4P_23
IO_L4N_VREF_23
IO_L5P_23
IO_L5N_23
IO_L6P_23
IO_L6N_23
IO_L7P_23
IO_L7N_23
IO_L8P_SRCC_23
IO_L8N_SRCC_23
IO_L9P_MRCC_23
IO_L9N_MRCC_23
Virtex-6 FPGA Packaging
UG365 (v2.6) October 3, 2018
Chapter 2:Pinout Tables
Table 2-5:FF1156/RF1156 Package—LX130T, LX195T, LX240T, LX365T, SX315T,
and SX475T (Cont’d)
Bank
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
24
24
24
24
24
24
24
24
24
24
24
24
Pin DescriptionPin Number
AK27
AJ27
AH23
AH24
AK26
AJ26
AL26
AM26
AJ24
AK24
AP27
AP26
AM25
AL25
AN25
AN24
AK23
AL24
AP25
AP24
L23
M22
K24
K23
M23
L24
F24
F23
N23
N24
H23
G23
No Connect (NC)
IO_L10P_MRCC_23
IO_L10N_MRCC_23
IO_L11P_SRCC_23
IO_L11N_SRCC_23
IO_L12P_VRN_23
IO_L12N_VRP_23
IO_L13P_23
IO_L13N_23
IO_L14P_23
IO_L14N_VREF_23
IO_L15P_23
IO_L15N_23
IO_L16P_23
IO_L16N_23
IO_L17P_23
IO_L17N_23
IO_L18P_23
IO_L18N_23
IO_L19P_23
IO_L19N_23
IO_L0P_GC_24
IO_L0N_GC_24
IO_L1P_GC_24
IO_L1N_GC_24
IO_L2P_D15_24
IO_L2N_D14_24
IO_L3P_D13_24
IO_L3N_D12_24
IO_L4P_D11_24
IO_L4N_VREF_D10_24
IO_L5P_D9_24
IO_L5N_D8_24
Virtex-6 FPGA Packaging
UG365 (v2.6) October 3, 2018
2024年4月4日发(作者：库绣梓)
Die Level Bank Numbering and Clock Pins Overview
Figure1-1 through Figure1-11 visually describe a die view of the FPGA bank numbering.
Table1-7 shows the I/O bank names and locations. Not all banks are bonded out in every
part/package combination.
Table 1-7:Virtex-6 FPGA Bank Numbering
Bank Name
IOCL
IOCR
IOOL
IOOR
Location
I/O center, left bank column
I/O center, right bank column
I/O outer, left bank column
I/O outer, right bank column
Description
Available in every device.
Available in every device.
Only available in all LX, LXT, and SXT
devices.
Device dependent, for LX, LXT, and SXT
devices only.
Bank 0
•
•
•
•
The center column contains Bank 0.
Bank 0 contains dedicated configuration pins.
Bank 0 is filled with CLB_LLs on the top and bottom.
The CMT (MMCM) column is adjacent to the right.
Horizontal Clock Row– HROW
•
•
HROW contains all clock tracks.
HROW is located in the center of a region/bank.
GTX/GTH Transceiver Bank Columns
•
•
One bank contains quad GTX or GTH transceiver banks which equals four GTXE1
primitives or one GTHE1_QUAD primitive.
In the LXT and SXT devices there is a single GTX column and the physical XY
locations for the GTXE1 transceivers always start at location X0Y0 with the lowest
bank number and then increment by one in the vertical Y direction for each GTXE1
transceiver (four Y locations for each quad).
Some HXT devices have two transceiver columns that can contain GTX and/or GTH
transceivers. The physical XY locations for the GTXE1 transceivers always start at
location X0Y0 and X1Y0 with the lowest bank number and then increment by one in
the vertical Y direction for each GTXE1 transceiver (four Y locations for each quad).
When present, GTHE1 transceivers are organized (instantiated) as quads under the
GTHE1_QUAD primitive and start at X0Y0 or X1Y0 (one location for four GTH
transceivers).
The physical XY locations for each IDELAYCNTRL start at X0Y0 in the bottom
left-most bank and then increment by one starting with the lowest bank number in
each column in the vertical Y direction and by one for each column in the horizontal X
direction. IDELAYCNTRLs are located in each of the HROWs.
•
•
Virtex-6 FPGA Packaging
UG365 (v2.6) October 3, 2018
Chapter 1:Packaging Overview
Virtex-6 FPGA Packaging
UG365 (v2.6) October 3, 2018
Chapter 1:Packaging Overview
Figure1-11 shows the I/O and transceiver banks for the XC6VHX565T. The black dots
denote the global clock banks.
GTX/GTH
Banks
108
108
107
HROW
IOCL
Banks
28
28
27
27
26
26
25
25
24
24
23
23
22
22
21
21
20
(2)
20
(2)
Center
Bank
CLB
CLB
CLB
CLB
CLB
CLB
0
CFG
0
CFG
0
CFG
0
CFG
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
MMCM17
IOCR
Banks
38
38
37
37
36
36
35
35
34
34
33
33
32
32
31
31
30
(2)
30
(2)
GTX/GTH
Banks
118
118
117
117
116
116
115
115
114
114
113
113
112
112
111
(1)
111
(1)
110
(1)
110
(1)
MGTAVTTRCAL
MGTRREF
Quad
GTX
Quad
GTH
CMT
MMCM16
MMCM15
CMT
MMCM14
MMCM13
107
106
106
CMT
MMCM12
MMCM11
MGTAVTTRCAL
MGTRREF
105
105
104
104
103
103
102
102
101
101
100
100
CMT
MMCM10
MMCM09
CMT
MMCM08
MMCM07
CMT
MMCM06
MMCM05
CMT
MMCM04
MMCM03
CMT
MMCM02
MMCM01
CMT
MMCM00
Note:
1. Unbonded GTX Quads in FF1923.
2. Unbonded banks in FF1924.
UG365_c1_11_111111
Figure 1-11:XC6VHX565T Banks
Virtex-6 FPGA Packaging
UG365 (v2.6) October 3, 2018
FF1156/RF1156 Package—LX130T, LX195T, LX240T, LX365T, SX315T, and SX475T
Table 2-5:FF1156/RF1156 Package—LX130T, LX195T, LX240T, LX365T, SX315T,
and SX475T (Cont’d)
Bank
22
22
22
22
22
22
22
22
22
22
22
22
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
Pin DescriptionPin Number
AC19
AD19
AM23
AL23
AK21
AJ21
AM22
AN22
AG20
AG21
AP22
AN23
AH27
AH28
AN30
AM30
AG25
AG26
AP30
AP31
AL29
AK29
AN29
AP29
AL28
AK28
AN28
AM28
AH25
AJ25
AN27
AM27
No Connect (NC)
IO_L14P_22
IO_L14N_VREF_22
IO_L15P_22
IO_L15N_22
IO_L16P_22
IO_L16N_22
IO_L17P_22
IO_L17N_22
IO_L18P_22
IO_L18N_22
IO_L19P_22
IO_L19N_22
IO_L0P_23
IO_L0N_23
IO_L1P_23
IO_L1N_23
IO_L2P_23
IO_L2N_23
IO_L3P_23
IO_L3N_23
IO_L4P_23
IO_L4N_VREF_23
IO_L5P_23
IO_L5N_23
IO_L6P_23
IO_L6N_23
IO_L7P_23
IO_L7N_23
IO_L8P_SRCC_23
IO_L8N_SRCC_23
IO_L9P_MRCC_23
IO_L9N_MRCC_23
Virtex-6 FPGA Packaging
UG365 (v2.6) October 3, 2018
Chapter 2:Pinout Tables
Table 2-5:FF1156/RF1156 Package—LX130T, LX195T, LX240T, LX365T, SX315T,
and SX475T (Cont’d)
Bank
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
24
24
24
24
24
24
24
24
24
24
24
24
Pin DescriptionPin Number
AK27
AJ27
AH23
AH24
AK26
AJ26
AL26
AM26
AJ24
AK24
AP27
AP26
AM25
AL25
AN25
AN24
AK23
AL24
AP25
AP24
L23
M22
K24
K23
M23
L24
F24
F23
N23
N24
H23
G23
No Connect (NC)
IO_L10P_MRCC_23
IO_L10N_MRCC_23
IO_L11P_SRCC_23
IO_L11N_SRCC_23
IO_L12P_VRN_23
IO_L12N_VRP_23
IO_L13P_23
IO_L13N_23
IO_L14P_23
IO_L14N_VREF_23
IO_L15P_23
IO_L15N_23
IO_L16P_23
IO_L16N_23
IO_L17P_23
IO_L17N_23
IO_L18P_23
IO_L18N_23
IO_L19P_23
IO_L19N_23
IO_L0P_GC_24
IO_L0N_GC_24
IO_L1P_GC_24
IO_L1N_GC_24
IO_L2P_D15_24
IO_L2N_D14_24
IO_L3P_D13_24
IO_L3N_D12_24
IO_L4P_D11_24
IO_L4N_VREF_D10_24
IO_L5P_D9_24
IO_L5N_D8_24
Virtex-6 FPGA Packaging
UG365 (v2.6) October 3, 2018