2024年4月4日发(作者：裴思莹)
Chapter 1:Packaging Overview
Device/Package Combinations and Maximum I/Os
Table1-1 shows the maximum number of user I/Os possible in Virtex-5 FPGA flip-chip
packages. FF denotes flip-chip fine-pitch BGA (1.00 mm pitch).
Table 1-1:Flip-Chip Packages
Packages
FF324
1.00
19 x 19
220
FF665
1.00
27 x 27
360
FF676
1.00
27 x 27
440
FF1136FF1153
1.00
35 x 35
640
1.00
35 x 35
800
FF1156
1.00
35 x 35
360
FF1738
1.00
42.5 x
42.5
960
FF1759
1.00
42.5 x
42.5
680
FF1760
1.00
42.5 x
42.5
1200
Package
Specifications
FF323
Pitch(mm)
Size(mm)
Maximum
I/Os
1.00
19 x 19
172
The number of I/Os per package includes all user I/Os except the 19 pins listed in
Table1-2.
Table 1-2:Virtex-5 FPGA I/O Pinsin the Dedicated Configuration Bank (Bank0)
DXP
DXN
VBATT
PROGRAM_B
HSWAPEN
D_IN
DONE
CCLK_0
INIT_B_0
CS_B_0
RDWR_B_0
TCK_0
M0_0
M1_0
M2_0
TMS
TDI
D_OUT_BUSY
TDO_0
The RocketIO™ GTP transceiver I/O channels for the devices listed in Table1-3 or the GTX
transceiver I/O channels for the devices listed in Table1-4.
Table 1-3:
I/O
Channels
MGTRXP
MGTRXN
MGTTXP
MGTTXN
Notes:
XC5VLX30T has 4 GTP I/O channels in the FF323/FFG323 package and 8 GTP I/O channels in the FF665/FFG665 package.
XC5VLX50T has 8 GTP I/O channels in the FF665/FFG665 package and 12 GTP I/O channels in the FF1136/FFG1136 package.
XC5VSX50T has 8 GTP I/O channels in the FF665/FFG665 package and 12 GTP I/O channels in the FF1136/FFG1136 package.
Number of GTP Transceiver I/O Channels/Device
Device
LX20TLX30T
(1)
SX35TLX50T
(2)
SX50T
(3)
LX85TSX95TLX110TLX155TLX220TSX240TLX330T
4
4
4
4
4 or 8
4 or 8
4 or 8
4 or 8
8
8
8
8
8 or 12
8 or 12
8 or 12
8 or 12
8 or 12
8 or 12
8 or 12
8 or 12
12
12
12
12
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
24
24
24
24
24
24
24
24
Virtex-5 FPGA Packaging and Pinout Specification
Chapter 1:Packaging Overview
Virtex-5 FPGA Packaging and Pinout Specification
Pin Definitions
Virtex-5 FPGA Packaging and Pinout Specificatio
Chapter 1:Packaging Overview
Virtex-5 FPGA Packaging and Pinout Specification
Chapter 2:Pinout Tables
Table 2-8:FF1738 Package—FX100T, LX110T, FX130T, LX155T, FX200T, LX220T,
SX240T, and LX330T (Continued)
Bank
23
23
23
23
23
23
23
23
23
23
23
23
23
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
Pin DescriptionPin Number
J33
K32
J32
L32
L31
P33
P32
R33
R32
T32
U32
U31
T31
J12
H11
G12
G11
F12
F11
E10
F10
K14
K13
K12
J11
J13
H13
H10
J10
H14
H15
K10
No Connect (NC)
IO_L13N_23
IO_L14P_23
IO_L14N_VREF_23
IO_L15P_23
IO_L15N_23
IO_L16P_23
IO_L16N_23
IO_L17P_23
IO_L17N_23
IO_L18P_23
IO_L18N_23
IO_L19P_23
IO_L19N_23
IO_L0P_24
IO_L0N_24
IO_L1P_24
IO_L1N_24
IO_L2P_24
IO_L2N_24
IO_L3P_24
IO_L3N_24
IO_L4P_24
IO_L4N_VREF_24
IO_L5P_24
IO_L5N_24
IO_L6P_24
IO_L6N_24
IO_L7P_24
IO_L7N_24
IO_L8P_CC_24
IO_L8N_CC_24
(2)
IO_L9P_CC_24
Virtex-5 FPGA Packaging and Pinout Specification
2024年4月4日发(作者：裴思莹)
Chapter 1:Packaging Overview
Device/Package Combinations and Maximum I/Os
Table1-1 shows the maximum number of user I/Os possible in Virtex-5 FPGA flip-chip
packages. FF denotes flip-chip fine-pitch BGA (1.00 mm pitch).
Table 1-1:Flip-Chip Packages
Packages
FF324
1.00
19 x 19
220
FF665
1.00
27 x 27
360
FF676
1.00
27 x 27
440
FF1136FF1153
1.00
35 x 35
640
1.00
35 x 35
800
FF1156
1.00
35 x 35
360
FF1738
1.00
42.5 x
42.5
960
FF1759
1.00
42.5 x
42.5
680
FF1760
1.00
42.5 x
42.5
1200
Package
Specifications
FF323
Pitch(mm)
Size(mm)
Maximum
I/Os
1.00
19 x 19
172
The number of I/Os per package includes all user I/Os except the 19 pins listed in
Table1-2.
Table 1-2:Virtex-5 FPGA I/O Pinsin the Dedicated Configuration Bank (Bank0)
DXP
DXN
VBATT
PROGRAM_B
HSWAPEN
D_IN
DONE
CCLK_0
INIT_B_0
CS_B_0
RDWR_B_0
TCK_0
M0_0
M1_0
M2_0
TMS
TDI
D_OUT_BUSY
TDO_0
The RocketIO™ GTP transceiver I/O channels for the devices listed in Table1-3 or the GTX
transceiver I/O channels for the devices listed in Table1-4.
Table 1-3:
I/O
Channels
MGTRXP
MGTRXN
MGTTXP
MGTTXN
Notes:
XC5VLX30T has 4 GTP I/O channels in the FF323/FFG323 package and 8 GTP I/O channels in the FF665/FFG665 package.
XC5VLX50T has 8 GTP I/O channels in the FF665/FFG665 package and 12 GTP I/O channels in the FF1136/FFG1136 package.
XC5VSX50T has 8 GTP I/O channels in the FF665/FFG665 package and 12 GTP I/O channels in the FF1136/FFG1136 package.
Number of GTP Transceiver I/O Channels/Device
Device
LX20TLX30T
(1)
SX35TLX50T
(2)
SX50T
(3)
LX85TSX95TLX110TLX155TLX220TSX240TLX330T
4
4
4
4
4 or 8
4 or 8
4 or 8
4 or 8
8
8
8
8
8 or 12
8 or 12
8 or 12
8 or 12
8 or 12
8 or 12
8 or 12
8 or 12
12
12
12
12
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
24
24
24
24
24
24
24
24
Virtex-5 FPGA Packaging and Pinout Specification
Chapter 1:Packaging Overview
Virtex-5 FPGA Packaging and Pinout Specification
Pin Definitions
Virtex-5 FPGA Packaging and Pinout Specificatio
Chapter 1:Packaging Overview
Virtex-5 FPGA Packaging and Pinout Specification
Chapter 2:Pinout Tables
Table 2-8:FF1738 Package—FX100T, LX110T, FX130T, LX155T, FX200T, LX220T,
SX240T, and LX330T (Continued)
Bank
23
23
23
23
23
23
23
23
23
23
23
23
23
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
24
Pin DescriptionPin Number
J33
K32
J32
L32
L31
P33
P32
R33
R32
T32
U32
U31
T31
J12
H11
G12
G11
F12
F11
E10
F10
K14
K13
K12
J11
J13
H13
H10
J10
H14
H15
K10
No Connect (NC)
IO_L13N_23
IO_L14P_23
IO_L14N_VREF_23
IO_L15P_23
IO_L15N_23
IO_L16P_23
IO_L16N_23
IO_L17P_23
IO_L17N_23
IO_L18P_23
IO_L18N_23
IO_L19P_23
IO_L19N_23
IO_L0P_24
IO_L0N_24
IO_L1P_24
IO_L1N_24
IO_L2P_24
IO_L2N_24
IO_L3P_24
IO_L3N_24
IO_L4P_24
IO_L4N_VREF_24
IO_L5P_24
IO_L5N_24
IO_L6P_24
IO_L6N_24
IO_L7P_24
IO_L7N_24
IO_L8P_CC_24
IO_L8N_CC_24
(2)
IO_L9P_CC_24
Virtex-5 FPGA Packaging and Pinout Specification