2024年4月8日发(作者：全秀颖)
Feature Descriptions
Device Configuration
Zynq-7000 XC7Z020 SoC uses a multi-stage boot process that supports both a non-secure
and a secure boot. The PS is the master of the boot and configuration process. For a secure
boot, the PL must be powered on to enable the use of the security block located within the
PL, which provides 256-bit AES and SHA decryption/authentication.
The ZC702 board supports these configuration options:
•
•
•
•
PS Configuration: Quad SPI flash memory
PS Configuration: Processor System Boot from SD Card (J64)
PL Configuration: USB JTAG configuration port (Digilent module)
PL Configuration: Platform cable header J2 and flying lead header J58 JTAG
configuration ports
TIP:
Designs using serial configuration based on Quad-SPI flash memory can take advantage of
low-cost commodity SPI flash memory.
The JTAG configuration option is selected by setting SW16 as shown in Table1-2 and SW10
as described in Programmable Logic JTAG Programming Options for PL configuration
details. SW10 is callout 23 in Figure1-2.
Table 1-2:Switch SW16 Configuration Option Settings
Boot Mode
JTAG mode
(1)
Independent JTAG mode
Quad SPI mode
SD mode
MIO configuration pin
Notes:
t switch setting
SW16.1
0
1
0
0
MIO2
SW16.2
0
0
0
0
MIO3
SW16.3
0
0
0
1
MIO4
SW16.4
0
0
1
1
MIO5
SW16.5
0
0
0
0
MIO6
Note:
For more information about Zynq-7000 SoC configuration settings, see the Zynq-7000 SoC
Technical Reference Manual (UG585) [Ref2].
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019
Feature Descriptions
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019
Feature Descriptions
Table 1-4:DDR3 Component Memory Connections to the XC7Z020 SoC (Cont’d)
Component Memory
Net Name
PS_DDR3_CAS_B
PS_DDR3_RAS_B
PS_DDR3_RESET_B
PS_DDR3_CS_B
PS_DDR3_ODT
PS_VRN
PS_VRP
VTTVREF_PS
VTTVREF_PS
XC7Z020 (U1) Pin
P3
R5
F3
P6
P5
M7
N7
H7
P7
Pin Number
G3
F3
N2
H2
G1
Pin Name
CAS_B
RAS_B
RESET_B
CS_B
ODT
Reference
Designator
U66, U67, U68, U69
U66, U67, U68, U69
U66, U67, U68, U69
U66, U67, U68, U69
U66, U67, U68, U69
documented in the DDR3 Design Guidelines section of the 7SeriesFPGAs Memory Interface Solutions
v1.8 UserGuide (UG586) [Ref4]. The ZC702 DDR3 memory interface is a 40
Ω
impedance
implementation. Other memory interface details are available in UG586 and the 7SeriesFPGAs
Memory Resources UserGuide (UG473) [Ref5]. For more details, see the Micron MT41J256M8HX-15E
data sheet at the Micron website [Ref14].
Note:
The ZC702 DDR3 4x 8-bit component memory interface adheres to the constraints guidelines
Quad-SPI Flash Memory
[Figure1-2, callout 3]
The Quad-SPI flash memory located at U41 provides 128 Mb of non-volatile storage that
can be used for configuration and data storage.
•
•
•
•
Part number: N25Q128A11ESF40G (Micron)
Supply voltage: 1.8V
Datapath width: 4 bits
Data rate: Various depending on Single/Dual/Quad mode
The connections between the SPI flash memory and the XC7Z020 SoC are listed in
Table1-5.
Table 1-5:
Pin Name
PS_MIO6
PS_MIO5
PS_MIO4
Quad SPI Flash Memory Connections to the XC7Z020 SoC
XC7Z020 (U1)
Bank
500
500
500
Schematic
Quad-SPI Flash Memory (U41)
MIO Select
Header
Pin Number
Net Name
Pin NumberPin Name
A4
A3
E4
QSPI_CLK
QSPI_IO3
QSPI_IO2
16
1
9
C
DQ3_HOLD_B
WP_B
J26.2
J25.2
J22.2
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019
Feature Descriptions
Table 1-5:
Pin Name
PS_MIO3
PS_MIO2
PS_MIO1
Notes:
Quad SPI Flash Memory Connections to the XC7Z020 SoC (Cont’d)
XC7Z020 (U1)
Bank
500
500
500
Schematic
Quad-SPI Flash Memory (U41)
MIO Select
Header
Pin Number
Net Name
Pin NumberPin Name
F6
A2
A1
QSPI_IO1
QSPI_IO0
QSPI_CS_B
8
15
7
DQ1
DQ0
S_B
J20.2
J21.2
NA
Each three-pin MIO select header has pin 1 wired to VCCMIO and pin 3 wired to GND.
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019
Feature Descriptions
Table 1-7:USB Connector Pin Assignments and Signal Definitions Between J1 and U9
Net Name
USB_VBUS_SEL
USB_D_N
USB_D_P
GND
USB Connector
J1
Pin
1
2
3
5
Description
+5V from host system
Bidirectional differential serial data (N-side)
Bidirectional differential serial data (P-side)
Signal ground
Name
VBUS
D_N
D_P
GND
USB3320 (U9)
Pin
22
19
18
33
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019
2024年4月8日发(作者：全秀颖)
Feature Descriptions
Device Configuration
Zynq-7000 XC7Z020 SoC uses a multi-stage boot process that supports both a non-secure
and a secure boot. The PS is the master of the boot and configuration process. For a secure
boot, the PL must be powered on to enable the use of the security block located within the
PL, which provides 256-bit AES and SHA decryption/authentication.
The ZC702 board supports these configuration options:
•
•
•
•
PS Configuration: Quad SPI flash memory
PS Configuration: Processor System Boot from SD Card (J64)
PL Configuration: USB JTAG configuration port (Digilent module)
PL Configuration: Platform cable header J2 and flying lead header J58 JTAG
configuration ports
TIP:
Designs using serial configuration based on Quad-SPI flash memory can take advantage of
low-cost commodity SPI flash memory.
The JTAG configuration option is selected by setting SW16 as shown in Table1-2 and SW10
as described in Programmable Logic JTAG Programming Options for PL configuration
details. SW10 is callout 23 in Figure1-2.
Table 1-2:Switch SW16 Configuration Option Settings
Boot Mode
JTAG mode
(1)
Independent JTAG mode
Quad SPI mode
SD mode
MIO configuration pin
Notes:
t switch setting
SW16.1
0
1
0
0
MIO2
SW16.2
0
0
0
0
MIO3
SW16.3
0
0
0
1
MIO4
SW16.4
0
0
1
1
MIO5
SW16.5
0
0
0
0
MIO6
Note:
For more information about Zynq-7000 SoC configuration settings, see the Zynq-7000 SoC
Technical Reference Manual (UG585) [Ref2].
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019
Feature Descriptions
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019
Feature Descriptions
Table 1-4:DDR3 Component Memory Connections to the XC7Z020 SoC (Cont’d)
Component Memory
Net Name
PS_DDR3_CAS_B
PS_DDR3_RAS_B
PS_DDR3_RESET_B
PS_DDR3_CS_B
PS_DDR3_ODT
PS_VRN
PS_VRP
VTTVREF_PS
VTTVREF_PS
XC7Z020 (U1) Pin
P3
R5
F3
P6
P5
M7
N7
H7
P7
Pin Number
G3
F3
N2
H2
G1
Pin Name
CAS_B
RAS_B
RESET_B
CS_B
ODT
Reference
Designator
U66, U67, U68, U69
U66, U67, U68, U69
U66, U67, U68, U69
U66, U67, U68, U69
U66, U67, U68, U69
documented in the DDR3 Design Guidelines section of the 7SeriesFPGAs Memory Interface Solutions
v1.8 UserGuide (UG586) [Ref4]. The ZC702 DDR3 memory interface is a 40
Ω
impedance
implementation. Other memory interface details are available in UG586 and the 7SeriesFPGAs
Memory Resources UserGuide (UG473) [Ref5]. For more details, see the Micron MT41J256M8HX-15E
data sheet at the Micron website [Ref14].
Note:
The ZC702 DDR3 4x 8-bit component memory interface adheres to the constraints guidelines
Quad-SPI Flash Memory
[Figure1-2, callout 3]
The Quad-SPI flash memory located at U41 provides 128 Mb of non-volatile storage that
can be used for configuration and data storage.
•
•
•
•
Part number: N25Q128A11ESF40G (Micron)
Supply voltage: 1.8V
Datapath width: 4 bits
Data rate: Various depending on Single/Dual/Quad mode
The connections between the SPI flash memory and the XC7Z020 SoC are listed in
Table1-5.
Table 1-5:
Pin Name
PS_MIO6
PS_MIO5
PS_MIO4
Quad SPI Flash Memory Connections to the XC7Z020 SoC
XC7Z020 (U1)
Bank
500
500
500
Schematic
Quad-SPI Flash Memory (U41)
MIO Select
Header
Pin Number
Net Name
Pin NumberPin Name
A4
A3
E4
QSPI_CLK
QSPI_IO3
QSPI_IO2
16
1
9
C
DQ3_HOLD_B
WP_B
J26.2
J25.2
J22.2
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019
Feature Descriptions
Table 1-5:
Pin Name
PS_MIO3
PS_MIO2
PS_MIO1
Notes:
Quad SPI Flash Memory Connections to the XC7Z020 SoC (Cont’d)
XC7Z020 (U1)
Bank
500
500
500
Schematic
Quad-SPI Flash Memory (U41)
MIO Select
Header
Pin Number
Net Name
Pin NumberPin Name
F6
A2
A1
QSPI_IO1
QSPI_IO0
QSPI_CS_B
8
15
7
DQ1
DQ0
S_B
J20.2
J21.2
NA
Each three-pin MIO select header has pin 1 wired to VCCMIO and pin 3 wired to GND.
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019
Feature Descriptions
Table 1-7:USB Connector Pin Assignments and Signal Definitions Between J1 and U9
Net Name
USB_VBUS_SEL
USB_D_N
USB_D_P
GND
USB Connector
J1
Pin
1
2
3
5
Description
+5V from host system
Bidirectional differential serial data (N-side)
Bidirectional differential serial data (P-side)
Signal ground
Name
VBUS
D_N
D_P
GND
USB3320 (U9)
Pin
22
19
18
33
ZC702 Board User Guide
UG850 (v1.7) March 27, 2019