2024年4月21日发(作者：线兴发)
现货库存、技术资料、百科信息、热点资讯，精彩尽在鼎好!
K4S51163PF-Y(P)F
8M x 16Bit x 4 Banks Mobile-SDRAM
FEATURES
• 1.8V power supply.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
-. DS (Driver Strength)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (8K cycle).
• Commercial Temperature Operation (-25°C ~ 70°C).
• 1 /CS Support.
• 2Chips DDP 54Balls FBGA( -YXXX -Pb, -PXXX -Pb Free).
Mobile-SDRAM
GENERAL DESCRIPTION
The K4S51163PF is 536,870,912 bits synchronous high data
rate Dynamic RAM organized as 4 x 8,388,608 words by 16 bits,
fabricated with SAMSUNG’s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high bandwidth and high per-
formance memory system applications.
ORDERING INFORMATION
Part No.
K4S51163PF-Y(P)F75
K4S51163PF-Y(P)F90
K4S51163PF-Y(P)F1L
Max Freq.
133MHz(CL=3),83MHz(CL=2)
111MHz(CL=3),83MHz(CL=2)
111MHz(CL=3)*1,66MHz(CL=2)
LVCMOS
InterfacePackage
54 FBGA Pb
(Pb Free)
- F : Low Power, Commercial Temperature(-25°C ~ 70°C)
Notes :
1. In case of 40MHz Frequency, CL1 can be supported.
2. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.
Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific
purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
Address configuration
Organization
32M x16
Bank
BA0,BA1
Row
A0 - A12
Column Address
A0 - A9
1
September 2004
K4S51163PF-Y(P)F
FUNCTIONAL BLOCK DIAGRAM
Mobile-SDRAM
I/O Control
LWE
Data Input Register
Bank Select
LDQM
8M x 16
Sense AMP
8M x 16
8M x 16
8M x 16
Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
LRAS
CLKCKE
CLK
ADD
Column Decoder
Col. Buffer
LRASLCBR
Latency & Burst Length
LCKE
LCBRLWE
LCAS
Programming Register
LWCBR
LDQM
Timing Register
CSRASCASWEL(U)DQM
2
September 2004
2024年4月21日发(作者：线兴发)
现货库存、技术资料、百科信息、热点资讯，精彩尽在鼎好!
K4S51163PF-Y(P)F
8M x 16Bit x 4 Banks Mobile-SDRAM
FEATURES
• 1.8V power supply.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
-. DS (Driver Strength)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (8K cycle).
• Commercial Temperature Operation (-25°C ~ 70°C).
• 1 /CS Support.
• 2Chips DDP 54Balls FBGA( -YXXX -Pb, -PXXX -Pb Free).
Mobile-SDRAM
GENERAL DESCRIPTION
The K4S51163PF is 536,870,912 bits synchronous high data
rate Dynamic RAM organized as 4 x 8,388,608 words by 16 bits,
fabricated with SAMSUNG’s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high bandwidth and high per-
formance memory system applications.
ORDERING INFORMATION
Part No.
K4S51163PF-Y(P)F75
K4S51163PF-Y(P)F90
K4S51163PF-Y(P)F1L
Max Freq.
133MHz(CL=3),83MHz(CL=2)
111MHz(CL=3),83MHz(CL=2)
111MHz(CL=3)*1,66MHz(CL=2)
LVCMOS
InterfacePackage
54 FBGA Pb
(Pb Free)
- F : Low Power, Commercial Temperature(-25°C ~ 70°C)
Notes :
1. In case of 40MHz Frequency, CL1 can be supported.
2. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.
Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific
purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
Address configuration
Organization
32M x16
Bank
BA0,BA1
Row
A0 - A12
Column Address
A0 - A9
1
September 2004
K4S51163PF-Y(P)F
FUNCTIONAL BLOCK DIAGRAM
Mobile-SDRAM
I/O Control
LWE
Data Input Register
Bank Select
LDQM
8M x 16
Sense AMP
8M x 16
8M x 16
8M x 16
Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
LRAS
CLKCKE
CLK
ADD
Column Decoder
Col. Buffer
LRASLCBR
Latency & Burst Length
LCKE
LCBRLWE
LCAS
Programming Register
LWCBR
LDQM
Timing Register
CSRASCASWEL(U)DQM
2
September 2004