2024年4月26日发(作者:冒璞)
赛灵思半导体(深圳)有限公司
DS180 (v2.6) February 27, 2018Product Specification
General Description
7 series FPGAs comprise four FPGA families that address the complete range of system requirements, ranging from low cost, small form factor, cost-
sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding
high-performance applications. The 7 series FPGAs include:
•Spartan®-7 Family: Optimized for low cost, lowest power, and high
I/O performance. Available in low-cost, very small form-factor
packaging for smallest PCB footprint.
Artix®-7 Family: Optimized for low power applications requiring serial
transceivers and high DSP and logic throughput. Provides the lowest
total bill of materials cost for high-throughput, cost-sensitive
applications.
•Kintex®-7 Family: Optimized for best price-performance with a 2X
improvement compared to previous generation, enabling a new class
of FPGAs.
Virtex®-7 Family: Optimized for highest system performance and
capacity with a 2X improvement in system performance. Highest
capability devices enabled by stacked silicon interconnect (SSI)
technology.
•
•
Built on a state-of-the-art, high-performance, low-power (HPL), 28nm, high-k metal gate (HKMG) process technology, 7series FPGAs enable an
unparalleled increase in system performance with 2.9Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3TMAC/s DSP, while consuming 50% less
power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs.
Summary of 7Series FPGA Features
•
•
•
•
•
•
Advanced high-performance FPGA logic based on real 6-input look-
up table (LUT) technology configurable as distributed memory.
36Kb dual-port block RAM with built-in FIFO logic for on-chip data
buffering.
High-performance SelectIO™ technology with support for DDR3
interfaces up to 1,866 Mb/s.
High-speed serial connectivity with built-in multi-gigabit transceivers
from 600Mb/s to max. rates of 6.6Gb/s up to 28.05Gb/s, offering a
special low-power mode, optimized for chip-to-chip interfaces.
A user configurable analog interface (XADC), incorporating dual
12-bit 1MSPS analog-to-digital converters with on-chip thermal and
supply sensors.
DSP slices with 25x18 multiplier, 48-bit accumulator, and pre-adder
for high-performance filtering, including optimized symmetric
coefficient filtering.
•
•
•
•
•
Powerful clock management tiles (CMT), combining phase-locked
loop (PLL) and mixed-mode clock manager (MMCM) blocks for high
precision and low jitter.
Quickly deploy embedded processing with MicroBlaze™ processor.
Integrated block for PCIExpress® (PCIe), for up to x8 Gen3
Endpoint and Root Port designs.
Wide variety of configuration options, including support for
commodity memories, 256-bit AES encryption with HMAC/SHA-256
authentication, and built-in SEU detection and correction.
Low-cost, wire-bond, bare-die flip-chip, and high signal integrity flip-
chip packaging offering easy migration between family members in
the same package. All packages available in Pb-free and selected
packages in Pb option.
Designed for high performance and lowest power with 28nm,
HKMG, HPL process, 1.0V core voltage process technology and
0.9V core voltage option for even lower power.
•
Table 1:7Series Families Comparison
Max. Capability
Logic Cells
Block RAM
(1)
DSP Slices
DSP Performance
(2)
MicroBlaze CPU
(3)
Transceivers
Transceiver Speed
Serial Bandwidth
PCIe Interface
Memory Interface
I/O Pins
I/O Voltage
Package Options
Notes:
1.
2.
3.
Additional memory available in the form of distributed RAM.
Peak DSP performance numbers are based on symmetrical filter implementation.
Peak MicroBlaze CPU performance numbers based on microcontroller preset.
Spartan-7
102K
4.2Mb
160
176 GMAC/s
260 DMIPs
–
–
–
–
800Mb/s
400
1.2V–3.3V
Low-Cost, Wire-Bond
Artix-7
215K
13Mb
740
929GMAC/s
303 DMIPs
16
6.6Gb/s
211Gb/s
x4 Gen2
1,066Mb/s
500
1.2V–3.3V
Low-Cost, Wire-Bond,
Bare-Die Flip-Chip
Kintex-7
478K
34Mb
1,920
2,845GMAC/s
438 DMIPs
32
12.5Gb/s
800Gb/s
x8 Gen2
1,866Mb/s
500
1.2V–3.3V
Bare-Die Flip-Chip and High-
Performance Flip-Chip
Virtex-7
1,955K
68Mb
3,600
5,335GMAC/s
441 DMIPs
96
28.05Gb/s
2,784Gb/s
x8 Gen3
1,866Mb/s
1,200
1.2V–3.3V
Highest Performance
Flip-Chip
© Copyright 2010–2018 Xilinx, Inc., Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI Express is a trademark of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS180 (v2.6) February 27, 2018
Product Specification
7Series FPGAs Data Sheet: Overview
Spartan-7 FPGA Feature Summary
Table 2:Spartan-7 FPGA Feature Summary by Device
CLB
Device
Logic
Cells
6,000
12,800
23,360
52,160
76,800
102,400
Slices
(1)
938
2,000
3,650
8,150
12,000
16,000
Max
Distributed
RAM (Kb)
70
150
313
600
832
1,100
DSP
Slices
(2)
10
20
80
120
140
160
Block RAM Blocks
(3)
18Kb
10
20
90
150
180
240
36Kb
5
10
45
75
90
120
Max
(Kb)
180
360
1,620
2,700
3,240
4,320
CMTs
(4)
PCIeGT
XADC
Blocks
0
0
1
1
1
1
Total I/O
Banks
(5)
2
2
3
5
8
8
Max User
I/O
100
100
150
250
400
400
XC7S6
XC7S15
XC7S25
XC7S50
XC7S75
XC7S100
2
2
3
5
8
8
0
0
0
0
0
0
0
0
0
0
0
0
Notes:
1.
2.
3.
4.
5.
Each 7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.
Each DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an accumulator.
Block RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18Kb blocks.
Each CMT contains one MMCM and one PLL.
Does not include configuration Bank 0.
DS180 (v2.6) February 27, 2018
Product Specification
7Series FPGAs Data Sheet: Overview
Artix-7 FPGA Feature Summary
Table 4:Artix-7 FPGA Feature Summary by Device
Logic
Cells
Configurable Logic Blocks
(CLBs)
Slices
(1)
2,000
2,600
3,650
5,200
8,150
11,800
15,850
33,650
Max
Distributed
RAM (Kb)
171
200
313
400
600
892
1,188
2,888
Block RAM Blocks
(3)
DSP48E1
Slices
(2)
18Kb
40
50
90
100
150
210
270
730
36Kb
20
25
45
50
75
105
135
365
Max
(Kb)
720
900
1,620
1,800
2,700
3,780
4,860
13,140
CMTs
(4)
PCIe
(5)
GTPs
XADC
Blocks
Total I/O
Banks
(6)
Max User
I/O
(7)
Device
XC7A12T
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T
12,800
16,640
23,360
33,280
52,160
75,520
101,440
215,360
40
45
80
90
120
180
240
740
3
5
3
5
5
6
6
10
1
1
1
1
1
1
1
1
2
4
4
4
4
8
8
16
1
1
1
1
1
1
1
1
3
5
3
5
5
6
6
10
150
250
150
250
250
300
300
500
Notes:
7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.
DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an accumulator.
RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18Kb blocks.
CMT contains one MMCM and one PLL.
-7 FPGA Interface Blocks for PCI Express support up to x4 Gen 2.
not include configuration Bank 0.
number does not include GTP transceivers.
Table 5:Artix-7 FPGA Device-Package Combinations and Maximum I/Os
Package
(1)
Size (mm)
Ball Pitch
(mm)
Device
XC7A12T
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T
2
2
106
106
2106
2112
0
0
0
0
210
210
210
210
GTP
(4)
CPG236
10 x 10
0.5
I/O
HR
(5)
CPG238
10 x 10
0.5
GTP
(4)
CSG324
15 x 15
0.8
CSG325
15 x 15
0.8
FTG256
17 x 17
1.0
SBG484
19 x 19
0.8
FGG484
(2)
23 x 23
1.0
FBG484
(2)
23 x 23
1.0
FGG676
(3)
27 x 27
1.0
FBG676
(3)
27 x 27
1.0
FFG1156
35 x 35
1.0
I/O
HR
(5)
GTP
(4)
I/O
HR
(5)
GTP
(4)
I/O
HR
(5)
GTP
(4)
I/O
HR
(5)
GTP
I/O
HR
(5)
GTP
(4)
I/O
HR
(5)
GTP
I/O
HR
(5)
GTP
(4)
I/O
HR
(5)
GTP
I/O
HR
(5)
GTP
I/O
HR
(5)
2112
0210
2
4
4
4
4
150
150
150
150
150
0
0
0
0
170
170
170
170
4285
4
4
4
4
250
250
285
285
4285
8
8
300
300
840016500
01704250
Notes:
packages listed are Pb-free (SBG, FBG, FFG with exemption 15). Some packages are available in Pb option.
s in FGG484 and FBG484 are footprint compatible.
s in FGG676 and FBG676 are footprint compatible.
transceivers in CP, CS, FT, and FG packages support data rates up to 6.25Gb/s.
= High-range I/O with support for I/O voltage from 1.2V to 3.3V.
质量等级领域:宇航级IC、特军级IC、超军级IC、普军级IC、禁运IC、工
业级IC,军级二三极管,功率管等;
应用领域:航空航天、船舶、汽车电子、军用计算机、铁路、医疗电子、通
信网络、电力工业以及大型工业设备
祝您:工作顺利,生活愉快!
以赛灵思半导体(深圳)有限公司提供的参数为例,以下为XC7VX690T-2FFG1927I的详细参数,仅供
参考
DS180 (v2.6) February 27, 2018
Product Specification
7Series FPGAs Data Sheet: Overview
Table 11:Virtex-7 HT FPGA Device-Package Combinations and Maximum I/Os
Package
(1)
Size (mm)
Ball Pitch
Device
XC7VH580T
XC7VH870T
GTH
24
FLG1155
35 x 35
1.0
GTZ
8
I/O
HP
(2)
400
GTH
48
FLG1931
45 x 45
1.0
GTZ
8
I/O
HP
(2)
600
7216300
GTH
FLG1932
45 x 45
1.0
GTZ
I/O
HP
(2)
Notes:
packages listed are Pb-free with exemption 15. Some packages are available in Pb option.
= High-performance I/O with support for I/O voltage from 1.2V to 1.8V.
DS180 (v2.6) February 27, 2018
Product Specification
7Series FPGAs Data Sheet: Overview
The Spartan-7 FPGA ordering information is shown in Figure1. Refer to the Package Marking section of UG475, 7 Series
FPGAs Packaging and Pinout for a more detailed explanation of the device markings.
Example:
X C 7 S 50- 2FGGA484C
Device Type
Speed Grade
(-L1
(1)
, -1, -2)
Temperature Range
C: Commercial (Tj = 0°C to +85°C)
I: Industrial (Tj = –40°C to +100°C)
Q: Expanded (Tj = –40°C to +125°C)
Package Designator and Pin Count
(Footprint Identifier)
Pb-Free
Package Type
1) -L1 is the ordering code for the lower power, -1L speed grade.
DS180_01_012517
Figure 1:Spartan-7 FPGA Ordering Information
The Artix-7, Kintex-7, and Virtex-7 FPGA ordering information, shown in Figure2, applies to all packages including Pb-Free.
Refer to the Package Marking section of UG475
, 7 Series FPGAs Packaging and Pinout for a more detailed explanation of
the device markings.
Example:X C 7 K 3 2 5 T - 2 F B G 9 0 0 C
Device Type
Speed Grade
(-L1
(1)
, -L2
(2)
, -G2
(3)
, -1, -2, -3)
Temperature Range
C: Commercial (Tj = 0°C to +85°C)
E: Extended (Tj = 0°C to +100°C)
I: Industrial (Tj = –40°C to +100°C)
Number of Pins
(4)
Pb-Free
V: RoHS 6/6
G (CPG, CSG, FTG, FGG): RoHS 6/6
G (FFG, FBG, SBG, FLG, FHG): RoHS 6/6 with Exemption 15
Package Type
1) -L1 is the ordering code for the lower power, -1L speed grade.
2) -L2 is the ordering code for the lower power, -2L speed grade.
3) -G2 is the ordering code for the -2 speed grade devices with higher performance transceivers.
4) Some package names do not exactly match the number of pins present on that package.
See UG475: 7 Series FPGAs Packaging and Pinout User Guide for package details.
DS180_01_061317
Figure 2:Artix-7, Kintex-7, and Virtex-7 FPGA Ordering Information
DS180 (v2.6) February 27, 2018
Product Specification
2024年4月26日发(作者:冒璞)
赛灵思半导体(深圳)有限公司
DS180 (v2.6) February 27, 2018Product Specification
General Description
7 series FPGAs comprise four FPGA families that address the complete range of system requirements, ranging from low cost, small form factor, cost-
sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding
high-performance applications. The 7 series FPGAs include:
•Spartan®-7 Family: Optimized for low cost, lowest power, and high
I/O performance. Available in low-cost, very small form-factor
packaging for smallest PCB footprint.
Artix®-7 Family: Optimized for low power applications requiring serial
transceivers and high DSP and logic throughput. Provides the lowest
total bill of materials cost for high-throughput, cost-sensitive
applications.
•Kintex®-7 Family: Optimized for best price-performance with a 2X
improvement compared to previous generation, enabling a new class
of FPGAs.
Virtex®-7 Family: Optimized for highest system performance and
capacity with a 2X improvement in system performance. Highest
capability devices enabled by stacked silicon interconnect (SSI)
technology.
•
•
Built on a state-of-the-art, high-performance, low-power (HPL), 28nm, high-k metal gate (HKMG) process technology, 7series FPGAs enable an
unparalleled increase in system performance with 2.9Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3TMAC/s DSP, while consuming 50% less
power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs.
Summary of 7Series FPGA Features
•
•
•
•
•
•
Advanced high-performance FPGA logic based on real 6-input look-
up table (LUT) technology configurable as distributed memory.
36Kb dual-port block RAM with built-in FIFO logic for on-chip data
buffering.
High-performance SelectIO™ technology with support for DDR3
interfaces up to 1,866 Mb/s.
High-speed serial connectivity with built-in multi-gigabit transceivers
from 600Mb/s to max. rates of 6.6Gb/s up to 28.05Gb/s, offering a
special low-power mode, optimized for chip-to-chip interfaces.
A user configurable analog interface (XADC), incorporating dual
12-bit 1MSPS analog-to-digital converters with on-chip thermal and
supply sensors.
DSP slices with 25x18 multiplier, 48-bit accumulator, and pre-adder
for high-performance filtering, including optimized symmetric
coefficient filtering.
•
•
•
•
•
Powerful clock management tiles (CMT), combining phase-locked
loop (PLL) and mixed-mode clock manager (MMCM) blocks for high
precision and low jitter.
Quickly deploy embedded processing with MicroBlaze™ processor.
Integrated block for PCIExpress® (PCIe), for up to x8 Gen3
Endpoint and Root Port designs.
Wide variety of configuration options, including support for
commodity memories, 256-bit AES encryption with HMAC/SHA-256
authentication, and built-in SEU detection and correction.
Low-cost, wire-bond, bare-die flip-chip, and high signal integrity flip-
chip packaging offering easy migration between family members in
the same package. All packages available in Pb-free and selected
packages in Pb option.
Designed for high performance and lowest power with 28nm,
HKMG, HPL process, 1.0V core voltage process technology and
0.9V core voltage option for even lower power.
•
Table 1:7Series Families Comparison
Max. Capability
Logic Cells
Block RAM
(1)
DSP Slices
DSP Performance
(2)
MicroBlaze CPU
(3)
Transceivers
Transceiver Speed
Serial Bandwidth
PCIe Interface
Memory Interface
I/O Pins
I/O Voltage
Package Options
Notes:
1.
2.
3.
Additional memory available in the form of distributed RAM.
Peak DSP performance numbers are based on symmetrical filter implementation.
Peak MicroBlaze CPU performance numbers based on microcontroller preset.
Spartan-7
102K
4.2Mb
160
176 GMAC/s
260 DMIPs
–
–
–
–
800Mb/s
400
1.2V–3.3V
Low-Cost, Wire-Bond
Artix-7
215K
13Mb
740
929GMAC/s
303 DMIPs
16
6.6Gb/s
211Gb/s
x4 Gen2
1,066Mb/s
500
1.2V–3.3V
Low-Cost, Wire-Bond,
Bare-Die Flip-Chip
Kintex-7
478K
34Mb
1,920
2,845GMAC/s
438 DMIPs
32
12.5Gb/s
800Gb/s
x8 Gen2
1,866Mb/s
500
1.2V–3.3V
Bare-Die Flip-Chip and High-
Performance Flip-Chip
Virtex-7
1,955K
68Mb
3,600
5,335GMAC/s
441 DMIPs
96
28.05Gb/s
2,784Gb/s
x8 Gen3
1,866Mb/s
1,200
1.2V–3.3V
Highest Performance
Flip-Chip
© Copyright 2010–2018 Xilinx, Inc., Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx
in the United States and other countries. PCI Express is a trademark of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS180 (v2.6) February 27, 2018
Product Specification
7Series FPGAs Data Sheet: Overview
Spartan-7 FPGA Feature Summary
Table 2:Spartan-7 FPGA Feature Summary by Device
CLB
Device
Logic
Cells
6,000
12,800
23,360
52,160
76,800
102,400
Slices
(1)
938
2,000
3,650
8,150
12,000
16,000
Max
Distributed
RAM (Kb)
70
150
313
600
832
1,100
DSP
Slices
(2)
10
20
80
120
140
160
Block RAM Blocks
(3)
18Kb
10
20
90
150
180
240
36Kb
5
10
45
75
90
120
Max
(Kb)
180
360
1,620
2,700
3,240
4,320
CMTs
(4)
PCIeGT
XADC
Blocks
0
0
1
1
1
1
Total I/O
Banks
(5)
2
2
3
5
8
8
Max User
I/O
100
100
150
250
400
400
XC7S6
XC7S15
XC7S25
XC7S50
XC7S75
XC7S100
2
2
3
5
8
8
0
0
0
0
0
0
0
0
0
0
0
0
Notes:
1.
2.
3.
4.
5.
Each 7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.
Each DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an accumulator.
Block RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18Kb blocks.
Each CMT contains one MMCM and one PLL.
Does not include configuration Bank 0.
DS180 (v2.6) February 27, 2018
Product Specification
7Series FPGAs Data Sheet: Overview
Artix-7 FPGA Feature Summary
Table 4:Artix-7 FPGA Feature Summary by Device
Logic
Cells
Configurable Logic Blocks
(CLBs)
Slices
(1)
2,000
2,600
3,650
5,200
8,150
11,800
15,850
33,650
Max
Distributed
RAM (Kb)
171
200
313
400
600
892
1,188
2,888
Block RAM Blocks
(3)
DSP48E1
Slices
(2)
18Kb
40
50
90
100
150
210
270
730
36Kb
20
25
45
50
75
105
135
365
Max
(Kb)
720
900
1,620
1,800
2,700
3,780
4,860
13,140
CMTs
(4)
PCIe
(5)
GTPs
XADC
Blocks
Total I/O
Banks
(6)
Max User
I/O
(7)
Device
XC7A12T
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T
12,800
16,640
23,360
33,280
52,160
75,520
101,440
215,360
40
45
80
90
120
180
240
740
3
5
3
5
5
6
6
10
1
1
1
1
1
1
1
1
2
4
4
4
4
8
8
16
1
1
1
1
1
1
1
1
3
5
3
5
5
6
6
10
150
250
150
250
250
300
300
500
Notes:
7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.
DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an accumulator.
RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18Kb blocks.
CMT contains one MMCM and one PLL.
-7 FPGA Interface Blocks for PCI Express support up to x4 Gen 2.
not include configuration Bank 0.
number does not include GTP transceivers.
Table 5:Artix-7 FPGA Device-Package Combinations and Maximum I/Os
Package
(1)
Size (mm)
Ball Pitch
(mm)
Device
XC7A12T
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T
2
2
106
106
2106
2112
0
0
0
0
210
210
210
210
GTP
(4)
CPG236
10 x 10
0.5
I/O
HR
(5)
CPG238
10 x 10
0.5
GTP
(4)
CSG324
15 x 15
0.8
CSG325
15 x 15
0.8
FTG256
17 x 17
1.0
SBG484
19 x 19
0.8
FGG484
(2)
23 x 23
1.0
FBG484
(2)
23 x 23
1.0
FGG676
(3)
27 x 27
1.0
FBG676
(3)
27 x 27
1.0
FFG1156
35 x 35
1.0
I/O
HR
(5)
GTP
(4)
I/O
HR
(5)
GTP
(4)
I/O
HR
(5)
GTP
(4)
I/O
HR
(5)
GTP
I/O
HR
(5)
GTP
(4)
I/O
HR
(5)
GTP
I/O
HR
(5)
GTP
(4)
I/O
HR
(5)
GTP
I/O
HR
(5)
GTP
I/O
HR
(5)
2112
0210
2
4
4
4
4
150
150
150
150
150
0
0
0
0
170
170
170
170
4285
4
4
4
4
250
250
285
285
4285
8
8
300
300
840016500
01704250
Notes:
packages listed are Pb-free (SBG, FBG, FFG with exemption 15). Some packages are available in Pb option.
s in FGG484 and FBG484 are footprint compatible.
s in FGG676 and FBG676 are footprint compatible.
transceivers in CP, CS, FT, and FG packages support data rates up to 6.25Gb/s.
= High-range I/O with support for I/O voltage from 1.2V to 3.3V.
质量等级领域:宇航级IC、特军级IC、超军级IC、普军级IC、禁运IC、工
业级IC,军级二三极管,功率管等;
应用领域:航空航天、船舶、汽车电子、军用计算机、铁路、医疗电子、通
信网络、电力工业以及大型工业设备
祝您:工作顺利,生活愉快!
以赛灵思半导体(深圳)有限公司提供的参数为例,以下为XC7VX690T-2FFG1927I的详细参数,仅供
参考
DS180 (v2.6) February 27, 2018
Product Specification
7Series FPGAs Data Sheet: Overview
Table 11:Virtex-7 HT FPGA Device-Package Combinations and Maximum I/Os
Package
(1)
Size (mm)
Ball Pitch
Device
XC7VH580T
XC7VH870T
GTH
24
FLG1155
35 x 35
1.0
GTZ
8
I/O
HP
(2)
400
GTH
48
FLG1931
45 x 45
1.0
GTZ
8
I/O
HP
(2)
600
7216300
GTH
FLG1932
45 x 45
1.0
GTZ
I/O
HP
(2)
Notes:
packages listed are Pb-free with exemption 15. Some packages are available in Pb option.
= High-performance I/O with support for I/O voltage from 1.2V to 1.8V.
DS180 (v2.6) February 27, 2018
Product Specification
7Series FPGAs Data Sheet: Overview
The Spartan-7 FPGA ordering information is shown in Figure1. Refer to the Package Marking section of UG475, 7 Series
FPGAs Packaging and Pinout for a more detailed explanation of the device markings.
Example:
X C 7 S 50- 2FGGA484C
Device Type
Speed Grade
(-L1
(1)
, -1, -2)
Temperature Range
C: Commercial (Tj = 0°C to +85°C)
I: Industrial (Tj = –40°C to +100°C)
Q: Expanded (Tj = –40°C to +125°C)
Package Designator and Pin Count
(Footprint Identifier)
Pb-Free
Package Type
1) -L1 is the ordering code for the lower power, -1L speed grade.
DS180_01_012517
Figure 1:Spartan-7 FPGA Ordering Information
The Artix-7, Kintex-7, and Virtex-7 FPGA ordering information, shown in Figure2, applies to all packages including Pb-Free.
Refer to the Package Marking section of UG475
, 7 Series FPGAs Packaging and Pinout for a more detailed explanation of
the device markings.
Example:X C 7 K 3 2 5 T - 2 F B G 9 0 0 C
Device Type
Speed Grade
(-L1
(1)
, -L2
(2)
, -G2
(3)
, -1, -2, -3)
Temperature Range
C: Commercial (Tj = 0°C to +85°C)
E: Extended (Tj = 0°C to +100°C)
I: Industrial (Tj = –40°C to +100°C)
Number of Pins
(4)
Pb-Free
V: RoHS 6/6
G (CPG, CSG, FTG, FGG): RoHS 6/6
G (FFG, FBG, SBG, FLG, FHG): RoHS 6/6 with Exemption 15
Package Type
1) -L1 is the ordering code for the lower power, -1L speed grade.
2) -L2 is the ordering code for the lower power, -2L speed grade.
3) -G2 is the ordering code for the -2 speed grade devices with higher performance transceivers.
4) Some package names do not exactly match the number of pins present on that package.
See UG475: 7 Series FPGAs Packaging and Pinout User Guide for package details.
DS180_01_061317
Figure 2:Artix-7, Kintex-7, and Virtex-7 FPGA Ordering Information
DS180 (v2.6) February 27, 2018
Product Specification