2024年4月27日发(作者：淦冬菱)

Chip Bus Hierarchy

Note that a locked transfer by the core processor (for example, execution

of a

TESTSET

instruction) effectively disables arbitration for the addressed

memory bank or resource until the memory lock is deasserted. DMA con-

trollers cannot perform locked transfers. DMA access to L1 memory can

only be stalled by an access already in progress from another DMA

channel.

Memory DMA transfers can result in repeated accesses to the same mem-

ory location. Because the memory DMA controller has the potential of

simultaneously accessing on-chip and off-chip memory, considerable

throughput can be achieved. The throughput rate for an on-chip/off-chip

memory access is limited by the slower of the two accesses.

In the case where the transfer is from on-chip to on-chip memory or from

off-chip to off-chip memory, the burst accesses cannot occur

simultaneously. The transfer rate is then determined by adding each trans-

fer plus an additional cycle between each transfer.

Table2-6 shows many types of 32-bit memory DMA transfers (on

DMAC1). In the table, it is assumed that no other DMA activity is con-

flicting with ongoing operations. The numbers in the table are theoretical

values. These values may be higher when they are measured on actual

hardware due to a variety of reasons relating to the device that is con-

nected to the EBIU.

For non-DMA accesses (for example, a core access through the EAB), a

32-bit access to DDR SDRAM (of the form

R0=[P0];

where P0 points

to an address in DDR SDRAM) always more efficient than executing two

16-bit accesses (of the form

R0=W[P0++];

where P0 points to an address

in DDR SDRAM). In this example, a 32-bit DDR SDRAM read takes ten

SCLK cycles while two 16-bit reads take nine SCLK cycles each.

ADSP-BF54x Blackfin Processor Hardware Reference

2024年4月27日发(作者：淦冬菱)

Chip Bus Hierarchy

Note that a locked transfer by the core processor (for example, execution

of a

TESTSET

instruction) effectively disables arbitration for the addressed

memory bank or resource until the memory lock is deasserted. DMA con-

trollers cannot perform locked transfers. DMA access to L1 memory can

only be stalled by an access already in progress from another DMA

channel.

Memory DMA transfers can result in repeated accesses to the same mem-

ory location. Because the memory DMA controller has the potential of

simultaneously accessing on-chip and off-chip memory, considerable

throughput can be achieved. The throughput rate for an on-chip/off-chip

memory access is limited by the slower of the two accesses.

In the case where the transfer is from on-chip to on-chip memory or from

off-chip to off-chip memory, the burst accesses cannot occur

simultaneously. The transfer rate is then determined by adding each trans-

fer plus an additional cycle between each transfer.

Table2-6 shows many types of 32-bit memory DMA transfers (on

DMAC1). In the table, it is assumed that no other DMA activity is con-

flicting with ongoing operations. The numbers in the table are theoretical

values. These values may be higher when they are measured on actual

hardware due to a variety of reasons relating to the device that is con-

nected to the EBIU.

For non-DMA accesses (for example, a core access through the EAB), a

32-bit access to DDR SDRAM (of the form

R0=[P0];

where P0 points

to an address in DDR SDRAM) always more efficient than executing two

16-bit accesses (of the form

R0=W[P0++];

where P0 points to an address

in DDR SDRAM). In this example, a 32-bit DDR SDRAM read takes ten

SCLK cycles while two 16-bit reads take nine SCLK cycles each.

ADSP-BF54x Blackfin Processor Hardware Reference