2024年4月28日发(作者：许芷雪)
Revision History
The following table shows the revision history for this document.
Date
06/22/2018
03/14/2018
Version
1.8.1
1.8
Revision
Editorial updates only. No technical content updates.
In Chapter1: Revised RSVDGND description in Table1-5.
In Chapter2: Updated links in Table2-1.
In Chapter4: In response to XCN16004: Forged to Stamped Lid Conversion for
Monolithic FPGA Flip Chip Packages, added Figure4-13: FFG900 (XC7Z035,
XC7Z045, and XC7Z100) Flip-Chip BGA with Stamped Lid Package Specifications.
06/14/20171.7Added the XC7Z007S, XC7Z012S, and XC7Z014S devices where applicable.
In Chapter5: Updated the packages and Peak Package Reflow Body Temperature.
Other updates to the Support for Thermal Models, Applied Pressure from Heat Sink
to the Package via Thermal Interface Materials, and Conformal Coating sections.
In Chapter6: Updated Figure6-1 to add the bar code marking and the Pb-free
character. Added the Pb-free Character description as outlined in XCN16022:
Cross-ship of Lead-free Bump and Substrates in Lead-free (FFG/FBG/SBG) Packages
[Ref14]. Revised the Bar Code section of Table6-1 to include changes outlined in
XCN16014: Top Marking change for 7 Series, UltraScale, and UltraScale+ Products.
Updated the Legal Disclaimers on page123.
03/01/20161.6Updated to add RF1156 packages and RoHS compliant options (FFV packages)
where applicable.
In Table1-5, updated the PS_POR_B and SRCC descriptions.
Added the XC7Z035 in the FF/FFG/FFV900 package to Table1-6.
Updated many of the drawings in Chapter4. Replaced the FF/FFG/FFV1156 package
mechanical drawing in Figure4-15.
Completely revised Chapter5, Thermal Specifications with industry standard
guidelines for all sections. Updated the Thermal Interface Material section
previously in AppendixB, and added the Applied Pressure from Heat Sink to the
Package via Thermal Interface Materials.
In AppendixB: Moved the Reasons for Thermal Interface Material
section to
Chapter5. Removed the Package Loading Specifications section.
11/17/20141.5Added the XC7Z035 device throughout the specification. Added a discussion on
ULA materials on page7. Added Note on page28. Updated Figure 5-4: Thermal
Management Options for Flip-Chip BGA Packages. In Table5-2 and Figure5-7,
revised the peak temperature (body) values and the ramp-up rate and ramp-down
rate to 2°C/s. Updated the Peak Package Reflow Body Temperature values in
Table5-3 and added Note1. Updated Soldering Guidelines section. Added Post
Reflow/Cleaning/Washing and Conformal Coating sections. Updated References.
Zynq-7000SoC Packaging Guide
UG865 (v1.8.1) June 22, 2018
Date
06/11/2014
Version
1.4
Revision
Added the RF900 package for the XQ7Z045 to Table1-1, Table1-3, Table1-4,
Table2-1, Table3-1, Figure3-45, Figure3-46, Figure3-47, Figure3-48,
Figure4-18, and Table5-1.
Updated the XC7Z015 bank numbering (Figure1-2).
Added XA7Z030 to Table1-3, Table1-4, Table2-1, Table3-1, Figure1-4,
Figure3-25, Figure3-26, Figure3-27, Figure3-28, Figure4-6, Figure4-7, and
Table5-1.
Updated the PUDC_B and PS_MIO_VREF descriptions in Table1-5. Added the
GTP/GTX XY coordinates to Figure1-2, Figure1-4, Figure1-5, and Figure1-6.
In Chapter3, updated the memory groupings legend’s DCI pin descriptions.
Added the Heat Sink Removal Procedure and Package Pressure Handling Capacity
sections. For clarity, updated Figure5-7 and Table5-3 with specific device
information.
Added Chapter7, Packing and Shipping.
11/12/20131.3Added the CLG485, SBG485, and FFG1156 packages. Added the XC7Z015 and
XC7Z100 devices. Added the XA Zynq-7000SoC devices (XA7Z010 and XA7Z020).
Added the Zynq-7000QSoC devices (XQ7Z020, XQ7Z030, and XQ7Z045) and the
RF484 and RF676 packages. Updated the Notice of Disclaimer.
Clarified the maximum and available PS I/O pins as 128 in Table1-1 and Table1-4.
In Table1-5, updated the PUDC_B description.
Added Note
1 and updated the data in Table5-1. Updated the Pb-Free Reflow
Soldering in Chapter5 discussion. Updated the MSL for flip-chip packages in
Table5-3.
Removed the engineering sample notation from the top mark drawings in
Figure6-1.
Updated AppendixA, Recommended PCB Design Rules.
02/14/20131.2Updated VCCPLL in Table1-5 and added Note2.
Updated Figure3-8 and Figure3-16.
Revised Figure4-1, increased the A and A2 maximum dimensions. Updated
Figure4-11. Added Figure4-6, Figure4-7. Figure4-9, and Figure4-12.
In Table5-1, updated thermal resistance data for the XC7Z010 and XC7Z020
devices.
Updated AppendixB, Heat Sink Guidelines for Lidless Flip-Chip Packages.
09/24/20121.1Added the CLG225 throughout document.
Clarified RSVDVCC[3:1] and PS_MIO_VREF in Table1-5, page12. Added Note9 to
the DXN_0 description.
Chapter3: Updated the legends for the pinout diagrams.
Chapter4: Added mechanical drawings.
05/08/20121.0Initial Xilinx release.
Zynq-7000SoC Packaging Guide
UG865 (v1.8.1) June 22, 2018
2024年4月28日发(作者：许芷雪)
Revision History
The following table shows the revision history for this document.
Date
06/22/2018
03/14/2018
Version
1.8.1
1.8
Revision
Editorial updates only. No technical content updates.
In Chapter1: Revised RSVDGND description in Table1-5.
In Chapter2: Updated links in Table2-1.
In Chapter4: In response to XCN16004: Forged to Stamped Lid Conversion for
Monolithic FPGA Flip Chip Packages, added Figure4-13: FFG900 (XC7Z035,
XC7Z045, and XC7Z100) Flip-Chip BGA with Stamped Lid Package Specifications.
06/14/20171.7Added the XC7Z007S, XC7Z012S, and XC7Z014S devices where applicable.
In Chapter5: Updated the packages and Peak Package Reflow Body Temperature.
Other updates to the Support for Thermal Models, Applied Pressure from Heat Sink
to the Package via Thermal Interface Materials, and Conformal Coating sections.
In Chapter6: Updated Figure6-1 to add the bar code marking and the Pb-free
character. Added the Pb-free Character description as outlined in XCN16022:
Cross-ship of Lead-free Bump and Substrates in Lead-free (FFG/FBG/SBG) Packages
[Ref14]. Revised the Bar Code section of Table6-1 to include changes outlined in
XCN16014: Top Marking change for 7 Series, UltraScale, and UltraScale+ Products.
Updated the Legal Disclaimers on page123.
03/01/20161.6Updated to add RF1156 packages and RoHS compliant options (FFV packages)
where applicable.
In Table1-5, updated the PS_POR_B and SRCC descriptions.
Added the XC7Z035 in the FF/FFG/FFV900 package to Table1-6.
Updated many of the drawings in Chapter4. Replaced the FF/FFG/FFV1156 package
mechanical drawing in Figure4-15.
Completely revised Chapter5, Thermal Specifications with industry standard
guidelines for all sections. Updated the Thermal Interface Material section
previously in AppendixB, and added the Applied Pressure from Heat Sink to the
Package via Thermal Interface Materials.
In AppendixB: Moved the Reasons for Thermal Interface Material
section to
Chapter5. Removed the Package Loading Specifications section.
11/17/20141.5Added the XC7Z035 device throughout the specification. Added a discussion on
ULA materials on page7. Added Note on page28. Updated Figure 5-4: Thermal
Management Options for Flip-Chip BGA Packages. In Table5-2 and Figure5-7,
revised the peak temperature (body) values and the ramp-up rate and ramp-down
rate to 2°C/s. Updated the Peak Package Reflow Body Temperature values in
Table5-3 and added Note1. Updated Soldering Guidelines section. Added Post
Reflow/Cleaning/Washing and Conformal Coating sections. Updated References.
Zynq-7000SoC Packaging Guide
UG865 (v1.8.1) June 22, 2018
Date
06/11/2014
Version
1.4
Revision
Added the RF900 package for the XQ7Z045 to Table1-1, Table1-3, Table1-4,
Table2-1, Table3-1, Figure3-45, Figure3-46, Figure3-47, Figure3-48,
Figure4-18, and Table5-1.
Updated the XC7Z015 bank numbering (Figure1-2).
Added XA7Z030 to Table1-3, Table1-4, Table2-1, Table3-1, Figure1-4,
Figure3-25, Figure3-26, Figure3-27, Figure3-28, Figure4-6, Figure4-7, and
Table5-1.
Updated the PUDC_B and PS_MIO_VREF descriptions in Table1-5. Added the
GTP/GTX XY coordinates to Figure1-2, Figure1-4, Figure1-5, and Figure1-6.
In Chapter3, updated the memory groupings legend’s DCI pin descriptions.
Added the Heat Sink Removal Procedure and Package Pressure Handling Capacity
sections. For clarity, updated Figure5-7 and Table5-3 with specific device
information.
Added Chapter7, Packing and Shipping.
11/12/20131.3Added the CLG485, SBG485, and FFG1156 packages. Added the XC7Z015 and
XC7Z100 devices. Added the XA Zynq-7000SoC devices (XA7Z010 and XA7Z020).
Added the Zynq-7000QSoC devices (XQ7Z020, XQ7Z030, and XQ7Z045) and the
RF484 and RF676 packages. Updated the Notice of Disclaimer.
Clarified the maximum and available PS I/O pins as 128 in Table1-1 and Table1-4.
In Table1-5, updated the PUDC_B description.
Added Note
1 and updated the data in Table5-1. Updated the Pb-Free Reflow
Soldering in Chapter5 discussion. Updated the MSL for flip-chip packages in
Table5-3.
Removed the engineering sample notation from the top mark drawings in
Figure6-1.
Updated AppendixA, Recommended PCB Design Rules.
02/14/20131.2Updated VCCPLL in Table1-5 and added Note2.
Updated Figure3-8 and Figure3-16.
Revised Figure4-1, increased the A and A2 maximum dimensions. Updated
Figure4-11. Added Figure4-6, Figure4-7. Figure4-9, and Figure4-12.
In Table5-1, updated thermal resistance data for the XC7Z010 and XC7Z020
devices.
Updated AppendixB, Heat Sink Guidelines for Lidless Flip-Chip Packages.
09/24/20121.1Added the CLG225 throughout document.
Clarified RSVDVCC[3:1] and PS_MIO_VREF in Table1-5, page12. Added Note9 to
the DXN_0 description.
Chapter3: Updated the legends for the pinout diagrams.
Chapter4: Added mechanical drawings.
05/08/20121.0Initial Xilinx release.
Zynq-7000SoC Packaging Guide
UG865 (v1.8.1) June 22, 2018