2024年4月29日发(作者：班驰婷)
元器件交易网
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C371i
UltraLogic™ 32-Macrocell Flash CPLD
Features
•
•
•
•
•
•
•
32 macrocells in two logic blocks
32 I/O pins
Five dedicated inputs including two clock pins
In-System Reprogrammable (ISR™) Flash technology
—JTAG interface
Bus Hold capabilities on all I/Os and dedicated inputs
No hidden delays
High speed
—f
MAX
= 143 MHz
—t
PD
= 8.5 n3s
—t
S
= 5 ns
—t
CO
= 6 ns
Fully PCI-compliant
3.3V or 5.0V I/O operation
Available in 44-pin PLCC, and TQFP packages
Pin-compatible with the CY7C372i
designed to bring the ease of use and high performance of the
22V10, as well as PCI Local Bus Specification support, to
high-density CPLDs.
Like all of the UltraLogic™ F
LASH
370i devices, the CY7C371i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows, thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins. The ISR interface is enabled
using the programming voltage pin (ISR
EN
). Additionally,
because of the superior routability of the F
LASH
370i devices,
ISR often allows users to change existing logic designs while
simultaneously fixing pinout assignments.
The 32 macrocells in the CY7C371i are divided between two
logic blocks. Each logic block includes 16 macrocells, a
72x86 product term array, and an intelligent product term
allocator.
The logic blocks in the F
LASH
370i architecture are connected
with an extremely fast and predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings
flexibility, routability, speed, and a uniform delay to the inter-
connect.
Like all members of the F
LASH
370i family, the CY7C371i is rich
in I/O resources. Each macrocell in the device features an
associated I/O pin, resulting in 32 I/O pins on the CY7C371i.
In addition, there are three dedicated inputs and two
input/clock pins.
Clock
Inputs
•
•
•
•
Functional Description
The CY7C371i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
F
LASH
370i™ family of high-density, high-speed CPLDs. Like
all members of the F
LASH
370i family, the CY7C371i is
Logic Block Diagram
Inputs
3
INPUT
MACROCELLS
2
2
INPUT/CLOCK
MACROCELLS
2
LOGIC
BLOCK
B
16 I/Os
I/O
16
–I/O
31
16 I/Os
I/O
0
–I/O
15
LOGIC
BLOCK
A
36
16
PIM
36
16
16
16
Selection Guide
7C371i-1437C371i-1107C371i-837C371iL-837C371i-667C371iL-66
Maximum Propagation Delay
[1]
, t
PD
Minimum Set-up, t
S
Maximum Clock to Output
[1]
, t
CO
Unit
ns
ns
ns
mA
8.5
5
6
75
10
6
6.5
75
12
8
8
75
12
8
8
45
15
10
10
75
15
10
10
45Typical Supply Current, I
CC
Comm./Ind.
Note:
3.3V I/O mode timing adder, t
3.3IO
, must be added to this specification when V
CCIO
= 3.3V.
CypressSemiconductorCorporation
Document #: 38-03032 Rev. *A
•3901NorthFirstStreet•SanJose
,
CA 95134•408-943-2600
Revised April 19, 2004
元器件交易网
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C371i
Pin Configurations
Top
PLCC
View
I
O
43210
D
C
1098
OOOOO
N
3322
/////
/
O
/
O
/
O
/
O
IIIII
G
C
V
IIII
65432
1
4443424140
I/O
I/O
5
/SCLK7
39
27
/SDI
I/O
6
8
38
I/O
26
I/O
I/O
7
9
37
25
I
I/O
24
0
10
36
ISR
EN
11
35CLK
1
/I
4
GND
12
34
GND
CLK
33
I
3
0
/I
1
13
I/O
8
14
32
I
2
I/O
31
I/O
9
15
23
I/O
I/O
10
16
30
22
I/O
I/O
11
17
29
21
1819262728
2567
O
1
D
E
O
O
1
4
O
1
T
D
O
1
O
1
8
D
2
0
///
N
N
//
I
I
G
O
1
/
M
O
IIIII
S
O
/
C
/
I
C
9
/
S
3
V
O
1
/
O
1
I
/
I
Functional Description
Finally, the CY7C371i features a very simple timing model.
Unlike other high-density CPLD architectures, there are no
hidden speed delays such as fanout effects, interconnect
delays, or expander delays. Regardless of the number of
resources used or the type of application, the timing param-
eters on the CY7C371i remain the same.
Logic Block
The number of logic blocks distinguishes the members of the
F
LASH
370i family. The CY7C371i includes two logic blocks.
Each logic block is constructed of a product term array, a
product term allocator, and 16 macrocells.
Product Term Array
The product term array in the F
LASH
370i logic block includes
36 inputs from the PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from the PIM are
available in both positive and negative polarity, making the
overall array size 72 x 86. This large array in each logic block
allows for very complex functions to be implemented in a
single pass through the device.
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be
assigned to any of the logic block macrocells (this is called
product term steering). Furthermore, product terms can be
shared among multiple macrocells. This means that product
terms that are common to more than one output can be imple-
mented in a single product term. Product term steering and
product term sharing help to increase the effective density of
the F
LASH
370i CPLDs. Note that product term allocation is
handled by software and is invisible to the user.
I/O Macrocell
Each of the macrocells on the CY7C371i has a separate
associated I/O pin. The input to the macrocell is the sum of
Document #: 38-03032 Rev. *A
Top
TQFP
View
43210
D
I
O
N
C
3
1
3
0
2
9
2
8
/
O
/
O
/
O
/
O
/
O
II
G
C
V
/
O
/
O
/
O
/
O
III
IIII
4443424144
I/O
5
/SCLK
1
33
I/O
27
/SDI
I/O
6
2
32
I/O
26
I/O
7
3
31
I/O
25
I
0
4
30
I/O
24
ISR
EN
5
29
CLK
1
/I
4
GND
6
28
GND
CLK
0
/I
1
7
27
I
3
I/O
8
8
26
I
2
I/O
9
9
25
I/O
23
I/O
10
10
24
I/O
22
I/O
11
11
23
I/O
21
71819202122
25
T
0
O
1
D
E
O
1
N
D
1
67
I
N
O
1
O
1
8
D
O
O
2
/////
II
C
II
M
O
O
1
4
/
I
C
G
O
/
I
/
S
I
V
/
S
3
O
1
9
/
I
O
1
/
I
between 0 and 16 product terms from the product term
allocator. The macrocell includes a register that can be
optionally bypassed. It also has polarity control, and two global
clocks to trigger the register. The macrocell also features a
separate feedback path to the PIM so that the register can be
buried if the I/O pin is used as an input.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
two logic blocks on the CY7C371i to the inputs and to each
other. All inputs (including feedbacks) travel through the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Programming
For an overview of ISR programming, refer to the F
LASH
370i
Family data sheet and for ISR cable and software specifica-
tions, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, “An
Introduction to In System Reprogramming with F
LASH
370i.”
PCI Compliance
The F
LASH
370i family of CMOS CPLDs are fully compliant with
the PCI Local Bus Specification published by the PCI Special
Interest Group. The simple and predictable timing model of
F
LASH
370i ensures compliance with the PCI AC specifications
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term distri-
bution.
3.3V or 5.0V I/O Operation
The F
LASH
370i family can be configured to operate in both
3.3V and 5.0V systems. All devices have two sets of V
CC
pins:
one set, V
CCINT
, for internal operation and input buffers, and
another set, V
CCIO
, for I/O output drivers. V
CCINT
pins must
always be connected to a 5.0V power supply. However, the
V
CCIO
pins may be connected to either a 3.3V or 5.0V power
supply, depending on the output requirements. When V
CCIO
pins are connected to a 5.0V source, the I/O voltage levels are
Page 2 of 12
2024年4月29日发(作者：班驰婷)
元器件交易网
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C371i
UltraLogic™ 32-Macrocell Flash CPLD
Features
•
•
•
•
•
•
•
32 macrocells in two logic blocks
32 I/O pins
Five dedicated inputs including two clock pins
In-System Reprogrammable (ISR™) Flash technology
—JTAG interface
Bus Hold capabilities on all I/Os and dedicated inputs
No hidden delays
High speed
—f
MAX
= 143 MHz
—t
PD
= 8.5 n3s
—t
S
= 5 ns
—t
CO
= 6 ns
Fully PCI-compliant
3.3V or 5.0V I/O operation
Available in 44-pin PLCC, and TQFP packages
Pin-compatible with the CY7C372i
designed to bring the ease of use and high performance of the
22V10, as well as PCI Local Bus Specification support, to
high-density CPLDs.
Like all of the UltraLogic™ F
LASH
370i devices, the CY7C371i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows, thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pins. The ISR interface is enabled
using the programming voltage pin (ISR
EN
). Additionally,
because of the superior routability of the F
LASH
370i devices,
ISR often allows users to change existing logic designs while
simultaneously fixing pinout assignments.
The 32 macrocells in the CY7C371i are divided between two
logic blocks. Each logic block includes 16 macrocells, a
72x86 product term array, and an intelligent product term
allocator.
The logic blocks in the F
LASH
370i architecture are connected
with an extremely fast and predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings
flexibility, routability, speed, and a uniform delay to the inter-
connect.
Like all members of the F
LASH
370i family, the CY7C371i is rich
in I/O resources. Each macrocell in the device features an
associated I/O pin, resulting in 32 I/O pins on the CY7C371i.
In addition, there are three dedicated inputs and two
input/clock pins.
Clock
Inputs
•
•
•
•
Functional Description
The CY7C371i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
F
LASH
370i™ family of high-density, high-speed CPLDs. Like
all members of the F
LASH
370i family, the CY7C371i is
Logic Block Diagram
Inputs
3
INPUT
MACROCELLS
2
2
INPUT/CLOCK
MACROCELLS
2
LOGIC
BLOCK
B
16 I/Os
I/O
16
–I/O
31
16 I/Os
I/O
0
–I/O
15
LOGIC
BLOCK
A
36
16
PIM
36
16
16
16
Selection Guide
7C371i-1437C371i-1107C371i-837C371iL-837C371i-667C371iL-66
Maximum Propagation Delay
[1]
, t
PD
Minimum Set-up, t
S
Maximum Clock to Output
[1]
, t
CO
Unit
ns
ns
ns
mA
8.5
5
6
75
10
6
6.5
75
12
8
8
75
12
8
8
45
15
10
10
75
15
10
10
45Typical Supply Current, I
CC
Comm./Ind.
Note:
3.3V I/O mode timing adder, t
3.3IO
, must be added to this specification when V
CCIO
= 3.3V.
CypressSemiconductorCorporation
Document #: 38-03032 Rev. *A
•3901NorthFirstStreet•SanJose
,
CA 95134•408-943-2600
Revised April 19, 2004
元器件交易网
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C371i
Pin Configurations
Top
PLCC
View
I
O
43210
D
C
1098
OOOOO
N
3322
/////
/
O
/
O
/
O
/
O
IIIII
G
C
V
IIII
65432
1
4443424140
I/O
I/O
5
/SCLK7
39
27
/SDI
I/O
6
8
38
I/O
26
I/O
I/O
7
9
37
25
I
I/O
24
0
10
36
ISR
EN
11
35CLK
1
/I
4
GND
12
34
GND
CLK
33
I
3
0
/I
1
13
I/O
8
14
32
I
2
I/O
31
I/O
9
15
23
I/O
I/O
10
16
30
22
I/O
I/O
11
17
29
21
1819262728
2567
O
1
D
E
O
O
1
4
O
1
T
D
O
1
O
1
8
D
2
0
///
N
N
//
I
I
G
O
1
/
M
O
IIIII
S
O
/
C
/
I
C
9
/
S
3
V
O
1
/
O
1
I
/
I
Functional Description
Finally, the CY7C371i features a very simple timing model.
Unlike other high-density CPLD architectures, there are no
hidden speed delays such as fanout effects, interconnect
delays, or expander delays. Regardless of the number of
resources used or the type of application, the timing param-
eters on the CY7C371i remain the same.
Logic Block
The number of logic blocks distinguishes the members of the
F
LASH
370i family. The CY7C371i includes two logic blocks.
Each logic block is constructed of a product term array, a
product term allocator, and 16 macrocells.
Product Term Array
The product term array in the F
LASH
370i logic block includes
36 inputs from the PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from the PIM are
available in both positive and negative polarity, making the
overall array size 72 x 86. This large array in each logic block
allows for very complex functions to be implemented in a
single pass through the device.
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be
assigned to any of the logic block macrocells (this is called
product term steering). Furthermore, product terms can be
shared among multiple macrocells. This means that product
terms that are common to more than one output can be imple-
mented in a single product term. Product term steering and
product term sharing help to increase the effective density of
the F
LASH
370i CPLDs. Note that product term allocation is
handled by software and is invisible to the user.
I/O Macrocell
Each of the macrocells on the CY7C371i has a separate
associated I/O pin. The input to the macrocell is the sum of
Document #: 38-03032 Rev. *A
Top
TQFP
View
43210
D
I
O
N
C
3
1
3
0
2
9
2
8
/
O
/
O
/
O
/
O
/
O
II
G
C
V
/
O
/
O
/
O
/
O
III
IIII
4443424144
I/O
5
/SCLK
1
33
I/O
27
/SDI
I/O
6
2
32
I/O
26
I/O
7
3
31
I/O
25
I
0
4
30
I/O
24
ISR
EN
5
29
CLK
1
/I
4
GND
6
28
GND
CLK
0
/I
1
7
27
I
3
I/O
8
8
26
I
2
I/O
9
9
25
I/O
23
I/O
10
10
24
I/O
22
I/O
11
11
23
I/O
21
71819202122
25
T
0
O
1
D
E
O
1
N
D
1
67
I
N
O
1
O
1
8
D
O
O
2
/////
II
C
II
M
O
O
1
4
/
I
C
G
O
/
I
/
S
I
V
/
S
3
O
1
9
/
I
O
1
/
I
between 0 and 16 product terms from the product term
allocator. The macrocell includes a register that can be
optionally bypassed. It also has polarity control, and two global
clocks to trigger the register. The macrocell also features a
separate feedback path to the PIM so that the register can be
buried if the I/O pin is used as an input.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
two logic blocks on the CY7C371i to the inputs and to each
other. All inputs (including feedbacks) travel through the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Programming
For an overview of ISR programming, refer to the F
LASH
370i
Family data sheet and for ISR cable and software specifica-
tions, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, “An
Introduction to In System Reprogramming with F
LASH
370i.”
PCI Compliance
The F
LASH
370i family of CMOS CPLDs are fully compliant with
the PCI Local Bus Specification published by the PCI Special
Interest Group. The simple and predictable timing model of
F
LASH
370i ensures compliance with the PCI AC specifications
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term distri-
bution.
3.3V or 5.0V I/O Operation
The F
LASH
370i family can be configured to operate in both
3.3V and 5.0V systems. All devices have two sets of V
CC
pins:
one set, V
CCINT
, for internal operation and input buffers, and
another set, V
CCIO
, for I/O output drivers. V
CCINT
pins must
always be connected to a 5.0V power supply. However, the
V
CCIO
pins may be connected to either a 3.3V or 5.0V power
supply, depending on the output requirements. When V
CCIO
pins are connected to a 5.0V source, the I/O voltage levels are
Page 2 of 12