2024年5月6日发(作者：竺民)
ISA 是 Industry Standard Architecture 的缩写
接口卡的外观
插槽的外观
I/O channel check; active low=parity error
A2 D7
A3 D6
A4 D5
A5 D4
A6 D3
A7 D2
A8 D1
A9 D0
A10 I/O CH RDY
A11 AEN
Address bit 19
A13 A18
Address bit 17
A15 A16 Address bit 16
Data bit 7
Data bit 6
Data bit 5
Data bit 4
Data bit 3
Data bit 2
Data bit 1
Data bit 0
I/O Channel ready, pulled low to lengthen memory cycles
1
A16 A15
Address bit 14
A18 A13
Address bit 10
A22 A9
Address bit 8
A24 A7
A25 A6
A26 A5
Address bit 4
A28 A3
Address bit 2
A30 A1
A31 A0
Address bit 1
Address bit 7
Address bit 6
Active high to reset or initialize system logic
B3 +5V
B4 IRQ2
B5 -5VDC
B6 DRQ2
+5 VDC
Interrupt Request 2
-5 VDC
No WaitState
B9 +12VDC
B10 GND
B11 /SMEMW
System Memory Read
B13 /IOW
+12 VDC
Ground
DMA Request 3
B17 /DACK1
DMA Request 1
B19 /REFRESH
B20 CLOCK
Refresh
System Clock (67 ns, 8-8.33 MHz, 50% duty cycle)
2
B21 IRQ7
Interrupt Request 6
B23 IRQ5
DMA Acknowledge 2
B27 T/C
Address Latch Enable
B29 +5V
B30 OSC
B31 GND
+5 VDC
High-speed Clock (70 ns, 14.31818 MHz, 50% duty cycle)
Ground
System bus high enable (data available on SD8-15)
Address bit 23
Address bit 22
Address bit 21
Address bit 20
Address bit 19
Address bit 18
Address bit 17
Memory Read (Active on all memory read cycles)
Memory Write (Active on all memory write cycles)
Data bit 8
Data bit 9
Data bit 10
Data bit 11
Data bit 12
Data bit 13
Data bit 14
Data bit 15
Memory 16-bit chip select (1 wait, 16-bit memory cycle)
C1 SBHE
C2 LA23
C3 LA22
C4 LA21
C5 LA20
C6 LA18
C7 LA17
C8 LA16
C9 /MEMR
C10 /MEMW
C11 SD08
C12 SD09
C13 SD10
C14 SD11
C15 SD12
C16 SD13
C17 SD14
C18 SD15
D1 /MEMCS16
D2 /IOCS16
Interrupt Request 10
D4 IRQ11
3
D7 IRQ14
DMA Acknowledge 0
D9 DRQ0
DMA Acknowledge 6
D13 DRQ6
DMA Acknowledge 7
D15 DRQ7
D16 +5 V
D17 /MASTER
DMA Request 7
4
2024年5月6日发(作者：竺民)
ISA 是 Industry Standard Architecture 的缩写
接口卡的外观
插槽的外观
I/O channel check; active low=parity error
A2 D7
A3 D6
A4 D5
A5 D4
A6 D3
A7 D2
A8 D1
A9 D0
A10 I/O CH RDY
A11 AEN
Address bit 19
A13 A18
Address bit 17
A15 A16 Address bit 16
Data bit 7
Data bit 6
Data bit 5
Data bit 4
Data bit 3
Data bit 2
Data bit 1
Data bit 0
I/O Channel ready, pulled low to lengthen memory cycles
1
A16 A15
Address bit 14
A18 A13
Address bit 10
A22 A9
Address bit 8
A24 A7
A25 A6
A26 A5
Address bit 4
A28 A3
Address bit 2
A30 A1
A31 A0
Address bit 1
Address bit 7
Address bit 6
Active high to reset or initialize system logic
B3 +5V
B4 IRQ2
B5 -5VDC
B6 DRQ2
+5 VDC
Interrupt Request 2
-5 VDC
No WaitState
B9 +12VDC
B10 GND
B11 /SMEMW
System Memory Read
B13 /IOW
+12 VDC
Ground
DMA Request 3
B17 /DACK1
DMA Request 1
B19 /REFRESH
B20 CLOCK
Refresh
System Clock (67 ns, 8-8.33 MHz, 50% duty cycle)
2
B21 IRQ7
Interrupt Request 6
B23 IRQ5
DMA Acknowledge 2
B27 T/C
Address Latch Enable
B29 +5V
B30 OSC
B31 GND
+5 VDC
High-speed Clock (70 ns, 14.31818 MHz, 50% duty cycle)
Ground
System bus high enable (data available on SD8-15)
Address bit 23
Address bit 22
Address bit 21
Address bit 20
Address bit 19
Address bit 18
Address bit 17
Memory Read (Active on all memory read cycles)
Memory Write (Active on all memory write cycles)
Data bit 8
Data bit 9
Data bit 10
Data bit 11
Data bit 12
Data bit 13
Data bit 14
Data bit 15
Memory 16-bit chip select (1 wait, 16-bit memory cycle)
C1 SBHE
C2 LA23
C3 LA22
C4 LA21
C5 LA20
C6 LA18
C7 LA17
C8 LA16
C9 /MEMR
C10 /MEMW
C11 SD08
C12 SD09
C13 SD10
C14 SD11
C15 SD12
C16 SD13
C17 SD14
C18 SD15
D1 /MEMCS16
D2 /IOCS16
Interrupt Request 10
D4 IRQ11
3
D7 IRQ14
DMA Acknowledge 0
D9 DRQ0
DMA Acknowledge 6
D13 DRQ6
DMA Acknowledge 7
D15 DRQ7
D16 +5 V
D17 /MASTER
DMA Request 7
4