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无线配置手册(CT5508+AP1142N)

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2024年5月15日发(作者:玄和悦)

无线基本配置手册(CT5508+AP1142N)

1、初始化控制器

初始化准备:控制器的console口与电脑的串口连接好,打开超级终端(默认),给控制器通电,按住电脑的《esc》键进入配置向

导,配置实例为CISCO WLC4402的配置,CT5508配置同WLC4402;

System will now restart!

Bootloader 4.0.217.0 (Apr 12 2007 - 17:46:14)

Motorola PowerPC ProcessorID=00000000 Rev. PVR=80200020

CPU: 833 MHz

CCB: 333 MHz

DDR: 166 MHz

LBC: 41 MHz

L1 D-cache 32KB, L1 I-cache 32KB enabled.

I2C: ready

DTT: 1 is 33 C

DRAM: DDR module detected, total size:512MB.

512 MB

8540 in PCI Host Mode.

8540 is the PCI Arbiter.

Memory Test PASS

FLASH:

Flash Bank 0: portsize = 2, size = 8 MB in 142 Sectors

8 MB

L2 cache enabled: 256KB

Card Id: 1540

Card Revision Id: 1

Card CPU Id: 1287

Number of MAC Addresses: 32

Number of Slots Supported: 4

Serial Number: FOC1127F04H

Unknown command Id: 0xa5

Unknown command Id: 0xa4

Unknown command Id: 0xa3

Manufacturers ID: 30464

Board Maintenance Level: 00

Number of supported APs: 50

In: serial

Out: serial

Err: serial

.o88b. d888888b .d8888. .o88b. .d88b.

d8P Y8 `88' 88' YP d8P Y8 .8P Y8.

8P 88 `8bo. 8P 88 88

8b 88 `Y8b. 8b 88 88

Y8b d8 .88. db 8D Y8b d8 `8b d8'

`Y88P' Y888888P `8888Y' `Y88P' `Y88P'

Model AIR-WLC4402-50-K9 S/N: FOC1127F04H

Net:

PHY DEVICE : Found Intel LXT971A PHY at 0x01

FEC ETHERNET

IDE: Bus 0: OK

Device 0: Model: STI Flash 7.4.0 Firm: 01.25.06 Ser#: STI

J11B4

Type: Removable Hard Disk

Capacity: 245.0 MB = 0.2 GB (501760 x 512)

Device 1: not available

Booting

Press now for additional

***** External Console Active *****

Boot Options

Please choose an option from below:

1. Run primary image (version 4.1.185.0) (active)

2. Run backup image (version 4.0.217.0)

3. Manually update images

4. Change active boot image

5. Clear Configuration

Please enter your choice: 5 清除原有的配置

Detecting Hardware . . .

Re-building configuration filesystem

Done.

Bootloader 4.0.217.0 (Apr 12 2007 - 17:46:14)

Motorola PowerPC ProcessorID=00000000 Rev. PVR=80200020

CPU: 833 MHz

CCB: 333 MHz

DDR: 166 MHz

LBC: 41 MHz

L1 D-cache 32KB, L1 I-cache 32KB enabled.

I2C: ready

2024年5月15日发(作者:玄和悦)

无线基本配置手册(CT5508+AP1142N)

1、初始化控制器

初始化准备:控制器的console口与电脑的串口连接好,打开超级终端(默认),给控制器通电,按住电脑的《esc》键进入配置向

导,配置实例为CISCO WLC4402的配置,CT5508配置同WLC4402;

System will now restart!

Bootloader 4.0.217.0 (Apr 12 2007 - 17:46:14)

Motorola PowerPC ProcessorID=00000000 Rev. PVR=80200020

CPU: 833 MHz

CCB: 333 MHz

DDR: 166 MHz

LBC: 41 MHz

L1 D-cache 32KB, L1 I-cache 32KB enabled.

I2C: ready

DTT: 1 is 33 C

DRAM: DDR module detected, total size:512MB.

512 MB

8540 in PCI Host Mode.

8540 is the PCI Arbiter.

Memory Test PASS

FLASH:

Flash Bank 0: portsize = 2, size = 8 MB in 142 Sectors

8 MB

L2 cache enabled: 256KB

Card Id: 1540

Card Revision Id: 1

Card CPU Id: 1287

Number of MAC Addresses: 32

Number of Slots Supported: 4

Serial Number: FOC1127F04H

Unknown command Id: 0xa5

Unknown command Id: 0xa4

Unknown command Id: 0xa3

Manufacturers ID: 30464

Board Maintenance Level: 00

Number of supported APs: 50

In: serial

Out: serial

Err: serial

.o88b. d888888b .d8888. .o88b. .d88b.

d8P Y8 `88' 88' YP d8P Y8 .8P Y8.

8P 88 `8bo. 8P 88 88

8b 88 `Y8b. 8b 88 88

Y8b d8 .88. db 8D Y8b d8 `8b d8'

`Y88P' Y888888P `8888Y' `Y88P' `Y88P'

Model AIR-WLC4402-50-K9 S/N: FOC1127F04H

Net:

PHY DEVICE : Found Intel LXT971A PHY at 0x01

FEC ETHERNET

IDE: Bus 0: OK

Device 0: Model: STI Flash 7.4.0 Firm: 01.25.06 Ser#: STI

J11B4

Type: Removable Hard Disk

Capacity: 245.0 MB = 0.2 GB (501760 x 512)

Device 1: not available

Booting

Press now for additional

***** External Console Active *****

Boot Options

Please choose an option from below:

1. Run primary image (version 4.1.185.0) (active)

2. Run backup image (version 4.0.217.0)

3. Manually update images

4. Change active boot image

5. Clear Configuration

Please enter your choice: 5 清除原有的配置

Detecting Hardware . . .

Re-building configuration filesystem

Done.

Bootloader 4.0.217.0 (Apr 12 2007 - 17:46:14)

Motorola PowerPC ProcessorID=00000000 Rev. PVR=80200020

CPU: 833 MHz

CCB: 333 MHz

DDR: 166 MHz

LBC: 41 MHz

L1 D-cache 32KB, L1 I-cache 32KB enabled.

I2C: ready

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