2024年5月20日发(作者：阚迎南)

Memory

In this example, at the end of 15 core cycles, 32 bytes of instructions or

data have been brought into cache and are available to the sequencer. If all

the instructions contain 16 bits, sixteen instructions are brought into

cache at the end of 15 cycles. In addition, the first instruction that is part

of the cache line fill executes on the tenth cycle; the second instruction

executes on the eleventh cycle, and the third instruction executes on the

twelfth cycle—all of them in parallel with the cache line fill.

Each cache line fill is aligned on a 32-byte boundary. When the requested

instruction or data is not 32-byte aligned, the requested item is always

loaded in the first read; each read is forwarded to the core as the line is

filled. Sequential memory accesses miss the cache only when they reach

the end of a cache line.

When on-chip L2 is configured as non-cacheable, instruction fetches and

data fetches occur in 64-bit fills. In this case, each fill takes seven core

cycles to complete. As shown in Figure3-17 on page3-50, on-chip L2 is

configured as non-cacheable. To illustrate the concept of L2 latency with

cache off, simple instructions are used that do not require additional

external data fetches. In this case, consecutive instructions are issued on

consecutive cycles if multiple instructions are brought into the core in a

given fetch.

One Time Programmable Memory

The ADSP-BF54x processor processor also includes an on-chip OTP

memory array which provides 64K bits of non-volatile memory that can

be programmed by the customer only one time. It includes the array and

logic to support read access and programming. A mechanism for error cor-

rection is provided. Additionally, its pages can be write protected. The

OTP is not part of the Blackfin processor linear memory map. OTP mem-

ory is not accessed directly using the Blackfin processor memory map,

rather, it is accessed through four 32-bit wide registers (

OTP_DATA0-3

)

which act as the OTP memory read/write buffer.

ADSP-BF54x Blackfin Processor Hardware Reference

2024年5月20日发(作者：阚迎南)

Memory

In this example, at the end of 15 core cycles, 32 bytes of instructions or

data have been brought into cache and are available to the sequencer. If all

the instructions contain 16 bits, sixteen instructions are brought into

cache at the end of 15 cycles. In addition, the first instruction that is part

of the cache line fill executes on the tenth cycle; the second instruction

executes on the eleventh cycle, and the third instruction executes on the

twelfth cycle—all of them in parallel with the cache line fill.

Each cache line fill is aligned on a 32-byte boundary. When the requested

instruction or data is not 32-byte aligned, the requested item is always

loaded in the first read; each read is forwarded to the core as the line is

filled. Sequential memory accesses miss the cache only when they reach

the end of a cache line.

When on-chip L2 is configured as non-cacheable, instruction fetches and

data fetches occur in 64-bit fills. In this case, each fill takes seven core

cycles to complete. As shown in Figure3-17 on page3-50, on-chip L2 is

configured as non-cacheable. To illustrate the concept of L2 latency with

cache off, simple instructions are used that do not require additional

external data fetches. In this case, consecutive instructions are issued on

consecutive cycles if multiple instructions are brought into the core in a

given fetch.

One Time Programmable Memory

The ADSP-BF54x processor processor also includes an on-chip OTP

memory array which provides 64K bits of non-volatile memory that can

be programmed by the customer only one time. It includes the array and

logic to support read access and programming. A mechanism for error cor-

rection is provided. Additionally, its pages can be write protected. The

OTP is not part of the Blackfin processor linear memory map. OTP mem-

ory is not accessed directly using the Blackfin processor memory map,

rather, it is accessed through four 32-bit wide registers (

OTP_DATA0-3

)

which act as the OTP memory read/write buffer.

ADSP-BF54x Blackfin Processor Hardware Reference