2024年6月1日发(作者：祭德厚)

Chapter1

Configuration Overview

Configuration Modes and Pins

Virtex

®

-5 devices are configured by loading application-specific configuration data—the

bitstream—into internal memory. Because Xilinx FPGA configuration memory is volatile,

it must be configured each time it is powered-up. The bitstream is loaded into the device

through special configuration pins. These configuration pins serve as the interface for a

number of different configuration modes:

















Master-serial configuration mode

Slave-serial configuration mode

Master SelectMAP (parallel) configuration mode (x8 and x16 only)

Slave SelectMAP (parallel) configuration mode (x8, x16, and x32)

JTAG/Boundary-Scan configuration mode

Master Serial Peripheral Interface (SPI) Flash configuration mode

Master Byte Peripheral Interface Up (BPI-Up) Flash configuration mode

(x8 and x16 only)

Master Byte Peripheral Interface Down (BPI-Down) Flash configuration mode

(x8 and x16 only)

The configuration modes are explained in detail in Chapter2, “Configuration Interfaces.”

The specific configuration mode is selected by setting the appropriate level on the

dedicated Mode input pins M[2:0]. The M2, M1, and M0 mode pins should be set at a

constant DC voltage level, either through pull-up or pull-down resistors, or tied directly to

ground or V

CC_CONFIG

. The mode pins should not be toggled during and after

configuration. See Table2-1, page37 for the mode pin setting options.

The terms Master and Slave refer to the direction of the configuration clock (CCLK):

In Master configuration modes, the Virtex-5 device drives CCLK from an internal

oscillator. To get the desired frequency, BitGen -g ConfigRate is used. The

“BitGen” section of the

Development System Reference Guide provides more

information. After configuration, the CCLK is turned off unless the

persist

option

is selected or SEU detection is used. The CCLK pin is 3-stated with a weak pull-up.

In Slave configuration modes, CCLK is an input.

The JTAG/Boundary-Scan configuration interface is always available, regardless of the

Mode pin settings. The JTAG/Boundary-Scan configuration mode disables all other

configuration modes to prevent conflicts between configuration interfaces.

Certain pins are dedicated to configuration (Table1-1), while others are dual-purpose

(Table1-2). Dual-purpose pins serve both as configuration pins and as user I/O after

configuration. Dedicated configuration pins retain their function after configuration.

Virtex-5 FPGA Configuration Guide

UG191 (v3.13) July 28, 2020

Configuration Sequence

pin and restarting the configuration process from the beginning. The JTAG interface is still

responsive and the device is still alive, only the BPI/SPI interface is inoperable. In

SelectMAP modes, either the PROGRAM_B pin can be pulsed Low or an ABORT sequence

can be initiated (see “SelectMAP Configuration Interface” in Chapter2).

Virtex-5 devices use a 32-bit CRC check. The CRC check is designed to catch errors in

transmitting the configuration bitstream. There is a scenario where errors in transmitting

the configuration bitstream can be missed by the CRC check: certain clocking errors, such

as double-clocking, can cause loss of synchronization between the 32-bit bitstream packets

and the configuration logic. Once synchronization is lost, any subsequent commands are

not understood, including the command to check the CRC. In this situation, configuration

fails with DONE Low and INIT_B High because the CRC was ignored. In BPI Modes, the

address counter eventually overflows or underflows to cause wraparound, which triggers

fallback reconfiguration (see “Fallback MultiBoot,” page153).

Startup (Step 8)

Steps

1

Device

Power-Up

2

Clear

Configuration

Memory

3

Sample Mode

Pins

4

Synchronization

5

Device ID

Check

6

Load

Configuration

Data

7

CRC Check

8

Startup

Sequence

Start

Bitstream

Loading

Finish

UG191_c1_10_050406

Figure 1-11:Startup Sequence (Step 8)

After the configuration frames are loaded, the bitstream instructs the device to enter the

startup sequence. The startup sequence is controlled by an 8-phase (phases 0–7) sequential

state machine. The startup sequencer performs the tasks outlined in Table1-15.

Table 1-15:

Phase

1

–

6

1

–

6

1

–

6

1

–

6

1

–

6

7

Wait for DCMs to Lock (optional)

Wait for DCI to Match (optional)

Assert

Global Write Enable (GWE)

, allowing RAMs and flip-flops to change state

Negate Global 3-State (GTS), activating I/O

Release DONE pin

Assert End Of Startup (EOS)

User-Selectable Cycle of Startup Events

Event

The specific order of startup events (except for EOS assertion) is user-programmable

through BitGen options (refer to the Development System Reference Guide). Table1-15 shows

the general sequence of events, although the specific phase for each of these startup events

is user-programmable (EOS is always asserted in the last phase). Refer to Chapter2,

“Configuration Interfaces” for important startup option guidelines. By default, startup

events occur as shown in Table1-16.

Virtex-5 FPGA Configuration Guide

UG191 (v3.13) July 28, 2020

2024年6月1日发(作者：祭德厚)

Chapter1

Configuration Overview

Configuration Modes and Pins

Virtex

®

-5 devices are configured by loading application-specific configuration data—the

bitstream—into internal memory. Because Xilinx FPGA configuration memory is volatile,

it must be configured each time it is powered-up. The bitstream is loaded into the device

through special configuration pins. These configuration pins serve as the interface for a

number of different configuration modes:

















Master-serial configuration mode

Slave-serial configuration mode

Master SelectMAP (parallel) configuration mode (x8 and x16 only)

Slave SelectMAP (parallel) configuration mode (x8, x16, and x32)

JTAG/Boundary-Scan configuration mode

Master Serial Peripheral Interface (SPI) Flash configuration mode

Master Byte Peripheral Interface Up (BPI-Up) Flash configuration mode

(x8 and x16 only)

Master Byte Peripheral Interface Down (BPI-Down) Flash configuration mode

(x8 and x16 only)

The configuration modes are explained in detail in Chapter2, “Configuration Interfaces.”

The specific configuration mode is selected by setting the appropriate level on the

dedicated Mode input pins M[2:0]. The M2, M1, and M0 mode pins should be set at a

constant DC voltage level, either through pull-up or pull-down resistors, or tied directly to

ground or V

CC_CONFIG

. The mode pins should not be toggled during and after

configuration. See Table2-1, page37 for the mode pin setting options.

The terms Master and Slave refer to the direction of the configuration clock (CCLK):

In Master configuration modes, the Virtex-5 device drives CCLK from an internal

oscillator. To get the desired frequency, BitGen -g ConfigRate is used. The

“BitGen” section of the

Development System Reference Guide provides more

information. After configuration, the CCLK is turned off unless the

persist

option

is selected or SEU detection is used. The CCLK pin is 3-stated with a weak pull-up.

In Slave configuration modes, CCLK is an input.

The JTAG/Boundary-Scan configuration interface is always available, regardless of the

Mode pin settings. The JTAG/Boundary-Scan configuration mode disables all other

configuration modes to prevent conflicts between configuration interfaces.

Certain pins are dedicated to configuration (Table1-1), while others are dual-purpose

(Table1-2). Dual-purpose pins serve both as configuration pins and as user I/O after

configuration. Dedicated configuration pins retain their function after configuration.

Virtex-5 FPGA Configuration Guide

UG191 (v3.13) July 28, 2020

Configuration Sequence

pin and restarting the configuration process from the beginning. The JTAG interface is still

responsive and the device is still alive, only the BPI/SPI interface is inoperable. In

SelectMAP modes, either the PROGRAM_B pin can be pulsed Low or an ABORT sequence

can be initiated (see “SelectMAP Configuration Interface” in Chapter2).

Virtex-5 devices use a 32-bit CRC check. The CRC check is designed to catch errors in

transmitting the configuration bitstream. There is a scenario where errors in transmitting

the configuration bitstream can be missed by the CRC check: certain clocking errors, such

as double-clocking, can cause loss of synchronization between the 32-bit bitstream packets

and the configuration logic. Once synchronization is lost, any subsequent commands are

not understood, including the command to check the CRC. In this situation, configuration

fails with DONE Low and INIT_B High because the CRC was ignored. In BPI Modes, the

address counter eventually overflows or underflows to cause wraparound, which triggers

fallback reconfiguration (see “Fallback MultiBoot,” page153).

Startup (Step 8)

Steps

1

Device

Power-Up

2

Clear

Configuration

Memory

3

Sample Mode

Pins

4

Synchronization

5

Device ID

Check

6

Load

Configuration

Data

7

CRC Check

8

Startup

Sequence

Start

Bitstream

Loading

Finish

UG191_c1_10_050406

Figure 1-11:Startup Sequence (Step 8)

After the configuration frames are loaded, the bitstream instructs the device to enter the

startup sequence. The startup sequence is controlled by an 8-phase (phases 0–7) sequential

state machine. The startup sequencer performs the tasks outlined in Table1-15.

Table 1-15:

Phase

1

–

6

1

–

6

1

–

6

1

–

6

1

–

6

7

Wait for DCMs to Lock (optional)

Wait for DCI to Match (optional)

Assert

Global Write Enable (GWE)

, allowing RAMs and flip-flops to change state

Negate Global 3-State (GTS), activating I/O

Release DONE pin

Assert End Of Startup (EOS)

User-Selectable Cycle of Startup Events

Event

The specific order of startup events (except for EOS assertion) is user-programmable

through BitGen options (refer to the Development System Reference Guide). Table1-15 shows

the general sequence of events, although the specific phase for each of these startup events

is user-programmable (EOS is always asserted in the last phase). Refer to Chapter2,

“Configuration Interfaces” for important startup option guidelines. By default, startup

events occur as shown in Table1-16.

Virtex-5 FPGA Configuration Guide

UG191 (v3.13) July 28, 2020