2024年6月4日发(作者：答佳思)

Configuration Interfaces

Virtex

®

-5 devices have six configuration interfaces. Each configuration interface

corresponds to one or more configuration modes and bus width, shown in Table2-1. For

detailed interface timing information, see DS202

, Virtex-5 FPGA Data Sheet: DC and

Switching Characteristic.

Table 2-1:Virtex-5 Device Configuration Modes

Configuration Mode

Master Serial

(2)

Master SPI

(2)

Master BPI-Up

(2)

Master BPI-Down

(2)

Master SelectMAP

(2)

JTAG

Slave SelectMAP

Slave Serial

Notes:

el configuration mode bus is auto-detected by the configuration logic.

Master configuration mode, the CCLK pin is the clock source for the Virtex-5 internal configuration

logic. The Virtex-5 CCLK output pin must be free from reflections to avoid double-clocking the

internal configuration logic. Refer to the

“Board Layout for Configuration Clock (CCLK)” section for

more details.

M[2:0]

000

001

010

011

100

101

110

111

Bus Width

1

1

8, 16

8, 16

8, 16

1

8, 16, 32

1

CCLK Direction

Output

Output

Output

Output

Output

Input (TCK)

Input

Input

Serial Configuration Interface

In serial configuration modes, the FPGA is configured by loading one configuration bit per

CCLK cycle:





In Master Serial mode, CCLK is an output.

In Slave Serial mode, CCLK is an input.

Figure2-1 shows the basic Virtex-5 serial configuration interface.

There are four methods of configuring an FPGA in serial mode:







Master serial configuration

Slave serial configuration

Serial daisy-chain configuration

Virtex-5 FPGA Configuration Guide

UG191 (v3.13) July 28, 2020

Chapter 2:Configuration Interfaces

Parallel Daisy Chain

Virtex-5 FPGA configuration supports parallel daisy-chain. Figure2-12 shows an example

schematic of the leading device in BPI mode. The leading device can also be in Master or

Slave SelectMAP modes. The D[15:0], CCLK, RDWR_B, PROGRAM_B, DONE, and

INIT_B pins share a common connection between all of the devices. The CS_B pins are

daisy chained.

4

.

7

k

Ω

3

3

0

Ω

3

3

0

Ω

3

3

0

Ω

A[25:0]

D[15:0]

Flash

FCS_B

FOE_B

FWE_B

BUSY

CSO_B

INIT_B

DONE

PROG

Virtex-5

A[25:0]

FPGA

D[15:0]

FCS_B

FOE_B

FWE_B

CCLK

M2M1M0

0

10

BUSY

CSO_B

INIT_B

DONE

PROG

Virtex-5

FPGA

D[15:0]

CS_B

RDWR_B

CCLK

M2M1M0

110

BUSY

No

CSO_B

INIT_B

Connect

DONE

PROG

D[15:0]

CS_B

Virtex-5

FPGA

RDWR_B

CCLK

M2

M1M0

110

BPI UP

M[2:0]=Slave SelectMAPM[2:0]=Slave SelectMAP

UG191_c2_14_081910

Figure 2-12:

Notes relevant to Figure2-12:

1.

2.

3.

4.

5.

6.

Parallel Daisy Chain

The DONE pin is by default an open-drain output requiring an external pull-up

resistor. In this arrangement, the active DONE driver must be disabled.

The INIT_B pin is a bidirectional, open-drain pin. An external pull-up is required.

The BitGen startup clock setting must be set for CCLK for SelectMAP configuration.

The BUSY signals can be left unconnected if readback is not needed.

The CCLK net requires Thevenin parallel termination. See

“Board Layout for

Configuration Clock (CCLK).”

The FCS_B, FWE_B, FOE_B, CSO_B weak pull-up resistors should be enabled,

otherwise external pull-up resistors are required for each pin. By default, all dual-

mode I/Os have weak pull-downs after configuration.

The first device in the chain can be Master SelectMAP, Slave SelectMAP, BPI-Up, or

BPI-Down.

Readback in the parallel daisy chain scheme is currently not supported.

AES decryption is not available in x16 or x32 mode, only in x8 mode.

7.

8.

9.

ck is not supported in parallel daisy-chain.

Virtex-5 FPGA Configuration Guide

UG191 (v3.13) July 28, 2020

2024年6月4日发(作者：答佳思)

Configuration Interfaces

Virtex

®

-5 devices have six configuration interfaces. Each configuration interface

corresponds to one or more configuration modes and bus width, shown in Table2-1. For

detailed interface timing information, see DS202

, Virtex-5 FPGA Data Sheet: DC and

Switching Characteristic.

Table 2-1:Virtex-5 Device Configuration Modes

Configuration Mode

Master Serial

(2)

Master SPI

(2)

Master BPI-Up

(2)

Master BPI-Down

(2)

Master SelectMAP

(2)

JTAG

Slave SelectMAP

Slave Serial

Notes:

el configuration mode bus is auto-detected by the configuration logic.

Master configuration mode, the CCLK pin is the clock source for the Virtex-5 internal configuration

logic. The Virtex-5 CCLK output pin must be free from reflections to avoid double-clocking the

internal configuration logic. Refer to the

“Board Layout for Configuration Clock (CCLK)” section for

more details.

M[2:0]

000

001

010

011

100

101

110

111

Bus Width

1

1

8, 16

8, 16

8, 16

1

8, 16, 32

1

CCLK Direction

Output

Output

Output

Output

Output

Input (TCK)

Input

Input

Serial Configuration Interface

In serial configuration modes, the FPGA is configured by loading one configuration bit per

CCLK cycle:





In Master Serial mode, CCLK is an output.

In Slave Serial mode, CCLK is an input.

Figure2-1 shows the basic Virtex-5 serial configuration interface.

There are four methods of configuring an FPGA in serial mode:







Master serial configuration

Slave serial configuration

Serial daisy-chain configuration

Virtex-5 FPGA Configuration Guide

UG191 (v3.13) July 28, 2020

Chapter 2:Configuration Interfaces

Parallel Daisy Chain

Virtex-5 FPGA configuration supports parallel daisy-chain. Figure2-12 shows an example

schematic of the leading device in BPI mode. The leading device can also be in Master or

Slave SelectMAP modes. The D[15:0], CCLK, RDWR_B, PROGRAM_B, DONE, and

INIT_B pins share a common connection between all of the devices. The CS_B pins are

daisy chained.

4

.

7

k

Ω

3

3

0

Ω

3

3

0

Ω

3

3

0

Ω

A[25:0]

D[15:0]

Flash

FCS_B

FOE_B

FWE_B

BUSY

CSO_B

INIT_B

DONE

PROG

Virtex-5

A[25:0]

FPGA

D[15:0]

FCS_B

FOE_B

FWE_B

CCLK

M2M1M0

0

10

BUSY

CSO_B

INIT_B

DONE

PROG

Virtex-5

FPGA

D[15:0]

CS_B

RDWR_B

CCLK

M2M1M0

110

BUSY

No

CSO_B

INIT_B

Connect

DONE

PROG

D[15:0]

CS_B

Virtex-5

FPGA

RDWR_B

CCLK

M2

M1M0

110

BPI UP

M[2:0]=Slave SelectMAPM[2:0]=Slave SelectMAP

UG191_c2_14_081910

Figure 2-12:

Notes relevant to Figure2-12:

1.

2.

3.

4.

5.

6.

Parallel Daisy Chain

The DONE pin is by default an open-drain output requiring an external pull-up

resistor. In this arrangement, the active DONE driver must be disabled.

The INIT_B pin is a bidirectional, open-drain pin. An external pull-up is required.

The BitGen startup clock setting must be set for CCLK for SelectMAP configuration.

The BUSY signals can be left unconnected if readback is not needed.

The CCLK net requires Thevenin parallel termination. See

“Board Layout for

Configuration Clock (CCLK).”

The FCS_B, FWE_B, FOE_B, CSO_B weak pull-up resistors should be enabled,

otherwise external pull-up resistors are required for each pin. By default, all dual-

mode I/Os have weak pull-downs after configuration.

The first device in the chain can be Master SelectMAP, Slave SelectMAP, BPI-Up, or

BPI-Down.

Readback in the parallel daisy chain scheme is currently not supported.

AES decryption is not available in x16 or x32 mode, only in x8 mode.

7.

8.

9.

ck is not supported in parallel daisy-chain.

Virtex-5 FPGA Configuration Guide

UG191 (v3.13) July 28, 2020