EMMC东芝8GBFLASH 耐擦写相关的证明报告15nm-USB迷|专注于互联网分享

2024年6月12日发(作者：冼慕诗)

TOSHIBA CONFIDENTIAL

TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

Reliability Note for 15nm MLC (Multi-Level-Cell) NAND Flash Memory of JEDEC

Ver.5.1 e•MMC

DESCRIPTION

This reliability note is intended to provide some guidance related to using 15nm MLC NAND flash. The following reliability data

are experimental results to be used for reference, and are based on using built in ECC and a read retry sequence(s).

Although random bit errors may occur during use, it does not necessarily mean that a block is bad. Generally, a block should be

marked as bad when a program status failure or erase status failure is detected. The other failure modes may be recovered by a block

erase.

ECC treatment for read data is mandatory due to the following Data Retention and Read Disturb failures.

RELIABILITY NOTE

 Write/Erase Endurance

Write/Erase endurance failures may occur in a cell, page, or block, and are detected by doing a status read after either an auto

program or auto block erase operation. The cumulative bad block count will increase along with the number of write/erase

cycles.

Write/Erase Cumulative Block

Cycle Failure Rate

[%]

3,000 Less than 0.04

 Data Retention

The data in memory may change after a certain amount of storage time. This is due to charge loss or charge gain. After block

erasure and reprogramming, the block may become usable again.

Here are the combined characteristics of Write/Erase Endurance and Data Retention.

Write/Erase Estimated Data

Cycles Retention Time

[Years]

Data

Initial

Retention

[Years]

(less than 100)

3,000 1

(Note) Conditions for estimated data retention time:

- Vcc = 3.3V, Ta = 40

C, with built in ECC

Write/Erase Cycles

- Cumulative failure rate: max 1,000ppm

- The 1,000 ppm above is the device failure rate

when one or more 1 KB areas become uncorrectable.

 Read Disturb

A read operation may disturb the data in memory. The data may change due to charge gain. Usually, bit errors occur on other

pages in the block, not the page being read. After a large number of read cycles (between block erases), a tiny charge may build

up and can cause a cell to be soft programmed to another state. After block erasure and reprogramming, the block may become

usable again.

(Note) Conditions for estimated Read cycles per page:

Write/Erase Estimated Read

- Vcc = 3.3V, Ta = 40

C, with built in ECC

Cycles Cycles per page

- Cumulative failure rate: max 1,000 ppm

[Cycles]

- The 1,000 ppm above is the device failure rate when one or

Initial

100,000

more 1 KB areas become uncorrectable.

(less than 100)

3,000 10,000

Rev.1.0 Apr. 10th, 2015

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