2024年6月15日发(作者：凭运洁)
45–55%T GEMTXCKO RGMII_TX_D[3:0], RGMII_TX_CTL output clock to out time –0.50–0.50ns T GEMRXDCK
RGMII_RX_D[3:0], RGMII_RX_CTL input setup time 0.80––ns T GEMRXCKD RGMII_RX_D[3:0], RGMII_RX_CTL input
hold time 0.80––ns T MDIOCLK MDC output clock period 400––ns T MDIOCKH MDC clock High time 160––ns T MDIOCKL
MDC clock Low time 160––ns T MDIODCK MDIO input data setup time 80––ns T MDIOCKD MDIO input data hold time 0––
ns T MDIOCKO MDIO data output delay
–20–170ns F GETXCLK RGMII_TX_CLK transmit clock frequency –125–MHz F GERXCLK RGMII_RX_CLK receive clock
frequency – 125–MHz F ENET_REF_CLK
Ethernet reference clock frequency
–
125
–
MHz
Notes:
conditions: LVCMOS25, fast slew rate, 8mA drive strength, 15pF loads. Values in this table are specified during
1000Mb/s operation.
25 slow slew rate and LVCMOS33 are not supported.
3.
All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional
external clock jitter.
Figure 7: RGMII Interface Timing Diagram
I2C Interfaces
Table 39:I2C Fast Mode Interface Switching Characteristics (1)
Symbol Description
Min Typ Max Units T DCI2CFCLK I2C {0,1}SCL duty cycle
–50–%
T I2CFCKO I2C {0,1}SDAO clock to out delay ––900ns T I2CFDCK I2C {0,1}SDAI setup time 100––ns F I2CFCLK I2C
{0,1}SCL clock frequency
–
–
400
KHz
Notes:
1.
Test conditions: LVCMOS33, slow slew rate, 8mA drive strength, 15pF loads.
2024年6月15日发(作者：凭运洁)
45–55%T GEMTXCKO RGMII_TX_D[3:0], RGMII_TX_CTL output clock to out time –0.50–0.50ns T GEMRXDCK
RGMII_RX_D[3:0], RGMII_RX_CTL input setup time 0.80––ns T GEMRXCKD RGMII_RX_D[3:0], RGMII_RX_CTL input
hold time 0.80––ns T MDIOCLK MDC output clock period 400––ns T MDIOCKH MDC clock High time 160––ns T MDIOCKL
MDC clock Low time 160––ns T MDIODCK MDIO input data setup time 80––ns T MDIOCKD MDIO input data hold time 0––
ns T MDIOCKO MDIO data output delay
–20–170ns F GETXCLK RGMII_TX_CLK transmit clock frequency –125–MHz F GERXCLK RGMII_RX_CLK receive clock
frequency – 125–MHz F ENET_REF_CLK
Ethernet reference clock frequency
–
125
–
MHz
Notes:
conditions: LVCMOS25, fast slew rate, 8mA drive strength, 15pF loads. Values in this table are specified during
1000Mb/s operation.
25 slow slew rate and LVCMOS33 are not supported.
3.
All timing values assume an ideal external input clock. Actual design system timing budgets should account for additional
external clock jitter.
Figure 7: RGMII Interface Timing Diagram
I2C Interfaces
Table 39:I2C Fast Mode Interface Switching Characteristics (1)
Symbol Description
Min Typ Max Units T DCI2CFCLK I2C {0,1}SCL duty cycle
–50–%
T I2CFCKO I2C {0,1}SDAO clock to out delay ––900ns T I2CFDCK I2C {0,1}SDAI setup time 100––ns F I2CFCLK I2C
{0,1}SCL clock frequency
–
–
400
KHz
Notes:
1.
Test conditions: LVCMOS33, slow slew rate, 8mA drive strength, 15pF loads.