ATMEL 爱特梅尔Flash 存储器AT25F512A 数据手册-USB迷|专注于互联网分享

2024年7月12日发(作者：杨茂才)

BDTIC /ATMEL

Features

•

Serial Peripheral Interface (SPI) Compatible

•

Supports SPI Modes 0 (0,0) and 3 (1,1)

–Datasheet Describes 0 Operation

•

33 MHz Clock Rate

•

Byte Mode and 128-byte Page Mode for Program Operations

•

Sector Architecture:

–Two Sectors with 32K Bytes Each

–256 Pages per Sector

•

Product Identification Mode

•

Low-voltage Operation

–2.7 (V

•

= 2.7 to 3.6V)

Sector Write Protection

•

Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software

Data Protection

•

Self-timed Program Cycle (75 µs/byte typical)

•

Self-timed Sector Erase Cycle (1 second/sector typical)

•

Single Cycle Reprogramming (Erase and Program) for Status Register

•

High Reliability

–Endurance: 10,000 Write Cycles Typical

–Data Retention: 20 Years

•

8-lead JEDEC SOIC and 8-lead SAP Packages

Description

The AT25F512A provides 524,288 bits of serial reprogrammable Flash memory orga-

nized as 65,536 words of 8 bits each. The device is optimized for use in many

industrial and commercial applications where low-power and low-voltage operation

are essential. The AT25F512A is available in a space-saving 8-lead JEDEC SOIC and

8-lead SAP packages.

The AT25F512A is enabled through the Chip Select pin (CS) and accessed via a

three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and

Serial Clock (SCK). All write cycles are completely self-timed.

Block write protection for the entire memory array is enabled by programming the sta-

tus register. Separate write enable and write disable instructions are provided for

additional data protection. Hardware data protection is provided via the Write Protect

(WP) pin to protect against inadvertent write attempts to the status register. The HOLD

pin may be used to suspend any serial communication without resetting the serial

sequence.

Table 1. Pin Configuration

8-lead SOIC

Pin NameFunction

CS1

VCC

Chip Select

SO2

HOLD

WP3

SCK

SCKSerial Data Clock

GND4

SISerial Data Input

SOSerial Data Output

8-lead SAP

VCC

GNDGround

HOLD

VCCPower Supply

SCK

GND

Write Protect

HOLD

Suspends Serial Input

Bottom View

512Kbit High

Speed SPI

Serial Flash

Memory

512K (65,536 x 8)

AT25F512A

Rev. 3345F–FLASH–11/06

Absolute Maximum Ratings*

−40°C to +85°C

−65°C to +150°C

Voltage on Any Pin

with Respect −1.0V to +5.0V

Maximum .4.2V

DC 5.0 mA

*NOTICE:Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Figure 1. Block Diagram

65,536 x 8

AT25F512A

3345F–FLASH–11/06

AT25F512A

Table 2. Pin Capacitance

(1)

Applicable over recommended operating range from T

= 25°C, f = 20 MHz, V

= +3.6V (unless otherwise noted)

Symbol

OUT

Note:

Test Conditions

Output Capacitance (SO)

Input Capacitance (CS, SCK, SI, WP, HOLD)

parameter is characterized and is not 100% tested.

Max

Units

Conditions

OUT

= 0V

Table 3. DC Characteristics

(1)

Applicable over recommended operating range from: T

= −40 to +85°C, V

= +2.7 to +3.6V,

= 0 to +70°C, V

= +2.7 to +3.6V (unless otherwise noted)

Symbol

CC1

CC2

(2)

Notes:

Parameter

Supply Voltage

Supply Current

Standby Current

Input Leakage

Output Leakage

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

2.7V ≤ V

≤ 3.6V

= 0.15 mA

= −100 µAV

− 0.2

= 3.6V at 33 MHz, SO = Open Read

= 3.6V at 33 MHz, SO = Open Write

= 2.7V, CS = V

; SCK, SI, WP,

HOLD = 0V or V

= 0V or V

, T

= −40°C to 85°C

−3.0

−0.6

x 0.7

Test ConditionMin

2.7

10.0

25.0

2.0

TypMax

3.6

15.0

35.0

10.0

3.0

x 0.3

+ 0.5

0.2

Units

µA

inary – subject to change

2.V

and V

max are reference only and are not tested.

3345F–FLASH–11/06

Table 4. AC Characteristics (Preliminary - Subject to Change)

Applicable over recommended operating range from T

= −40 to +85°C, V

= +2.7 to +3.6V

= 1 TTL Gate and 30 pF (unless otherwise noted)

Symbol

SCK

CSS

CSH

DIS

BPC

Endurance

(2)

Notes:

Parameter

SCK Clock Frequency

Input Rise Time

Input Fall Time

SCK High Time

SCK Low Time

CS High Time

CS Setup Time

CS Hold Time

Data In Setup Time

Data In Hold Time

Hold Setup Time

Hold Time

Output Valid

Output Hold Time

Hold to Output Low Z

Hold to Output High Z

Output Disable Time

Erase Cycle Time per Sector

Status Register Write Cycle Time

Byte Program Cycle Time

(1)

10K

200

100

1.1

100

Min

TypMax

Units

MHz

µs

Write Cycles

(3)

programming time for n bytes will be equal to n x t

BPC

parameter is ensured by characterization at 3.0V, 25°C only.

write cycle consists of erasing a sector, followed by programming the same sector.

AT25F512A

3345F–FLASH–11/06

AT25F512A

Serial Interface

Description

MASTER: The device that generates the serial clock.

SLAVE: Because the SCK pin is always an input, the AT25F512A always operates as a

slave.

TRANSMITTER/RECEIVER:The AT25F512A has separate pins designated for data

transmission (SO) and reception (SI).

MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.

SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be

received. This byte contains the op-code that defines the operations to be performed.

INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the

AT25F512A, and the serial output pin (SO) will remain in a high impedance state until

the falling edge of CS is detected again. This will reinitialize the serial communication.

CHIP SELECT: The AT25F512A is selected when the CS pin is low. When the device is

not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will

remain in a high impedance state.

HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25F512A.

When the device is selected and a serial sequence is underway, HOLD can be used to

pause the serial communication with the master device without resetting the serial

sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To

resume serial communication, the HOLD pin is brought high while the SCK pin is low

(SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin

is in the high impedance state.

WRITE PROTECT: The AT25F512A has a write lockout feature that can be activated by

asserting the WP pin. When the lockout feature is activated, locked-out sectors will be

read only. The write protect pin will allow normal read/write operations when held high.

When the WP is brought low and WPEN bit is “1”, all write operations to the status register

are inhibited. WP going low while CS is still low will interrupt a write to the status register.

If the internal status register write cycle has already been initiated, WP going low will have

no effect on any write operation to the status register. The WP pin function is blocked

when the WPEN bit in the status register is “0”. This will allow the user to install the

AT25F512A in a system with the WP pin tied to ground and still be able to write to the sta-

tus register. All WP pin functions are enabled when the WPEN bit is set to “1”.

3345F–FLASH–11/06

Figure 2. SPI Serial Interface

MASTER:

MICROCONTROLLER

DATA OUT (MOSI)

DATA IN (MISO)

SERIAL CLOCK (SPI CK)

SS0

SS1

SS2

SS3

SLAVE:

AT25F512A

SCK

AT25F512A

3345F–FLASH–11/06

AT25F512A

Functional

Description

The AT25F512A is designed to interface directly with the synchronous serial peripheral

interface (SPI) of the 6800 type series of microcontrollers.

The AT25F512A utilizes an 8-bit instruction register. The list of instructions and their

operation codes are contained in Table 5. All instructions, addresses, and data are

transferred with the MSB first and start with a high-to-low transition.

Write is defined as program and/or erase in this specification. The commands Program,

Sector Erase, Chip Erase, and WRSR are write instructions for AT25F512A.

Table 5. Instruction Set for the AT25F512A

Instruction Name

WREN

WRDI

RDSR

WRSR

READ

PROGRAM

SECTOR ERASE

CHIP ERASE

RDID

Instruction

Format

0000 X110

0000 X100

0000 X101

0000 X001

0000 X011

0000 X010

0101 X010

0110 X010

0001 X101

Operation

Set Write Enable Latch

Reset Write Enable Latch

Read Status Register

Write Status Register

Read Data from Memory Array

Program Data into MemoryArray

Erase One Sector in MemoryArray

Erase All Sectors in MemoryArray

Read Manufacturer and ProductID

WRITE ENABLE (WREN): The device will power up in the write disable state when V

is applied. All write instructions must therefore be preceded by the WREN instruction.

WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the WRDI

instruction disables all write commands. The WRDI instruction is independent of the sta-

tus of the WP pin.

READ STATUS REGISTER (RDSR): The RDSR instruction provides access to the sta-

tus register. The Ready/Busy and write enable status of the device can be determined

by the RDSR instruction. Similarly, the block write protection bits indicate the extent of

protection employed. These bits are set by using the WRSR instruction. During internal

write cycles, all other commands will be ignored except the RDSR instruction.

Table 6. Status Register Format

Bit 7

WPEN

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

BP0

Bit 1

WEN

Bit 0

RDY

3345F–FLASH–11/06

Table 7. Read Status Register Bit Definition

Bit

Bit 0 (RDY)

Bit 1 (WEN)

Bit 2 (BP0)

Definition

Bit 0 = “0” (RDY) indicates the device is ready. Bit0=“1” indicates the

write cycle is in progress.

Bit 1 = “0” indicates the device is not write enabled. Bit 1 = “1” indicates

the device is write enabled.

See Table 8.

Bits 3–6 are “0”s when device is not in an internal write cycle.

Bit 7 (WPEN) See Table 9.

Bits 0–7 are “1”s during an internal write cycle.

READ PRODUCT ID (RDID): The RDID instruction allows the user to read the manufac-

turer and product ID of the device. The first byte after the instruction will be the

manufacturer code (1FH = ATMEL), followed by the device code, 65H.

WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select

two levels of protection for the AT25F512A. The AT25F512A is divided into two sectors

where all of the memory sectors can be protected (locked out) from write. Any of the

locked-out sectors will therefore be read only. The locked-out sectors and the corre-

sponding status register control bits are shown in Table 8.

The two bits, BP0 and WPEN, are nonvolatile cells that have the same properties and

functions as the regular memory cells (e.g., WREN, t

, RDSR).

Table 8. Block Write Protect Bits

Status Register Bits

BP0

AT25F512A

Array Addresses Locked Out

None

000000–00FFFF

Locked-out Sector(s)

None

All sectors (1–2)

The WRSR instruction also allows the user to enable or disable the WP pin through the

use of the WPEN bit. Hardware write protection is enabled when the WP pin is low and

the WPEN bit is “1”. Hardware write protection is disabled when either the WP pin is

high or the WPEN bit is “0.” When the device is hardware write protected, writes to the

status register, including the block protect bit and the WPEN bit, and the locked-out sec-

tors in the memory array are disabled. The WRSR instruction is self-timed to

automatically erase and program BP0 and WPEN bits. In order to write the status regis-

ter, the device must first be write enabled via the WREN instruction. Then, the

instruction and data for the two bits are entered. During the internal write cycle, all

instructions will be ignored except RDSR instructions. The AT25F512A will automatically

return to write disable state at the completion of the WRSR cycle.

Note:When the WPEN bit is hardware write protected, it cannot be changed back to “0” as

long as the WP pin is held low.

AT25F512A

3345F–FLASH–11/06

AT25F512A

Table 9. WPEN Operation

WPEN

Low

High

WEN

ProtectedBlocks

Protected

UnprotectedBlocks

Protected

Writeable

Protected

Writeable

Protected

Writeable

Status Register

Protected

Writeable

Protected

Writeable

READ (READ): Reading the AT25F512A via the SO pin requires the following

sequence. After the CS line is pulled low to select a device, the Read instruction is

transmitted via the SI line followed by the three-byte address to be read (see Table 10

on page 10). Upon completion, any data on the SI line will be ignored. The data (D7–D0)

at the specified address is then shifted out onto the SO line. If only one byte is to be

read, the CS line should be driven high after the data comes out. The Read instruction

can be continued since the byte address is automatically incremented and data will con-

tinue to be shifted out. When the highest address is reached, the address counter will

roll over to the lowest address, allowing the entire memory to be read in one continuous

READ instruction.

PROGRAM (PROGRAM): In order to program the AT25F512A, two separate instruc-

tions must be executed. First, the CS line is pulled low to select the device, the device

must be write enabled via the WREN instruction. Then, the Program instruction can be

executed.

The Program instruction requires the following sequence. After the CS line is pulled low

to select the device, the PROGRAM instruction is transmitted via the SI line followed by

the three-byte address and the data (D7–D0) to be programmed (see Table 10 on page

10). Programming will start after the CS pin is brought high. The low-to-high transition of

the CS pin must occur during the SCK low time immediately after clocking in the D0

(LSB) data bit (assuming mode 0 operation). During an internal self-timed programming

cycle, all commands will be ignored except the RDSR instruction.

The Ready/Busy status of the device can be determined by initiating a RDSR instruc-

tion. If Bit 0 = “1”, the program cycle is still in progress. If Bit 0 = “0”, the program cycle

has ended. Only the RDSR instruction is enabled during the program cycle.

A single PROGRAM instruction programs 1 to 128 consecutive bytes within a page if it

is not write protected. The starting byte could be anywhere within the page. When the

end of the page is reached, the address will wrap around to the beginning of the same

page. If the data to be programmed are less than a full page, the data of all other bytes

on the same page will remain unchanged. If more than 128 bytes of data are provided,

the address counter will roll over on the same page and the previous data provided will

be replaced. The same byte cannot be reprogrammed without erasing the whole sector

first. The AT25F512A will automatically return to the write disable state at the completion

of the program cycle.

Note:If the device is not write enabled (WREN), the device will ignore the WRITE instruction

and will return to the standby state when CS is brought high. A new CS falling edge is

required to re-initiate the serial communication.

3345F–FLASH–11/06

Table 10. Address Key

Address

Don’t Care Bits

AT25F512A

– A

SECTOR ERASE (SECTOR ERASE): Before a byte can be reprogrammed, the sector

containing the byte must be erased. In order to erase the AT25F512A, two separate

instructions must be executed. First, the device must be write enabled via the WREN

instruction. Then the SECTOR ERASE instruction can be executed.

Table 11. Sector Addresses

Sector Address

000000 to 007FFF

008000 to 00FFFF

AT25F512A Sector

Sector 1

Sector 2

The Sector Erase instruction erases every byte in the selected sector if the device is not

locked out. Sector address is automatically determined if any address within the sector

is selected. The SECTOR ERASE instruction is internally controlled; it will automatically

be timed to completion. During this time, all commands will be ignored except RDSR

instruction. The AT25F512A will automatically return to the WRDI state at the comple-

tion of the sector erase cycle.

CHIP ERASE (CHIP ERASE): As an alternative to the Sector Erase, the Chip Erase

instruction will erase every byte in both sectors if the device is not locked out. First, the

device must be write enabled via the WREN instruction. Then the Chip Erase instruction

can be executed. The Chip Erase instruction is internally controlled; it will automatically

be timed to completion. The chip erase cycle time typically is 2 seconds. During the

internal erase cycle, all instructions will be ignored except RDSR. The AT25F512A will

automatically return to the WRDI state at the completion of the chip erase cycle.

AT25F512A

3345F–FLASH–11/06

AT25F512A

Timing Diagrams (for SPI Mode 0 (0, 0))

Figure 3. Synchronous Data Timing

CSS

SCK

HI-Z

DIS

HI-Z

VALIDIN

CSH

Figure 4. WREN Timing

SCK

WREN OP-CODE

HI-Z

Figure 5. WRDI Timing

SCK

WRDI OP-CODE

HI-Z

3345F–FLASH–11/06

Figure 6. RDSR Timing

SCK

1112131415

INSTRUCTION

DATA OUT

HIGH IMPEDANCE

MSB

6543210

Figure 7. WRSR Timing

1234567891

SCK

DATA IN

INSTRUCTION

76543210

HIGH IMPEDANCE

Figure 8. READ Timing

SCK

33343536373839

3-BYTE ADDRESS

INSTRUCTION232221

...

3210

HIGH IMPEDANCE

76543210

AT25F512A

3345F–FLASH–11/06

AT25F512A

Figure 9. PROGRAM Timing

SCK

3334

1st BYTE DATA-IN

128th BYTE DATA-IN

3-BYTE ADDRESS

INSTRUCTION

2322210

HIGH IMPEDANCE

Figure 10. HOLD Timing

SCK

HOLD

Figure 11. SECTOR ERASE Timing

2829

SCK

INSTRUCTION

3-BYTE ADDRESS

1 0 23 22 21

...

HIGH IMPEDANCE

X = Don’t Care bit

3345F–FLASH–11/06

Figure 12. CHIP ERASE Timing

SCK

011

HIGH IMPEDANCE

X = Don’t Care bit

Figure 13. RDID Timing

910

71819

2122

SCK

001

HIGH IMPEDANCE

MANUFACTURER

CODE (ATMEL)

DATA OUT

DEVICE CODE

AT25F512A

3345F–FLASH–11/06

AT25F512A

Ordering Information

Ordering Code

AT25F512AN-10SH-2.7

AT25F512AY4-10YH-2.7

Package

8S1

8Y4

Operation Range

Lead-free/Halogen-free/NiPdAu Lead Finish

Industrial Temperature

(−40 to 85°C)

Package Type

8S1

8Y4

8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)

8-lead, 6.00 mm x 4.90 mm Body, Dual Footprint, Non-leaded, Small Array Package (SAP)

Options

−2.7Low-voltage (2.7 to 3.6V)

3345F–FLASH–11/06

Packaging Information

8S1 – SOIC

∅

Top View

End View

SYMBOL

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

1.35

0.10

0.31

0.17

4.80

3.81

5.79

NOM

–

1.27 BSC

0.40

0˚

–

1.27

8˚

MAX

1.75

0.25

0.51

0.25

5.00

3.99

6.20

NOTE

Side View

∅

Note:

These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.

10/7/03

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TITLE

8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing

Small Outline (JEDEC SOIC)

DRAWING NO.

8S1

REV.

AT25F512A

3345F–FLASH–11/06

AT25F512A

8Y4 – SAP

PIN 1 INDEX AREA

PIN 1 ID

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

MIN

–

0.00

5.80

4.70

2.85

0.35

NOM

–

6.00

4.90

3.00

0.40

1.27 TYP

3.81 REF

MAX

0.90

0.05

6.20

5.10

3.15

0.45

NOTE

L0.500.600.70

5/24/04

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TITLE

8Y4, 8-lead (6.00 x 4.90 mm Body) SOIC Array Package

(SAP) Y4

DRAWING NO.

8Y4

REV.

3345F–FLASH–11/06

Revision History

Document No.

3345F

Comments

Removed preliminary status”