2024年9月9日发(作者:功鸿志)
深圳市和芯润德科技有限公司
USB3.2 Gen1X1 4口集线器芯片
SL6340
简要数据手册
V1.1
2023.09.25
1
USB3.2 Gen1X1接口4口集线器控制器集成电路
概述
SL6340是一款USB3.2 Gen1X1接口的4口HUB控制器芯片,片上集成32
位微处理器,它具有低功耗、高性能、可配置等特点;芯片集成USB3.0高速物
理层收发器和USB2.0高速物理层收发器,使得芯片可以完美支持超高速、高速
和低速USB上下行设备连接;芯片集成度高,内部集成5V转3.3V和5V转1.1V
DCDC,极大的精简了外围电路。
SL6340支持符合USB IF规范的BC1.2快充协议,他可以为苹果、三星设备
提供最高1.5A的充电电流。
SL6340支持通过外挂SPI-flash/EEPROM配置设备信息,本版本SL6340芯片
必须配置SPI-FLASH使用,我司提供配置程序/或完成程序配置的SPI-FLASH。
功能特点
SL6340符合USB3.2 V1.0 规范。
SL6340向下兼容支持USB2.0、USB1.1规范
SL6340上行口支持超高速SS、高速HS、低速FS设备
SL6340下行口支持超高速SS、高速HS、全速FS、低速LS设备
SL6340S支持一路控制和一路中断
SL6340集线器芯片上行口USB和下行口USB端口都支持BC1.2快充协议
支持BC1.2快充协议、支持SDP(Standard Downstream Port), CDP,DCP, and ACA-
Dock
SL6340支持数据传输同时为移动设备充电(BC1.2)
SL6340下行口USB可以从标准的USB口切换为快充口或者专用充电端口
SL6340上游非标准USB HOST/OTG,依然可以支持BC1.2快充协议,此时需要
电源适配器行供电.
SL6340集成USB3.2 Gen1X1 超高速收发器,集成USB2.0高速收发器
SL6340下行端口设备支持过流保护,支持USB2.0挂起和恢复。
SL6340支持下行端口(单口/多口)电源使能
SL6340支持通过外挂SPI-flash/EEPROM配置设备信息
支持通过SPI-Flash/EEPROM固件升级
支持通过SPI-Flash/EEPROM配置BC1.2充电功能
支持通过SPI-Flash/EEPROM自定义设备VID/PID
支持通过SPI-Flash/EEPROM配置LED闪灯方式等
SL6340支持自供电模式,同时也总线供电模式
SL6340支持USB3.0 PHY收发自适应
SL6340支持单个24M晶体/振荡器时钟输入,
SL6340上行端口集成1.5KΩ上拉、下游端口集成15KΩ下拉电阻器
SL6340才有QFN80 8X8扁平封装
2
产品应用
独立的3.0 HUB集线器、type-c扩展坞、dock底座等
服务器、PC、笔记本等USB3.0扩展
商业显示、会议平板等嵌入式系统USB3.0接口扩展
工业控制USB3.0扩展
车载HUB
USB挂式充电墙
其他消费类电子
芯片内部功能框图
SL6340功能框图
3
管脚排列
SL6340 管脚排列图
管脚定义
1.1
Pin Description
QFN 80 Pin name Type Description
Table 4.2 –1 Power and GND
41, 64 VIN_5V I 5v Adapter Input or Vbus input
40 VIN_33V I 3.3v Power Input
63 VOUT_33V O 3.3v power output
42 VOUT_11V O
NC,should be floating
17,23,29,35,67,78 AVDD_33V I 3.3v Analog power
4
18,24,30,36,68,79 AVDD_11V I
5,61
13,45
14,39,43,44
81
VDD_33V
VDD_11V
VSS
EPAD
I
I
-
P
1.1v Analog power
3.3v Digital power
1.1v Digital power
GND
EPAD
Table 4.2 – 2 USB2.0 Interface
71
72
73
74
75
76
80
1
2
3
77
UP_DP
UP_DM
DN1_DP
DN1_DM
DN2_DP
DN2_DM
DN3_DP
DN3_DM
DN4_DP
DN4_DM
RREF
B
B
B
B
B
B
B
B
B
B
I
USB2.0 DP for Upstream Port
USB2.0 DM for Upstream Port
USB2.0 DP for Downstream Port 1
USB2.0 DM for Downstream Port1
USB2.0 DP for Downstream Port 2
USB2.0 DM for Downstream Port2
USB2.0 DP for Downstream Port 3
USB2.0 DM for Downstream Port3
USB2.0 DP for Downstream Port 4
USB2.0 DM for Downstream Port4
USB2.0 Reference Input, connect to 200ohm 1%
Resister
Table 4.2 – 3 USB3.2 Interface
65
66
69
70
15
16
19
20
21
22
25
UP_RXP
UP_RXN
UP_TXP
UP_TXN
DN1_RXP
DN1_RXN
DN1_TXP
DN1_TXN
DN2_RXP
DN2_RXN
DN2_TXP
I
I
O
O
I
I
O
O
I
I
O
USB3.0 Differential Data Receiver Rx+ for Upstream
Port
USB3.0 Differential Data Receiver Rx- for Upstream
Port
USB3.0 Differential Data Transmitter Tx+ for
Upstream Port
USB3.0 Differential Data Transmitter Tx- for
Upstream Port
USB3.0 Differential Data Receiver Rx+ for
Downstream Port1
USB3.0 Differential Data Receiver Rx- for
Downstream Port1
USB3.0 Differential Data Receiver Tx+ for
Downstream Port1
USB3.0 Differential Data Receiver Tx- for
Downstream Port1
USB3.0 Differential Data Receiver Rx+ for
Downstream Port2
USB3.0 Differential Data Receiver Rx- for
Downstream Port2
USB3.0 Differential Data Receiver Tx+ for
Downstream Port2
5
26
27
28
31
32
33
34
37
38
DN2_TXN
DN3_RXP
DN3_RXN
DN3_TXP
DN3_TXN
DN4_RXP
DN4_RXN
DN4_TXP
DN4_TXN
O
I
I
O
O
I
I
O
O
USB3.0 Differential Data Receiver Tx- for
Downstream Port2
USB3.0 Differential Data Receiver Rx+ for
Downstream Port3
USB3.0 Differential Data Receiver Rx- for
Downstream Port3
USB3.0 Differential Data Receiver Tx+ for
Downstream Port3
USB3.0 Differential Data Receiver Tx- for
Downstream Port3
USB3.0 Differential Data Receiver Rx+ for
Downstream Port4
USB3.0 Differential Data Receiver Rx- for
Downstream Port4
USB3.0 Differential Data Receiver Tx+ for
Downstream Port4
USB3.0 Differential Data Receiver Tx- for
Downstream Port4
Table 4.2 – 4 Clock, Reset and Tes
6
7
4
8
OSC_XI
OSC_XO
TE
RSTN
I
O
I
I
Crystal/OSC Clock input
Crystal Clock output
Test Enable
Reset input, Active Low
Table 4.2 – 5 Misc & Digital Interfac
e
9 PwrMode B/PU Power Mode Selection
0 : Set Hub to BusPower Mode
1 : Set Hub to SelfPower Mode
It is also the power mode indicator
B/PU 0 : DownStream Port goto DCP mode
1 : DownStream Port under normal mode (SDP)
O/PU Strapping stage : ACA_Dock mode enable
0 : enable ACA DOCK mode for Downstream Port
1 : disable ACA DOCK mode for Downstream Port
Normal stage : Debug uart tx Pin
I/PU Debug uart Rx
O/PU Strapping stage : Mcu Enable
1 : enable internal Mcu
0 : disable internal Mcu
Normal stage : spi chip selection signal
B/PU Spi clock signal
O/PD Strapping stage : mcu IIC or spi selection
1 : iic eeprom
6
10
11
DCP_En
DBG_TXD
12
62
DBG_RXD
SPI_SC
59
60
SPI_CLK
SPI_MOSI
0 : spi flash (default)
Normal stage : spi Master Output Slave Input signal
57
58
SPI_MISO
LED4
I/PU Spi Master Input Slave Output signal
O/PD Strapping stage : DnPort4 non-removable setting bit
1 : Connected non-removable device under DnPort4
0 : No non-removable device under DnPort4
Normal stage : LED4, not used under 3-wire or 1-wire
mode
1 : light on LED4 for DnPort 4 when 4-wire mode
0 : light off LED4 for DnPort 4 when 4-wire mode
O/PD Strapping stage : DnPort3 non-removable setting bit
1 : Connected non-removable device under DnPort3
0 : No non-removable device under DnPort3
Normal stage : LED3, when under 3-wire mode, It is
the LED_DRV signal, not used under 1-wire mode
1 : light on LED3 for DnPort 3 when 4-wire mode
0 : light off LED3 for DnPort 3 when 4-wire mode
O/PD Strapping stage : DnPort2 non-removable setting bit
1 : Connected non-removable device under DnPort2
0 : No non-removable device under DnPort2
Normal stage : LED2, when under 3-wire mode, It is
the LED2 signal for 3-wire mode, not used under 1-
wire mode
1 : light on LED2 for DnPort 2 when 4-wire mode
0 : light off LED2 for DnPort 2 when 4-wire mode
O/PD Strapping stage : DnPort1 non-removable setting bit
1 : Connected non-removable device under DnPort1
0 : No non-removable device under DnPort1
Normal stage : LED1, when under 3-wire mode, It is
the LED1 signal for 3-wire mode, It is also the LED1
signal under 1-wire mode
1 : light on LED1 for DnPort 1 when 4-wire mode
0 : light off LED1 for DnPort 1 when 4-wire mode
I/PU
I/PU
I/PU
I/PU
Over Current indicator for downstream port 4
Over Current indicator for downstream port 3
Over Current indicator for downstream port 2
Over Current indicator for downstream port 1
56 LED3
55 LED2
54 LED1
53
52
51
50
48
OC4
OC3
OC2
OC1
PwrEn4 O/PD Strapping stage : gang/individual mode setting
0 : gang mode enabled (default)
1 : individual mode enabled
Normal stage : power enable output for downstream
port 4
1 : output power enable as high level
0 : output power enable as low level
7
49 PwrEn3 O/PD Strapping stage : BC1.2 Charger enable
0 : enable BC1.2 Charger function
1 : disable BC1.2 Charger function
Normal stage : power enable output for downstream
port 3
1 : output power enable as high level
0 : output power enable as low level
O/PD Strapping stage : dummy1(Reserved for later use)
Normal stage :
Normal stage : power enable output for downstream
port 2
1 : output power enable as high level
0 : output power enable as low level
O/PD Strapping stage : dummy0(Reserved for later use)
Normal stage : power enable output for downstream
port 1
1 : output power enable as high level
0 : output power enable as low level
46 PwrEn2
47 PwrEn1
注解:
O Output I Input
B Bi-directional P Power / Ground
A Analog PU Internal pull up PD Internal pull down
电器特性
极限参数
极限参数
Symbol
Ts
Tj
VDD50
VDD33
VDD11
Vin
Vout
Pd
Parameter
Storage Temperature
Junction Temperature
5V Input Voltage
3.3V LDO Output Voltage
1.1V DCDC Output Voltage
Input Voltage at I/O pins
Output Voltage at I/O pins
Power Dissipation
Min Max Unit Note
-55 150 ℃
-40 125 ℃
LDO : -0.5 ~ 5.5
-0.3 5.5 V DCDC : -0.3 ~ 6.0
U2/U3 : -0.66 ~ 3.96
-0.5 3.96 V IO : -0.5 ~ 3.8
U2/U3 : -0.22 ~ 1.32
-0.22 1.32 V IO : -0.5 ~ 1.8
-0.5 3.8 V GPIO PIN
-0.5 3.8 V GPIO PIN
--- 1 W
8
Vesd
I
latch
Electrostatic Discharge
Latch Up Current
-
2000 2000 V
--- 100 mA
HBM 1C Level
推荐工作环境
推荐工作环境
Symbol
Ta
VDD50
VDD33
VDD11
Parameter
Operating Ambient Temperature
5V Input Voltage for LDO and DCDC
3.3V LDO Output Voltage
1.1V DCDC Output Voltage
Min Typ Max
85
5.5
3.63
1.21
Unit
℃
V
V
V
-40
4.5 5
2.97 3.3
0.99 1.1
工作电气特性
工作电气特性
Symbol
VDD_IO
VDD_CORE
V
IL
V
IH
V
oL
V
OH
I
oL
I
OH
I
L
I
OZ
R
PU
R
PD
Parameter
Digital Input IO Voltage
Digital Input Core Voltage
Digital IO Input Low Voltage
Digital IO Input High Voltage
Digital IO Output Low Voltage
Digital IO Output High Voltage
Digital Low Level Output Current
Digital High Level Output Current
Input Leakage Current
Tri-State Output Leakage Current
Internal Pull-up Resistor
Internal Pull-down Resistor
Min Typ Max Unit
2.97 3.3 3.63 V
0.99 1.1 1.21 V
-0.3 0 0.8 V
2 3.3 3.63 V
--- 0 0.4
2.4 3.3 3.63
--- 12 ---
--- 12 ---
-10 --- 10
-10 --- 10
27 40 64
30 46
V
V
mA
mA
uA
uA
KΩ
80 KΩ
注:SL6340符合通用串行总线规范2.0版的直流特性。
SL6340符合通用串行总线规范3.0版的直流特性。
9
系统时钟
系统时钟
Symbol
F
clk
R
f
C1, C2
ESR
Parameter
Clock Frequency
Feedback Resistor
Load Capacitance
Max equivalent series resistance
Min Typ Max Unit
ppm
MΩ
pF
Ω
-20 24M 20
--- 1 ---
--- 12~15 ---
--- 40 ---
复用管脚功能说明
SL6340部分管脚复用使用,情况如下:
Pin Normal
9
11
62
60
58
56
55
54
48
PwrMode
DBG_TXD
SPI_SC
SPI_MOSI
LED4
LED3
LED2
LED1
PwrEN4
Strapping
PwrMode
AcaDock_n
McuEnable
Mcu_spi_iic_sel
DP4_NonRemovable
DP3_NonRemovable
DP2_NonRemovable
DP1_NonRemovable
GangMode_n
Default
value
1
1
1
0
0
0
0
0
0
功能说明
0:Set Hub to BusPower Mode
1:Set Hub to SelfPower Mode
0:Enable ACA Dock mode
1:Disable ACA Dock Mode
0:Disable Internal Mcu
1:Enable Internal Mcu
1 : iic eeprom selected
0 : spi flash selected
0 : Disable DP4 Non Removable
1 : Enable DP4 Non Removable
0 : Disable DP3 Non Removable
1 : Enable DP3 Non Removable
0 : Disable DP2 Non Removable
1 : Enable DP2 Non Removable
0 : Disable DP1 Non Removable
1 : Enable DP1 Non Removable
0:OverCurrent with gang mode
1:OverCurrent with individual
mode
0:Enable BC1.2 Function
1:Disable BC1.2 Function
Not used
Not used
49
46
47
PwrEN3
PwrEn2
PwrEn1
ChargerEnable_n
Dummy1
Dummy0
0
0
0
注:具体管脚复用配置资料以及方法见完整版Datasheet
10
封装外形图
俯视图
侧视图
底部视图
11
2024年9月9日发(作者:功鸿志)
深圳市和芯润德科技有限公司
USB3.2 Gen1X1 4口集线器芯片
SL6340
简要数据手册
V1.1
2023.09.25
1
USB3.2 Gen1X1接口4口集线器控制器集成电路
概述
SL6340是一款USB3.2 Gen1X1接口的4口HUB控制器芯片,片上集成32
位微处理器,它具有低功耗、高性能、可配置等特点;芯片集成USB3.0高速物
理层收发器和USB2.0高速物理层收发器,使得芯片可以完美支持超高速、高速
和低速USB上下行设备连接;芯片集成度高,内部集成5V转3.3V和5V转1.1V
DCDC,极大的精简了外围电路。
SL6340支持符合USB IF规范的BC1.2快充协议,他可以为苹果、三星设备
提供最高1.5A的充电电流。
SL6340支持通过外挂SPI-flash/EEPROM配置设备信息,本版本SL6340芯片
必须配置SPI-FLASH使用,我司提供配置程序/或完成程序配置的SPI-FLASH。
功能特点
SL6340符合USB3.2 V1.0 规范。
SL6340向下兼容支持USB2.0、USB1.1规范
SL6340上行口支持超高速SS、高速HS、低速FS设备
SL6340下行口支持超高速SS、高速HS、全速FS、低速LS设备
SL6340S支持一路控制和一路中断
SL6340集线器芯片上行口USB和下行口USB端口都支持BC1.2快充协议
支持BC1.2快充协议、支持SDP(Standard Downstream Port), CDP,DCP, and ACA-
Dock
SL6340支持数据传输同时为移动设备充电(BC1.2)
SL6340下行口USB可以从标准的USB口切换为快充口或者专用充电端口
SL6340上游非标准USB HOST/OTG,依然可以支持BC1.2快充协议,此时需要
电源适配器行供电.
SL6340集成USB3.2 Gen1X1 超高速收发器,集成USB2.0高速收发器
SL6340下行端口设备支持过流保护,支持USB2.0挂起和恢复。
SL6340支持下行端口(单口/多口)电源使能
SL6340支持通过外挂SPI-flash/EEPROM配置设备信息
支持通过SPI-Flash/EEPROM固件升级
支持通过SPI-Flash/EEPROM配置BC1.2充电功能
支持通过SPI-Flash/EEPROM自定义设备VID/PID
支持通过SPI-Flash/EEPROM配置LED闪灯方式等
SL6340支持自供电模式,同时也总线供电模式
SL6340支持USB3.0 PHY收发自适应
SL6340支持单个24M晶体/振荡器时钟输入,
SL6340上行端口集成1.5KΩ上拉、下游端口集成15KΩ下拉电阻器
SL6340才有QFN80 8X8扁平封装
2
产品应用
独立的3.0 HUB集线器、type-c扩展坞、dock底座等
服务器、PC、笔记本等USB3.0扩展
商业显示、会议平板等嵌入式系统USB3.0接口扩展
工业控制USB3.0扩展
车载HUB
USB挂式充电墙
其他消费类电子
芯片内部功能框图
SL6340功能框图
3
管脚排列
SL6340 管脚排列图
管脚定义
1.1
Pin Description
QFN 80 Pin name Type Description
Table 4.2 –1 Power and GND
41, 64 VIN_5V I 5v Adapter Input or Vbus input
40 VIN_33V I 3.3v Power Input
63 VOUT_33V O 3.3v power output
42 VOUT_11V O
NC,should be floating
17,23,29,35,67,78 AVDD_33V I 3.3v Analog power
4
18,24,30,36,68,79 AVDD_11V I
5,61
13,45
14,39,43,44
81
VDD_33V
VDD_11V
VSS
EPAD
I
I
-
P
1.1v Analog power
3.3v Digital power
1.1v Digital power
GND
EPAD
Table 4.2 – 2 USB2.0 Interface
71
72
73
74
75
76
80
1
2
3
77
UP_DP
UP_DM
DN1_DP
DN1_DM
DN2_DP
DN2_DM
DN3_DP
DN3_DM
DN4_DP
DN4_DM
RREF
B
B
B
B
B
B
B
B
B
B
I
USB2.0 DP for Upstream Port
USB2.0 DM for Upstream Port
USB2.0 DP for Downstream Port 1
USB2.0 DM for Downstream Port1
USB2.0 DP for Downstream Port 2
USB2.0 DM for Downstream Port2
USB2.0 DP for Downstream Port 3
USB2.0 DM for Downstream Port3
USB2.0 DP for Downstream Port 4
USB2.0 DM for Downstream Port4
USB2.0 Reference Input, connect to 200ohm 1%
Resister
Table 4.2 – 3 USB3.2 Interface
65
66
69
70
15
16
19
20
21
22
25
UP_RXP
UP_RXN
UP_TXP
UP_TXN
DN1_RXP
DN1_RXN
DN1_TXP
DN1_TXN
DN2_RXP
DN2_RXN
DN2_TXP
I
I
O
O
I
I
O
O
I
I
O
USB3.0 Differential Data Receiver Rx+ for Upstream
Port
USB3.0 Differential Data Receiver Rx- for Upstream
Port
USB3.0 Differential Data Transmitter Tx+ for
Upstream Port
USB3.0 Differential Data Transmitter Tx- for
Upstream Port
USB3.0 Differential Data Receiver Rx+ for
Downstream Port1
USB3.0 Differential Data Receiver Rx- for
Downstream Port1
USB3.0 Differential Data Receiver Tx+ for
Downstream Port1
USB3.0 Differential Data Receiver Tx- for
Downstream Port1
USB3.0 Differential Data Receiver Rx+ for
Downstream Port2
USB3.0 Differential Data Receiver Rx- for
Downstream Port2
USB3.0 Differential Data Receiver Tx+ for
Downstream Port2
5
26
27
28
31
32
33
34
37
38
DN2_TXN
DN3_RXP
DN3_RXN
DN3_TXP
DN3_TXN
DN4_RXP
DN4_RXN
DN4_TXP
DN4_TXN
O
I
I
O
O
I
I
O
O
USB3.0 Differential Data Receiver Tx- for
Downstream Port2
USB3.0 Differential Data Receiver Rx+ for
Downstream Port3
USB3.0 Differential Data Receiver Rx- for
Downstream Port3
USB3.0 Differential Data Receiver Tx+ for
Downstream Port3
USB3.0 Differential Data Receiver Tx- for
Downstream Port3
USB3.0 Differential Data Receiver Rx+ for
Downstream Port4
USB3.0 Differential Data Receiver Rx- for
Downstream Port4
USB3.0 Differential Data Receiver Tx+ for
Downstream Port4
USB3.0 Differential Data Receiver Tx- for
Downstream Port4
Table 4.2 – 4 Clock, Reset and Tes
6
7
4
8
OSC_XI
OSC_XO
TE
RSTN
I
O
I
I
Crystal/OSC Clock input
Crystal Clock output
Test Enable
Reset input, Active Low
Table 4.2 – 5 Misc & Digital Interfac
e
9 PwrMode B/PU Power Mode Selection
0 : Set Hub to BusPower Mode
1 : Set Hub to SelfPower Mode
It is also the power mode indicator
B/PU 0 : DownStream Port goto DCP mode
1 : DownStream Port under normal mode (SDP)
O/PU Strapping stage : ACA_Dock mode enable
0 : enable ACA DOCK mode for Downstream Port
1 : disable ACA DOCK mode for Downstream Port
Normal stage : Debug uart tx Pin
I/PU Debug uart Rx
O/PU Strapping stage : Mcu Enable
1 : enable internal Mcu
0 : disable internal Mcu
Normal stage : spi chip selection signal
B/PU Spi clock signal
O/PD Strapping stage : mcu IIC or spi selection
1 : iic eeprom
6
10
11
DCP_En
DBG_TXD
12
62
DBG_RXD
SPI_SC
59
60
SPI_CLK
SPI_MOSI
0 : spi flash (default)
Normal stage : spi Master Output Slave Input signal
57
58
SPI_MISO
LED4
I/PU Spi Master Input Slave Output signal
O/PD Strapping stage : DnPort4 non-removable setting bit
1 : Connected non-removable device under DnPort4
0 : No non-removable device under DnPort4
Normal stage : LED4, not used under 3-wire or 1-wire
mode
1 : light on LED4 for DnPort 4 when 4-wire mode
0 : light off LED4 for DnPort 4 when 4-wire mode
O/PD Strapping stage : DnPort3 non-removable setting bit
1 : Connected non-removable device under DnPort3
0 : No non-removable device under DnPort3
Normal stage : LED3, when under 3-wire mode, It is
the LED_DRV signal, not used under 1-wire mode
1 : light on LED3 for DnPort 3 when 4-wire mode
0 : light off LED3 for DnPort 3 when 4-wire mode
O/PD Strapping stage : DnPort2 non-removable setting bit
1 : Connected non-removable device under DnPort2
0 : No non-removable device under DnPort2
Normal stage : LED2, when under 3-wire mode, It is
the LED2 signal for 3-wire mode, not used under 1-
wire mode
1 : light on LED2 for DnPort 2 when 4-wire mode
0 : light off LED2 for DnPort 2 when 4-wire mode
O/PD Strapping stage : DnPort1 non-removable setting bit
1 : Connected non-removable device under DnPort1
0 : No non-removable device under DnPort1
Normal stage : LED1, when under 3-wire mode, It is
the LED1 signal for 3-wire mode, It is also the LED1
signal under 1-wire mode
1 : light on LED1 for DnPort 1 when 4-wire mode
0 : light off LED1 for DnPort 1 when 4-wire mode
I/PU
I/PU
I/PU
I/PU
Over Current indicator for downstream port 4
Over Current indicator for downstream port 3
Over Current indicator for downstream port 2
Over Current indicator for downstream port 1
56 LED3
55 LED2
54 LED1
53
52
51
50
48
OC4
OC3
OC2
OC1
PwrEn4 O/PD Strapping stage : gang/individual mode setting
0 : gang mode enabled (default)
1 : individual mode enabled
Normal stage : power enable output for downstream
port 4
1 : output power enable as high level
0 : output power enable as low level
7
49 PwrEn3 O/PD Strapping stage : BC1.2 Charger enable
0 : enable BC1.2 Charger function
1 : disable BC1.2 Charger function
Normal stage : power enable output for downstream
port 3
1 : output power enable as high level
0 : output power enable as low level
O/PD Strapping stage : dummy1(Reserved for later use)
Normal stage :
Normal stage : power enable output for downstream
port 2
1 : output power enable as high level
0 : output power enable as low level
O/PD Strapping stage : dummy0(Reserved for later use)
Normal stage : power enable output for downstream
port 1
1 : output power enable as high level
0 : output power enable as low level
46 PwrEn2
47 PwrEn1
注解:
O Output I Input
B Bi-directional P Power / Ground
A Analog PU Internal pull up PD Internal pull down
电器特性
极限参数
极限参数
Symbol
Ts
Tj
VDD50
VDD33
VDD11
Vin
Vout
Pd
Parameter
Storage Temperature
Junction Temperature
5V Input Voltage
3.3V LDO Output Voltage
1.1V DCDC Output Voltage
Input Voltage at I/O pins
Output Voltage at I/O pins
Power Dissipation
Min Max Unit Note
-55 150 ℃
-40 125 ℃
LDO : -0.5 ~ 5.5
-0.3 5.5 V DCDC : -0.3 ~ 6.0
U2/U3 : -0.66 ~ 3.96
-0.5 3.96 V IO : -0.5 ~ 3.8
U2/U3 : -0.22 ~ 1.32
-0.22 1.32 V IO : -0.5 ~ 1.8
-0.5 3.8 V GPIO PIN
-0.5 3.8 V GPIO PIN
--- 1 W
8
Vesd
I
latch
Electrostatic Discharge
Latch Up Current
-
2000 2000 V
--- 100 mA
HBM 1C Level
推荐工作环境
推荐工作环境
Symbol
Ta
VDD50
VDD33
VDD11
Parameter
Operating Ambient Temperature
5V Input Voltage for LDO and DCDC
3.3V LDO Output Voltage
1.1V DCDC Output Voltage
Min Typ Max
85
5.5
3.63
1.21
Unit
℃
V
V
V
-40
4.5 5
2.97 3.3
0.99 1.1
工作电气特性
工作电气特性
Symbol
VDD_IO
VDD_CORE
V
IL
V
IH
V
oL
V
OH
I
oL
I
OH
I
L
I
OZ
R
PU
R
PD
Parameter
Digital Input IO Voltage
Digital Input Core Voltage
Digital IO Input Low Voltage
Digital IO Input High Voltage
Digital IO Output Low Voltage
Digital IO Output High Voltage
Digital Low Level Output Current
Digital High Level Output Current
Input Leakage Current
Tri-State Output Leakage Current
Internal Pull-up Resistor
Internal Pull-down Resistor
Min Typ Max Unit
2.97 3.3 3.63 V
0.99 1.1 1.21 V
-0.3 0 0.8 V
2 3.3 3.63 V
--- 0 0.4
2.4 3.3 3.63
--- 12 ---
--- 12 ---
-10 --- 10
-10 --- 10
27 40 64
30 46
V
V
mA
mA
uA
uA
KΩ
80 KΩ
注:SL6340符合通用串行总线规范2.0版的直流特性。
SL6340符合通用串行总线规范3.0版的直流特性。
9
系统时钟
系统时钟
Symbol
F
clk
R
f
C1, C2
ESR
Parameter
Clock Frequency
Feedback Resistor
Load Capacitance
Max equivalent series resistance
Min Typ Max Unit
ppm
MΩ
pF
Ω
-20 24M 20
--- 1 ---
--- 12~15 ---
--- 40 ---
复用管脚功能说明
SL6340部分管脚复用使用,情况如下:
Pin Normal
9
11
62
60
58
56
55
54
48
PwrMode
DBG_TXD
SPI_SC
SPI_MOSI
LED4
LED3
LED2
LED1
PwrEN4
Strapping
PwrMode
AcaDock_n
McuEnable
Mcu_spi_iic_sel
DP4_NonRemovable
DP3_NonRemovable
DP2_NonRemovable
DP1_NonRemovable
GangMode_n
Default
value
1
1
1
0
0
0
0
0
0
功能说明
0:Set Hub to BusPower Mode
1:Set Hub to SelfPower Mode
0:Enable ACA Dock mode
1:Disable ACA Dock Mode
0:Disable Internal Mcu
1:Enable Internal Mcu
1 : iic eeprom selected
0 : spi flash selected
0 : Disable DP4 Non Removable
1 : Enable DP4 Non Removable
0 : Disable DP3 Non Removable
1 : Enable DP3 Non Removable
0 : Disable DP2 Non Removable
1 : Enable DP2 Non Removable
0 : Disable DP1 Non Removable
1 : Enable DP1 Non Removable
0:OverCurrent with gang mode
1:OverCurrent with individual
mode
0:Enable BC1.2 Function
1:Disable BC1.2 Function
Not used
Not used
49
46
47
PwrEN3
PwrEn2
PwrEn1
ChargerEnable_n
Dummy1
Dummy0
0
0
0
注:具体管脚复用配置资料以及方法见完整版Datasheet
10
封装外形图
俯视图
侧视图
底部视图
11