2024年9月17日发(作者：仇鸿运)
查询CXK77B3610GB供应商
CXK77B3610GB
-6/7
High Speed Bi-CMOS Synchronous Static RAM
Description
The CXK77B3610GB-6/7 is a high speed 1M bit
Bi-CMOS synchronous statis RAM organized as
32768 words by 36 bits. This SRAM integrates input
registers, high speed SRAM and write buffer onto a
single monolithic IC and features the delayed write
system to reduce the dead cycles.
Features
•Fast cycle time(Cycle)(Frequency)
CXK77B3610GB-66ns166MHz
CXK77B3610GB-77ns142MHz
•Inputs and outputs are LVTTL/LVCMOS compatible
•Single 3.3V power supply: 3.3V ±0.15V
•Byte-write possible
•OE asynchronization
•JTAG test circuit
•Package 119TBGA
•3 kinds of synchronous operation mode
Register-Register mode (R-R mode)
Register-Flow Thru mode (R-F mode)
Register-Latch mode (R-L mode)
Function
32768 word ×36bit High Speed Bi-CMOS Synchronous SRAM
Structure
Silicon gate Bi-CMOS IC
Preliminary
119 pin BGA (Plastic)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1–
PE95128-PS
CXK77B3610GB
Block Diagram
15
A0 to 14
Input
Reg.
2:1
Mux
Add.
Dout
Write
Store
Reg.
32K × 36
Din
Write
pulse
2:1
Mux
Output
latch
DQ
Reg.
Read
Comp.
S
Reg.
W
Reg.
Salf
Time
Write
Logic
4
BW
a to d
Reg.
K/K
Output
Clock
M1
M2
Mode
Control
G
– 2–
CXK77B3610GB
Pin Configuration (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DD
Q
NC
NC
DQc
DQc
V
DD
Q
DQc
DQc
V
DD
Q
DQd
DQd
V
DD
Q
DQd
DQd
NC
NC
V
DD
Q
2
A
NC
A
DQc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DQd
A
NC
TME
3
A
NC
A
V
SS
V
SS
V
SS
BWc
V
SS
NC
V
SS
BWd
V
SS
V
SS
V
SS
M1
A
TDI
4
NC
NC
V
DD
NC
S
G
NC
NC
V
DD
K
K
W
A
A
V
DD
A
TCK
5
A
NC
A
V
SS
V
SS
V
SS
BWb
V
SS
NC
V
SS
BWa
V
SS
V
SS
V
SS
M2
A
TDO
6
A
NC
A
DQb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DQa
A
NC
NC
7
V
DD
Q
NC
NC
DQb
DQb
V
DD
Q
DQb
DQb
V
DD
Q
DQa
DQa
V
DD
Q
DQa
DQa
NC
ZZ
V
DD
Q
Pin Description
Symbol
A
DQx
K
K
W
BWx
S
Description
Address Input
Data I/O in byte
a to d
Positive Clock
Negative Clock
Write Enable
Byte Write Enable
(a to d)
Chip Select
Symbol
G
ZZ
TCK
TMS
TDI
TDO
V
DD
Description
Asyn Output Enable
Sleep Mode Select
JTAG Clock
JTAG Mode Select
JTAG Data In
JTAG Data Out
+3.3V power supply
Symbol
V
DD
Q
V
SS
M1, M2
NC
Description
Output power supply
Ground
Mode Select
No Connect
– 3–
CXK77B3610GB
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
Output voltage
Allowable power dissipation
operating temperature
Strorage temperature
Soldering temperature · time
Symbol
V
CC
V
IN
V
O
P
D
Topr
Tstg
Tsolder
Rating
–0.5 to +4.6
(Ta = 25°C, GND = 0V)
Unit
V
V
V
W
°C
°C
°C · sec
–0.5 to V
CC
+0.5 (4.6V max.)
–0.5 to V
CC
+0.5 (4.6V max.)
TBD
0 to 70
–55 to +150
235 · 10
Truth Table
ZZ
H
L
L
L
L
L
L
S (tn)
X
H
L
L
L
L
L
W (tn)BWx (tn)
X
X
H
H
L
L
L
X
X
X
X
L
X
H
G
X
X
H
L
X
X
X
Mode
Sleep mode, Power down
Deselect
Read
Read
Write all bytes (bits 0 to 35)
Write bytes with BWx = L
Aborted Write
DQ0 to 35DQ0 to 35V
DD
(tn)(tn+1)Current
Hi-Z
X
Hi-Z
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Q (tn)
D (tn)
D (tn)
X
I
SB
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
DC Recommended Operating Conditions
Item
Supply voltage
Output supply voltage
Input high voltage
Input low voltage
Differential clock input signal
Differential clock input
common mode
Symbol
V
DD
V
DD
Q
V
IH
V
IL
∆V
K
V
K
, COM
Min.
3.15
3.15
2.0
–0.3
0.4
1.2
(Ta = 25°C, GND = 0V)
Typ.
3.3
3.3
—
—
0.8
2.0
Max.
3.45
3.45
V
DD
+0.3
0.8
—
2.2
Unit
V
V
V
V
V
V
– 4–
CXK77B3610GB
Mode Select Truth Table
Item
Register-Resister mode
Register-Flow Thru mode
Register-Latch mode
M1
L
L
H
M2
H
L
L
Electrical Characteristics
•DC and operating characteristics
Item
Input leakage current
Output leakage current
Operating power supply
current
Standby current
Output high voltage
Output low voltage
∗
V
CC
= 3.3V, Ta = 25°C
Symbol
I
LI
I
LO
(V
CC
= 3.3V ±10%, GND = 0V, Ta = 0 to 70°C)
Test conditions
V
IN
= GND to V
CC
V
O
= GND to V
CC
G = V
IH
Cycle = min.
Duty = 100%
I
OUT
= 0mA
ZZ ≥V
IH
I
OH
= –2.0mA
I
OL
= 2.0mA
2.4
—
—
—
Min.
–1
–10
Typ.
∗
—
—
Max.
1
10
Unit
µA
µA
I
CC
I
SB
V
OH
V
OL
—
—TBD
20
—
0.4
mA
mA
V
V
•I/O capacitance
Item
Input capacitance
Clock input capacitance
Output capacitance
Symbol
C
IN
C
CLK
C
OUT
Test conditions
V
IN
= 0V
V
IN
= 0V
V
OUT
= 0V
(Ta = 25°C, f = 1MHz)
Min.
—
—
—
Max.
5
8
8
Unit
pF
pF
pF
Note)These parameters are sampled and are not 100% tested.
– 5–
CXK77B3610GB
•AC Electrical Characteristics
Item
Address access (except Register-Register mode)
Clock period
Clock pulse high
Clock pulse low
Setup time
Hold time
Clock high to output (R-R mode)
Clock high to output (R-F mode, R-L mode)
Clock low to output (R-L mode)
Write cycle clock high to following Read cycle output
(R-F mode, R-L mode)
Clock high to output high impedance (S deselect cycle)
Write cycle clock high to output high impedance
(R-F mode, R-L mode)
Clock high to output low impedance
(R-R mode)
Clock high to output low impedance
(R-F mode)
Clock low to output low impedance (R-L mode)
Output enable to output valid (G)
Output enable to output in low Z (G)
Output disable to output in high Z (G)
Symbol
-6
Min.
—
6
2
2
0.5
1
1.5
∗
2
—
1.5
∗
2
Max.
9
—
—
—
—
—
3
6
3
15
1.5
1.5
1.5
2
1.5
—
1
—
3
3
—
—
—
3
—
3
1.5
1.5
1.5
2
1.5
—
1
—
Min.
—
7
3
3
1
1
1.5
∗
2
—
1.5
∗
2
-7
Max.
10
—
—
—
—
—
3.5
7
3.5
17
3.5
3.5
—
—
—
3.5
—
3.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AA
t
KP
t
KH
t
KL
t
S
t
H
t
KQ
t
KQ1
t
KQ2
t
KQ3
t
HZ
∗
2
t
WHZ
∗
2
t
LZ
∗
2
t
LZ1
∗
2
t
LZ2
∗
2
t
OE
t
OLZ
∗
2
t
OHZ
∗
2
∗
1
All parameters are specified over the range 0 to 70°C.
∗
2
These parameters are sampled and are not 100% tested.
AC characteristics
•AC test conditions
Item
Input pulse high level
Input pulse low level
Input rise & fall time
Input reference level
Clock input reference level
Clock input differential signal
Clock input rise & fall time
Output reference level
Output load conditions
(V
DD
= 3.3V ±0.15V, Ta = 0 to 70°C)
Conditions
V
IH
= 2.4V
V
IL
= 0.4V
1V/ns
2.0/0.8V
K/K cross;
C/C cross
0.8V
1V/ns
1.4V
Fig. 1
– 6–
∗
1
Including scope and jig capacitance.
∗
2
For
t
LZ
,
t
HZ
.
Fig. 1.
I/O
50Ω
50Ω
1.4V
I/O
5pF
∗
1
1178Ω
Output Load (1)
Output Load (2)
∗
2
3.3V
868Ω
CXK77B3610GB
Register-Register mode
Timing waveform of READ CYCLE
K
K
t
KP
t
S
A0 to 14
n
t
H
n + 1
t
KH
t
KL
n + 2
W
t
S
t
H
t
S
S
t
KQ
t
KQ
G
t
LZ
DQ0 to 35
Qn – 2
t
OHZ
t
OLZ
t
HZ
Qn – 1Qn
t
OE
t
H
Timing waveform of WRITE CYCLE
K
K
t
S
A0 to 14
n
t
H
n + 1n + 2
S
W/BWx
G
DQ0 to 35
Dn – 1DnDn + 1
– 7–
CXK77B3610GB
Register-Register mode
Timing waveform of READ-WRITE-READ CYCLE I(S controlled)
K
K
A0 to 14
NN + 2N + 3N + 4N + 5
S
W/BWx
G = V
IL
DQ0 to 35
Qn – 1
Reed N
Deselect
(Hi-Z)
Qn
Write N + 2
Dn + 2
Reed N + 3
Qn + 3
Timing waveform of READ-WRITE-READ CYCLE II(G controlled)
K
K
A0 to 14
NN + 2N + 3N + 4N + 5
S = V
IL
W/BWx
G
DQ0 to 35
Qn – 1
Qn
Dn + 2Qn + 3
Reed N
Hi-Z;
Write N + 2
Reed N + 3
– 8–
CXK77B3610GB
Register-Latch mode
Timing waveform of READ CYCLE
K
K
t
KP
t
S
t
H
n + 1
t
KH
t
KL
A0 to 14
nn + 2
W
t
S
t
H
t
S
S
t
KQ2
t
KQ1
t
KQ2
t
OE
t
H
t
S
t
H
t
KQ1
t
AA
G
t
LZ2
t
OHZ
t
OLZ
t
HZ
DQ0 to 35
Qn – 1
QnQn + 1
Timing waveform of WRITE CYCLE
K
K
t
S
A0 to 14
n
t
KP
t
H
n + 1n + 2
S
W/BWx
G
DQ0 to 35
Dn – 1DnDn + 1
– 9–
CXK77B3610GB
Register-Latch mode
Timing waveform of READ-WRITE-READ CYCLE
K
K
A0 to 14
S
W/BWx
G = V
IL
DQ0 to 35
t
KP
t
KP
t
KP
t
KP
NN + 1N + 2N + 3N + 4N + 5
t
S
t
H
t
t
H
S
t
H
t
S
t
KQ2
t
KQ1
t
KQ2
t
AA
t
KQ1
t
WHZ
t
S
t
H
t
KQ2
t
LZ2
QnDn + 1
Qn + 2Qn + 4
t
KQ3
t
LZ1
Reed NWrite N + 1Reed N + 2
Deselect
(Hi-Z)
Reed N + 4
– 10–
CXK77B3610GB
Register-Flow Thru mode
Timing waveform of READ CYCLE
K
K
t
S
A0 to 14
n
t
H
t
KP
t
KH
t
KL
n + 1n + 2
W
t
S
t
H
t
S
S
t
KQ1
t
KQ1
G
t
AA
t
OE
t
H
t
S
t
H
t
LZ1
DQ0 to 35
Qn – 1
t
OHZ
Qn
t
OLZ
t
HZ
Qn + 1
Timing waveform of WRITE CYCLE
K
K
t
S
A0 to 14
n
t
H
n + 1n + 2
S
W/BWx
G
DQ0 to 35
Dn – 1DnDn + 1
– 11–
CXK77B3610GB
Register-Flow Thru mode
Timing waveform of READ-WRITE-READ CYCLE
K
K
A0 to 14
S
W/BWx
G = V
IL
DQ0 to 35
NN + 1N + 2N + 3N + 4N + 5
t
S
t
H
t
t
H
S
t
H
t
S
t
t
KQ1
AA
t
KO1
t
WHZ
t
S
t
H
t
KQ1
QnDn + 1Qn + 2Qn + 4
t
KQ3
t
LZ1
Reed NWrite N + 1Reed N + 2
Deselect
(Hi-Z)
Reed N + 4
– 12–
CXK77B3610GB
Test Mode Description
Fuctional Description
The CXK77B3610 provides JTAG boundary scan interface using IEEE std. 1149.1 protocol. The test mode is
intended to provided a mechanism for testing the interconnect between master (processor, controller, etc.),
SRAMs other components and print circuit board.
In conformance with IEEE std. 1149.1, the CXK77B3610 contains a TAP controller, Instruction register,
Boundary scan register and Bypass register.
Test Access Port (TAP)
4 pins as defined in Pin Description table are used to perform JTAG functions. TDI input pin is used to scan
test data serially into one of three registers (Instruction register, Boundary scan register and Bypass register).
TDO is output pin used to scan test data serially out. The TDI send the data into LSBof selected register and
the MSB of the selected register feeds the data to TDO. TMS input pin controls the state transition of 16 state
TAP controller as specified in IEEE std. 1149.1. Inputs on TDI, TMS are registered on the rising edge of TCK
clock and the output data on TDO is presented on the falling edge of TCK. TDO driver is in active state only
when TAP conroller is in Shift-IR state or in Shift-DR state.
TAP Controller
16 state controller is implemented as specified in IEEE std. 1149.1.
The controller enter reset state in one of three ways:
1. Power up
2. Apply logic 1 on TMS input pin on 5 consecutive TCK rising edges.
Instruction Resister (3 bits)
The JTAG Instruction resister is consisted of shift resister stage and parallel output latch. The register is 3 bits
wide and is encoded as follow:
Octal
0
1
2
3
4
5
6
7
MSB LSB
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Bypass
IDCODE. read device ID
Sample-Z. Sample Inputs and tri-state DQs
Bypass
Sample. Sample Inputs.
Private. Manufacturer use only.
Bypass
Bypass
Instruction
Bypass Register (1 bit)
The Bypass Register is one bit wide and is connected electrically between TDI and TDO and provides the
minimum length serial path between TDI and TDO.
– 13–
CXK77B3610GB
ID Registers (32 bits)
The ID Register are 32 bits wide and are listed as follow:
ID [0]
Sony ID
Part Number
Revision Number
ID [11:1]
ID [27:12]
ID [31:28]
1
0000 1110 001
0000 0000 0000 0000
xxxx
∗
1
∗
1
Please contact Sony Sales Department.
Boundary Scan Register (70 bits)
The Boundary Scan Registers are 70 bits wide and are listed as follow:
DQ
A
W, BWx
S, G
K, K, C, C
ZZ
Mode
Place Holder
36
15
5
2
4
1
2
5
K/K, C/C inputs are sampled through one differential stage and internal inverted to generate internal K/K, C/C
signals for scan registers. Place Holder are required for some NC pins to maintain 70 bits Scan Register for
different types of same family SRAM and for density upgrade. All Place Holder Registers are connected to V
SS
internally regardless of pin connection externally.
– 14–
CXK77B3610GB
Scan Order (Order by exit sequence)
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
—
—
3A
3C
2C
2A
2D
1D
2E
1E
2F
2G
1G
2H
1H
3G
—
4E
4G
4H
4M
3L
1K
2K
1L
2L
2M
1N
2N
1P
2P
3T
2R
4N
3R
V
SS
V
SS
A
A
A
A
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
/Wc
V
SS
/S
/C
C
/W
/Wd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
A
A
A
M1
V
SS
V
SS
A
A
A
A
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
/Wb
/G
K
/K
/Wa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
ZZ
A
A
A
A
M2
—
—
5A
5C
6C
6A
6D
7D
6E
7E
6F
6G
7G
6H
7H
5G
4F
4K
4L
5L
7K
6K
7L
6L
6M
7N
6N
7P
6P
7T
5T
6R
4T
4P
5R
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
– 15–
CXK77B3610GB
Package OutlineUnit: mm
119 TERMINAL BGA (PLASTIC)
14.0
11.5
B
A
0.6 ± 0.1
X
C
3.19
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
7.62
1.27
0
.
8
4
1
9
.
5
C
1
.
0
× 4
0.10
1 2 3 4 5 6 7
3
-
0.6 ± 0.1
1.5
φ0.75 ± 0.15
φ0.3
φ0.1
2
0
.
3
2
CAB
EPOXY RESIN
COPPER-CLAD LAMINATE
SOLDER
0.8g
2
2
.
0
0.35
1
.
2
7
C
SONY CODE
EIAJ CODE
JEDEC CODE
C
4
-
6
0
.
DETAIL X
BGA-119P-01
C
5
1
.
0.15C
PACKAGE STRUCTURE
PACKAGE MATERIAL
BOARD MATERIAL
TERMINAL MATERIAL
PACKAGE WEIGHT
– 16–
2024年9月17日发(作者：仇鸿运)
查询CXK77B3610GB供应商
CXK77B3610GB
-6/7
High Speed Bi-CMOS Synchronous Static RAM
Description
The CXK77B3610GB-6/7 is a high speed 1M bit
Bi-CMOS synchronous statis RAM organized as
32768 words by 36 bits. This SRAM integrates input
registers, high speed SRAM and write buffer onto a
single monolithic IC and features the delayed write
system to reduce the dead cycles.
Features
•Fast cycle time(Cycle)(Frequency)
CXK77B3610GB-66ns166MHz
CXK77B3610GB-77ns142MHz
•Inputs and outputs are LVTTL/LVCMOS compatible
•Single 3.3V power supply: 3.3V ±0.15V
•Byte-write possible
•OE asynchronization
•JTAG test circuit
•Package 119TBGA
•3 kinds of synchronous operation mode
Register-Register mode (R-R mode)
Register-Flow Thru mode (R-F mode)
Register-Latch mode (R-L mode)
Function
32768 word ×36bit High Speed Bi-CMOS Synchronous SRAM
Structure
Silicon gate Bi-CMOS IC
Preliminary
119 pin BGA (Plastic)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1–
PE95128-PS
CXK77B3610GB
Block Diagram
15
A0 to 14
Input
Reg.
2:1
Mux
Add.
Dout
Write
Store
Reg.
32K × 36
Din
Write
pulse
2:1
Mux
Output
latch
DQ
Reg.
Read
Comp.
S
Reg.
W
Reg.
Salf
Time
Write
Logic
4
BW
a to d
Reg.
K/K
Output
Clock
M1
M2
Mode
Control
G
– 2–
CXK77B3610GB
Pin Configuration (Top View)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DD
Q
NC
NC
DQc
DQc
V
DD
Q
DQc
DQc
V
DD
Q
DQd
DQd
V
DD
Q
DQd
DQd
NC
NC
V
DD
Q
2
A
NC
A
DQc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
DQd
A
NC
TME
3
A
NC
A
V
SS
V
SS
V
SS
BWc
V
SS
NC
V
SS
BWd
V
SS
V
SS
V
SS
M1
A
TDI
4
NC
NC
V
DD
NC
S
G
NC
NC
V
DD
K
K
W
A
A
V
DD
A
TCK
5
A
NC
A
V
SS
V
SS
V
SS
BWb
V
SS
NC
V
SS
BWa
V
SS
V
SS
V
SS
M2
A
TDO
6
A
NC
A
DQb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
DQa
A
NC
NC
7
V
DD
Q
NC
NC
DQb
DQb
V
DD
Q
DQb
DQb
V
DD
Q
DQa
DQa
V
DD
Q
DQa
DQa
NC
ZZ
V
DD
Q
Pin Description
Symbol
A
DQx
K
K
W
BWx
S
Description
Address Input
Data I/O in byte
a to d
Positive Clock
Negative Clock
Write Enable
Byte Write Enable
(a to d)
Chip Select
Symbol
G
ZZ
TCK
TMS
TDI
TDO
V
DD
Description
Asyn Output Enable
Sleep Mode Select
JTAG Clock
JTAG Mode Select
JTAG Data In
JTAG Data Out
+3.3V power supply
Symbol
V
DD
Q
V
SS
M1, M2
NC
Description
Output power supply
Ground
Mode Select
No Connect
– 3–
CXK77B3610GB
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
Output voltage
Allowable power dissipation
operating temperature
Strorage temperature
Soldering temperature · time
Symbol
V
CC
V
IN
V
O
P
D
Topr
Tstg
Tsolder
Rating
–0.5 to +4.6
(Ta = 25°C, GND = 0V)
Unit
V
V
V
W
°C
°C
°C · sec
–0.5 to V
CC
+0.5 (4.6V max.)
–0.5 to V
CC
+0.5 (4.6V max.)
TBD
0 to 70
–55 to +150
235 · 10
Truth Table
ZZ
H
L
L
L
L
L
L
S (tn)
X
H
L
L
L
L
L
W (tn)BWx (tn)
X
X
H
H
L
L
L
X
X
X
X
L
X
H
G
X
X
H
L
X
X
X
Mode
Sleep mode, Power down
Deselect
Read
Read
Write all bytes (bits 0 to 35)
Write bytes with BWx = L
Aborted Write
DQ0 to 35DQ0 to 35V
DD
(tn)(tn+1)Current
Hi-Z
X
Hi-Z
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Q (tn)
D (tn)
D (tn)
X
I
SB
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
DC Recommended Operating Conditions
Item
Supply voltage
Output supply voltage
Input high voltage
Input low voltage
Differential clock input signal
Differential clock input
common mode
Symbol
V
DD
V
DD
Q
V
IH
V
IL
∆V
K
V
K
, COM
Min.
3.15
3.15
2.0
–0.3
0.4
1.2
(Ta = 25°C, GND = 0V)
Typ.
3.3
3.3
—
—
0.8
2.0
Max.
3.45
3.45
V
DD
+0.3
0.8
—
2.2
Unit
V
V
V
V
V
V
– 4–
CXK77B3610GB
Mode Select Truth Table
Item
Register-Resister mode
Register-Flow Thru mode
Register-Latch mode
M1
L
L
H
M2
H
L
L
Electrical Characteristics
•DC and operating characteristics
Item
Input leakage current
Output leakage current
Operating power supply
current
Standby current
Output high voltage
Output low voltage
∗
V
CC
= 3.3V, Ta = 25°C
Symbol
I
LI
I
LO
(V
CC
= 3.3V ±10%, GND = 0V, Ta = 0 to 70°C)
Test conditions
V
IN
= GND to V
CC
V
O
= GND to V
CC
G = V
IH
Cycle = min.
Duty = 100%
I
OUT
= 0mA
ZZ ≥V
IH
I
OH
= –2.0mA
I
OL
= 2.0mA
2.4
—
—
—
Min.
–1
–10
Typ.
∗
—
—
Max.
1
10
Unit
µA
µA
I
CC
I
SB
V
OH
V
OL
—
—TBD
20
—
0.4
mA
mA
V
V
•I/O capacitance
Item
Input capacitance
Clock input capacitance
Output capacitance
Symbol
C
IN
C
CLK
C
OUT
Test conditions
V
IN
= 0V
V
IN
= 0V
V
OUT
= 0V
(Ta = 25°C, f = 1MHz)
Min.
—
—
—
Max.
5
8
8
Unit
pF
pF
pF
Note)These parameters are sampled and are not 100% tested.
– 5–
CXK77B3610GB
•AC Electrical Characteristics
Item
Address access (except Register-Register mode)
Clock period
Clock pulse high
Clock pulse low
Setup time
Hold time
Clock high to output (R-R mode)
Clock high to output (R-F mode, R-L mode)
Clock low to output (R-L mode)
Write cycle clock high to following Read cycle output
(R-F mode, R-L mode)
Clock high to output high impedance (S deselect cycle)
Write cycle clock high to output high impedance
(R-F mode, R-L mode)
Clock high to output low impedance
(R-R mode)
Clock high to output low impedance
(R-F mode)
Clock low to output low impedance (R-L mode)
Output enable to output valid (G)
Output enable to output in low Z (G)
Output disable to output in high Z (G)
Symbol
-6
Min.
—
6
2
2
0.5
1
1.5
∗
2
—
1.5
∗
2
Max.
9
—
—
—
—
—
3
6
3
15
1.5
1.5
1.5
2
1.5
—
1
—
3
3
—
—
—
3
—
3
1.5
1.5
1.5
2
1.5
—
1
—
Min.
—
7
3
3
1
1
1.5
∗
2
—
1.5
∗
2
-7
Max.
10
—
—
—
—
—
3.5
7
3.5
17
3.5
3.5
—
—
—
3.5
—
3.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
AA
t
KP
t
KH
t
KL
t
S
t
H
t
KQ
t
KQ1
t
KQ2
t
KQ3
t
HZ
∗
2
t
WHZ
∗
2
t
LZ
∗
2
t
LZ1
∗
2
t
LZ2
∗
2
t
OE
t
OLZ
∗
2
t
OHZ
∗
2
∗
1
All parameters are specified over the range 0 to 70°C.
∗
2
These parameters are sampled and are not 100% tested.
AC characteristics
•AC test conditions
Item
Input pulse high level
Input pulse low level
Input rise & fall time
Input reference level
Clock input reference level
Clock input differential signal
Clock input rise & fall time
Output reference level
Output load conditions
(V
DD
= 3.3V ±0.15V, Ta = 0 to 70°C)
Conditions
V
IH
= 2.4V
V
IL
= 0.4V
1V/ns
2.0/0.8V
K/K cross;
C/C cross
0.8V
1V/ns
1.4V
Fig. 1
– 6–
∗
1
Including scope and jig capacitance.
∗
2
For
t
LZ
,
t
HZ
.
Fig. 1.
I/O
50Ω
50Ω
1.4V
I/O
5pF
∗
1
1178Ω
Output Load (1)
Output Load (2)
∗
2
3.3V
868Ω
CXK77B3610GB
Register-Register mode
Timing waveform of READ CYCLE
K
K
t
KP
t
S
A0 to 14
n
t
H
n + 1
t
KH
t
KL
n + 2
W
t
S
t
H
t
S
S
t
KQ
t
KQ
G
t
LZ
DQ0 to 35
Qn – 2
t
OHZ
t
OLZ
t
HZ
Qn – 1Qn
t
OE
t
H
Timing waveform of WRITE CYCLE
K
K
t
S
A0 to 14
n
t
H
n + 1n + 2
S
W/BWx
G
DQ0 to 35
Dn – 1DnDn + 1
– 7–
CXK77B3610GB
Register-Register mode
Timing waveform of READ-WRITE-READ CYCLE I(S controlled)
K
K
A0 to 14
NN + 2N + 3N + 4N + 5
S
W/BWx
G = V
IL
DQ0 to 35
Qn – 1
Reed N
Deselect
(Hi-Z)
Qn
Write N + 2
Dn + 2
Reed N + 3
Qn + 3
Timing waveform of READ-WRITE-READ CYCLE II(G controlled)
K
K
A0 to 14
NN + 2N + 3N + 4N + 5
S = V
IL
W/BWx
G
DQ0 to 35
Qn – 1
Qn
Dn + 2Qn + 3
Reed N
Hi-Z;
Write N + 2
Reed N + 3
– 8–
CXK77B3610GB
Register-Latch mode
Timing waveform of READ CYCLE
K
K
t
KP
t
S
t
H
n + 1
t
KH
t
KL
A0 to 14
nn + 2
W
t
S
t
H
t
S
S
t
KQ2
t
KQ1
t
KQ2
t
OE
t
H
t
S
t
H
t
KQ1
t
AA
G
t
LZ2
t
OHZ
t
OLZ
t
HZ
DQ0 to 35
Qn – 1
QnQn + 1
Timing waveform of WRITE CYCLE
K
K
t
S
A0 to 14
n
t
KP
t
H
n + 1n + 2
S
W/BWx
G
DQ0 to 35
Dn – 1DnDn + 1
– 9–
CXK77B3610GB
Register-Latch mode
Timing waveform of READ-WRITE-READ CYCLE
K
K
A0 to 14
S
W/BWx
G = V
IL
DQ0 to 35
t
KP
t
KP
t
KP
t
KP
NN + 1N + 2N + 3N + 4N + 5
t
S
t
H
t
t
H
S
t
H
t
S
t
KQ2
t
KQ1
t
KQ2
t
AA
t
KQ1
t
WHZ
t
S
t
H
t
KQ2
t
LZ2
QnDn + 1
Qn + 2Qn + 4
t
KQ3
t
LZ1
Reed NWrite N + 1Reed N + 2
Deselect
(Hi-Z)
Reed N + 4
– 10–
CXK77B3610GB
Register-Flow Thru mode
Timing waveform of READ CYCLE
K
K
t
S
A0 to 14
n
t
H
t
KP
t
KH
t
KL
n + 1n + 2
W
t
S
t
H
t
S
S
t
KQ1
t
KQ1
G
t
AA
t
OE
t
H
t
S
t
H
t
LZ1
DQ0 to 35
Qn – 1
t
OHZ
Qn
t
OLZ
t
HZ
Qn + 1
Timing waveform of WRITE CYCLE
K
K
t
S
A0 to 14
n
t
H
n + 1n + 2
S
W/BWx
G
DQ0 to 35
Dn – 1DnDn + 1
– 11–
CXK77B3610GB
Register-Flow Thru mode
Timing waveform of READ-WRITE-READ CYCLE
K
K
A0 to 14
S
W/BWx
G = V
IL
DQ0 to 35
NN + 1N + 2N + 3N + 4N + 5
t
S
t
H
t
t
H
S
t
H
t
S
t
t
KQ1
AA
t
KO1
t
WHZ
t
S
t
H
t
KQ1
QnDn + 1Qn + 2Qn + 4
t
KQ3
t
LZ1
Reed NWrite N + 1Reed N + 2
Deselect
(Hi-Z)
Reed N + 4
– 12–
CXK77B3610GB
Test Mode Description
Fuctional Description
The CXK77B3610 provides JTAG boundary scan interface using IEEE std. 1149.1 protocol. The test mode is
intended to provided a mechanism for testing the interconnect between master (processor, controller, etc.),
SRAMs other components and print circuit board.
In conformance with IEEE std. 1149.1, the CXK77B3610 contains a TAP controller, Instruction register,
Boundary scan register and Bypass register.
Test Access Port (TAP)
4 pins as defined in Pin Description table are used to perform JTAG functions. TDI input pin is used to scan
test data serially into one of three registers (Instruction register, Boundary scan register and Bypass register).
TDO is output pin used to scan test data serially out. The TDI send the data into LSBof selected register and
the MSB of the selected register feeds the data to TDO. TMS input pin controls the state transition of 16 state
TAP controller as specified in IEEE std. 1149.1. Inputs on TDI, TMS are registered on the rising edge of TCK
clock and the output data on TDO is presented on the falling edge of TCK. TDO driver is in active state only
when TAP conroller is in Shift-IR state or in Shift-DR state.
TAP Controller
16 state controller is implemented as specified in IEEE std. 1149.1.
The controller enter reset state in one of three ways:
1. Power up
2. Apply logic 1 on TMS input pin on 5 consecutive TCK rising edges.
Instruction Resister (3 bits)
The JTAG Instruction resister is consisted of shift resister stage and parallel output latch. The register is 3 bits
wide and is encoded as follow:
Octal
0
1
2
3
4
5
6
7
MSB LSB
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Bypass
IDCODE. read device ID
Sample-Z. Sample Inputs and tri-state DQs
Bypass
Sample. Sample Inputs.
Private. Manufacturer use only.
Bypass
Bypass
Instruction
Bypass Register (1 bit)
The Bypass Register is one bit wide and is connected electrically between TDI and TDO and provides the
minimum length serial path between TDI and TDO.
– 13–
CXK77B3610GB
ID Registers (32 bits)
The ID Register are 32 bits wide and are listed as follow:
ID [0]
Sony ID
Part Number
Revision Number
ID [11:1]
ID [27:12]
ID [31:28]
1
0000 1110 001
0000 0000 0000 0000
xxxx
∗
1
∗
1
Please contact Sony Sales Department.
Boundary Scan Register (70 bits)
The Boundary Scan Registers are 70 bits wide and are listed as follow:
DQ
A
W, BWx
S, G
K, K, C, C
ZZ
Mode
Place Holder
36
15
5
2
4
1
2
5
K/K, C/C inputs are sampled through one differential stage and internal inverted to generate internal K/K, C/C
signals for scan registers. Place Holder are required for some NC pins to maintain 70 bits Scan Register for
different types of same family SRAM and for density upgrade. All Place Holder Registers are connected to V
SS
internally regardless of pin connection externally.
– 14–
CXK77B3610GB
Scan Order (Order by exit sequence)
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
—
—
3A
3C
2C
2A
2D
1D
2E
1E
2F
2G
1G
2H
1H
3G
—
4E
4G
4H
4M
3L
1K
2K
1L
2L
2M
1N
2N
1P
2P
3T
2R
4N
3R
V
SS
V
SS
A
A
A
A
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
/Wc
V
SS
/S
/C
C
/W
/Wd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
A
A
A
M1
V
SS
V
SS
A
A
A
A
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
/Wb
/G
K
/K
/Wa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
ZZ
A
A
A
A
M2
—
—
5A
5C
6C
6A
6D
7D
6E
7E
6F
6G
7G
6H
7H
5G
4F
4K
4L
5L
7K
6K
7L
6L
6M
7N
6N
7P
6P
7T
5T
6R
4T
4P
5R
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
– 15–
CXK77B3610GB
Package OutlineUnit: mm
119 TERMINAL BGA (PLASTIC)
14.0
11.5
B
A
0.6 ± 0.1
X
C
3.19
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
7.62
1.27
0
.
8
4
1
9
.
5
C
1
.
0
× 4
0.10
1 2 3 4 5 6 7
3
-
0.6 ± 0.1
1.5
φ0.75 ± 0.15
φ0.3
φ0.1
2
0
.
3
2
CAB
EPOXY RESIN
COPPER-CLAD LAMINATE
SOLDER
0.8g
2
2
.
0
0.35
1
.
2
7
C
SONY CODE
EIAJ CODE
JEDEC CODE
C
4
-
6
0
.
DETAIL X
BGA-119P-01
C
5
1
.
0.15C
PACKAGE STRUCTURE
PACKAGE MATERIAL
BOARD MATERIAL
TERMINAL MATERIAL
PACKAGE WEIGHT
– 16–