NANYA_NT5DS32M16CS-5T-USB迷|专注于互联网分享

2024年11月6日发(作者：胡凝荷)

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Features

•DDR 512M bit, Die C, based on 90nm design rules

•Double data rate architecture: two data transfers per

clock cycle

•Bidirectional data strobe (DQS) is transmitted and

received with data, to be used in capturing data at the

receiver

•DQS is edge-aligned with data for reads and is center-

aligned with data for writes

•Differential clock inputs (CK and CK)

•Four internal banks for concurrent operation

•Data mask (DM) for write data

•DLL aligns DQ and DQS transitions with CK transitions

•Commands entered on each positive CK edge; data and

data mask referenced to both edges of DQS

•Burst lengths: 2, 4, or 8

•CAS Latency: 2.5, 3

•Auto Precharge option for each burst access

•Auto Refresh and Self Refresh Modes

•7.8µs Maximum Average Periodic Refresh Interval

•2.5V (SSTL_2 compatible) I/O

•V

= V

DDQ

= 2.6V ± 0.1V (DDR400)

•V

= V

DDQ

= 2.5V ± 0.2V (DDR333)

•RoHS compliance

Description

Die C of 512Mb SDRAM devices based using DDR interface.

They are all based on Nanya’s 90 nm design process.

The 512Mb DDR SDRAM is a high-speed CMOS, dynamic

random-access memory containing 536,870,912 bits. It is

internally configured as a quad-bank DRAM.

The 512Mb DDR SDRAM uses a double-data-rate architec-

ture to achieve high-speed operation. The double data rate

architecture is essentially a 2n prefetch architecture with an

interface designed to transfer two data words per clock cycle

at the I/O pins. A single read or write access for the 512Mb

DDR SDRAM effectively consists of a single 2n-bit wide, one

clock cycle data transfer at the internal DRAM core and two

corresponding n-bit wide, one-half-clock-cycle data transfers

at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally,

along with data, for use in data capture at the receiver. DQS

is a strobe transmitted by the DDR SDRAM during Reads

and by the memory controller during Writes. DQS is edge-

aligned with data for Reads and center-aligned with data for

Writes.

The 512Mb DDR SDRAM operates from a differential clock

(CK and CK; the crossing of CK going high and CK going

LOW is referred to as the positive edge of CK). Commands

(address and control signals) are registered at every positive

edge of CK. Input data is registered on both edges of DQS,

and output data is referenced to both edges of DQS, as well

as to both edges of CK.

Read and write accesses to the DDR SDRAM are burst ori-

ented; accesses start at a selected location and continue for

a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an Active

command, which is then followed by a Read or Write com-

mand. The address bits registered coincident with the Active

command are used to select the bank and row to be

accessed. The address bits registered coincident with the

Read or Write command are used to select the bank and the

starting column location for the burst access.

The DDR SDRAM provides for programmable Read or Write

burst lengths of 2, 4, or 8 locations. An Auto Precharge func-

tion may be enabled to provide a self-timed row precharge

that is initiated at the end of the burst access.

As with standard SDRAMs, the pipelined, multibank architec-

ture of DDR SDRAMs allows for concurrent operation,

thereby providing high effective bandwidth by hiding row pre-

charge and activation time.

An auto refresh mode is provided along with a power-saving

Power Down mode. All inputs are compatible with the JEDEC

Standard for SSTL_2. All outputs are SSTL_2, Class II com-

patible.

The functionality described and the timing specifications

included in this data sheet are for the DLL Enabled mode of

operation.

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Ordering Information (Lead-Free)

Number

NT5DS128M4CS-5T

128M x 4

NT5DS128M4CS-6K

NT5DS128M4CG-5T

NT5DS128M4CG-6K

NT5DS64M8CS-5T

64M x 8

NT5DS64M8CS-6K

NT5DS64M8CG-5T

NT5DS64M8CG-6K

NT5DS32M16CS-5T

32M x 16

NT5DS32M16CS-6K

NT5DS32M16CG-5T

NT5DS32M16CG-6K

Package

Speed

Clock (MHz)

200

166

200

166

200

166

200

166

200

166

200

166

CL-t

RCD

-t

3-3-3

2.5-3-3

3-3-3

2.5-3-3

3-3-3

2.5-3-3

3-3-3

2.5-3-3

3-3-3

2.5-3-3

3-3-3

2.5-3-3

Comments

DDR400

DDR333

DDR400

DDR333

DDR400

DDR333

DDR400

DDR333

DDR400

DDR333

DDR400

DDR333

66 pin TSOP-II

60ball BGA

0.8mmx1.0mm

Pitch

66 pin TSOP-II

60ball BGA

0.8mmx1.0mm

Pitch

66 pin TSOP-II

60ball BGA

0.8mmx1.0mm

Pitch

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Pin Configuration - 400mil TSOP II (x4 / x8 / x16)

DDQ

DQ0

SSQ

DDQ

DQ1

SSQ

DDQ

CAS

RAS

BA0

BA1

A10/AP

DQ0

DDQ

DQ1

SSQ

DQ2

DDQ

DQ3

SSQ

DDQ

CAS

RAS

BA0

BA1

A10/AP

DQ0

DDQ

DQ1

DQ2

SSQ

DQ3

DQ4

DDQ

DQ5

DQ6

SSQ

DQ7

DDQ

LDQS

LDM*

CAS

RAS

BA0

BA1

A10/AP

DQ15

SSQ

DQ14

DQ13

DDQ

DQ12

DQ11

SSQ

DQ10

DQ9

DDQ

DQ8

SSQ

UDQS

REF

UDM*

CKE

A12

A11

DQ7

SSQ

DQ6

DDQ

DQ5

SSQ

DQ4

DDQ

SSQ

DQS

REF

DM*

CKE

A12

A11

SSQ

DQ3

DDQ

SSQ

DQ2

DDQ

SSQ

DQS

REF

DM*

CKE

A12

A11

66-pin Plastic TSOP-II 400mil

32Mb x 16

64Mb x 8

128Mb x 4

Column Address Table

Organization

128Mb x 4

64Mb x 8

32Mb x 16

Column Address

A0-A9, A11, A12

A0-A9, A11

A0-A9

*DM is internally loaded to match DQ and DQS identically

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Pin Configuration - 60 balls 0.8mmx1.0mm Pitch CSP Package

See the balls through the package.

128 X 4

VSSQ

VREF

VDDQ

VSSQ

VDDQ

VSSQ

VSS

CLK

A12

A11

VSS

DQ3

DQ2

DQS

DQM

CLK

CKE

VSS

VDD

DQ0

DQ1

RAS

BA1

VDD

VSSQ

VDDQ

VSSQ

VDDQ

VDD

CAS

BA0

A10/

VDDQ

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Pin Configuration - 60 balls 0.8mmx1.0mm Pitch CSP Package

See the balls through the package.

32 X 16

VSSQ

DQ14

DQ12

DQ10

DQ8

VREF

DQ15

VDDQ

VSSQ

VDDQ

VSSQ

VSS

CLK

A12

A11

VSS

DQ13

DQ11

DQ9

UDQS

UDM

CLK

CKE

VSS

VDD

DQ2

DQ4

DQ6

LDQS

LDM

RAS

BA1

VDD

DQ0

VSSQ

VDDQ

VSSQ

VDDQ

VDD

CAS

BA0

A10/

VDDQ

DQ1

DQ3

DQ5

DQ7

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Input/Output Functional Description

Symbol

CK, CK

Type

Input

Function

Clock: CK and CK are differential clock inputs. All address and control input signals are sampled

on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-

enced to the crossings of CK and CK (both directions of crossing).

Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device

input buffers and output drivers. Taking CKE Low provides Precharge Power Down and Self

Refresh operation (all banks idle), or Active Power Down (row Active in any bank). CKE is syn-

chronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self

refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,

excluding CK, CK and CKE are disabled during Power Down. Input buffers, excluding CKE, are

disabled during self refresh. The standard pinout includes one CKE pin.

Chip Select: All commands are masked when CS is registered high. CS provides for external

bank selection on systems with multiple banks. CS is considered part of the command code. The

standard pinout includes one CS pin.

Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.

Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is

sampled high coincident with that input data during a Write access. DM is sampled on both edges

of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Dur-

ing a Read, DM can be driven high, low, or floated.

Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge

command is being applied. BA0 and BA1 also determines if the mode register or extended mode

Address Inputs: Provide the row address for Active commands, and the column address and

Auto Precharge bit for Read/Write commands, to select one location out of the memory array in

the respective bank. A10 is sampled during a Precharge command to determine whether the Pre-

charge applies to one bank (A10 low) or all banks (A10 high). If only one bank is to be precharged,

the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode

Data Input/Output: Data bus.

Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered

in write data. Used to capture write data.

No Connect: No internal electrical connection is present.

Not Useable:Electrical connection is present. Should not be connected at second level of assem-

bly.

DQ Power Supply: 2.6V ± 0.1V (DDR400); 2.5V ± 0.2V (DDR333)

DQ Ground

Power Supply: 2.6V ± 0.1V (DDR400); 2.5V ± 0.2V (DDR333)

Ground

SSTL_2 reference voltage

CKEInput

RAS, CAS, WE

Input

BA0, BA1Input

A0 - A12Input

DQS

DDQ

SSQ

REF

Input/Output

Supply

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Block Diagram (128Mb x 4)

CKE

CAS

RAS

Bank1

Bank2

Bank3

CK, CK

DLL

Mode

Registers

8192

Sense Amplifiers

DQS

Generator

Bank0

Memory

Array

(8192 x 2048 x 8)

Data

2048

(x8)

Column

Decoder

clk

out

Data

CK,

COL0

Column-Address

Counter/Latch

COL0

Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of

the device; it does not represent an actual circuit implementation.

Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-

rectional DQ and DQS signals.

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

A0-A12,

BA0, BA1

I/O Gating

DM Mask Logic

COL0

Write

FIFO

Drivers

Input

Mask

DQS

DQ0-DQ3,

DQS

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Block Diagram (64Mb x 8)

CKE

CAS

RAS

Bank1

Bank2

Bank3

CK, CK

DLL

Mode

Registers

8192

Sense Amplifiers

DQS

Generator

Bank0

Memory

Array

(8192 x 1024 x 16)

Data

1024

(x16)

Column

Decoder

Column-Address

Counter/Latch

COL0

clk

out

Data

CK,

COL0

Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of

the device; it does not represent an actual circuit implementation.

Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-

rectional DQ and DQS signals.

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

A0-A12,

BA0, BA1

I/O Gating

DM Mask Logic

COL0

Write

FIFO

Drivers

Input

Mask

DQS

DQ0-DQ7,

DQS

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Block Diagram (32Mb x 16)

CKE

CAS

RAS

Bank1

Bank2

Bank3

CK, CK

DLL

Mode

Registers

8192

Sense Amplifiers

DQS

Generator

Bank0

Memory

Array

(8192 x 512 x 32)

Data

512

(x32)

COL0

Column

Decoder

Column-Address

Counter/Latch

COL0

clk

out

Data

CK,

Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of

the device; it does not represent an actual circuit implementation.

Note: UDM and LDM are unidirectional signals (input only), but is internally loaded to match the

load of the bidirectional DQ, UDQS, and LDQS signals.

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

A0-A12,

BA0, BA1

I/O Gating

DM Mask Logic

COL0

Write

FIFO

Drivers

Input

Mask

DQS

DQ0-DQ15,

LDM, UDM

LDQS,UDQS

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Functional Description

The 512Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. The 512Mb

DDR SDRAM is internally configured as a quad-bank DRAM.

The 512Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate architec-

ture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O

pins. A single read or write access for the 512Mb DDR SDRAM consists of a single 2n-bit wide, one clock cycle data transfer at

the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.

Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a pro-

grammed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is

then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select

the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident

with the Read or Write command are used to select the starting column location for the burst access.

Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering

device initialization, register definition, command descriptions and device operation.

Initialization

Only one of the following two conditions must be met.

• No power sequencing is specified during power up or power down given the following criteria:

and V

DDQ

are driven from a single power converter output

meets the specification

A minimum resistance of 42 ohms limits the input current from the VTT supply into any pin and

REF

tracks V

DDQ

• The following relationships must be followed:

DDQ

is driven after or with V

such that V

DDQ

< V

+ 0.3V

is driven after or with V

DDQ

such that V

< V

DDQ

+ 0.3V

REF

is driven after or with V

DDQ

such that V

REF

< V

DDQ

+ 0.3V

The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a read access). After

all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200µs delay prior to

applying an executable command.

Once the 200µs delay has been satisfied, a Deselect or NOP command should be applied, and CKE must be brought HIGH.

Following the NOP command, a Precharge ALL command must be applied. Next a Mode Register Set command must be

issued for the Extended Mode Register, to enable the DLL, then a Mode Register Set command must be issued for the Mode

Register, to reset the DLL, and to program the operating parameters. 200 clock cycles are required between the DLL reset and

any read command. A Precharge ALL command should be applied, placing the device in the “all banks idle” state

Once in the idle state, two auto refresh cycles must be performed. Additionally, a Mode Register Set command for the Mode

Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the DLL) must be performed.

Following these cycles, the DDR SDRAM is ready for normal operation.

DDR SDRAM’s may be reinitialized at any time during normal operation by asserting a valid MRS command to either the base

or extended mode registers without affecting the contents of the memory array. The contents of either the mode register or

extended mode register can be modified at any valid time during device operation without affecting the state of the internal

address refresh counters used for device refresh.

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Mode Register

The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of

a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is programmed via the Mode Register

Set command (with BA0 = 0 and BA1 = 0) and retains the stored information until it is programmed again or the device loses

power (except for bit A8, which is self-clearing).

Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the

CAS latency, and A7-A12 specify the operating mode.

The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the

subsequent operation. Violating either of these requirements results in unspecified operation.

Burst Length

Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length

determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths

of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for

that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is

uniquely selected by A1-Ai when the burst length is set to two, by A

-Ai when the burst length is set to four and by A

-Ai when

the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining

(least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length

applies to both Read and Write bursts.

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Mode Register Operation

BA1

BA0

A12A11A10A9A8A7A6A5A4A3

A2A1A0

Address Bus

Mode Register

Operating Mode

CAS LatencyBurst Length

A12

- A9

A6 - A0

Valid

VS**

Operating Mode

Normal operation

Do not reset DLL

Normal operation

in DLL Reset

Vendor-Specific

Test Mode

Reserved

Burst

Type

Sequential

Interleave

−−−

CAS Latency

Latency

Reserved

2.5

Reserved

Burst Length

Reserved

VS** Vendor Specific

* BA0 and BA1 must be 0, 0 to select the Mode Register

(vs. the Extended Mode Register).

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Burst Definition

Burst Length

Starting Column Address

A2A1A0

Order of Accesses Within a Burst

Type = Sequential

0-1

1-0

0-1-2-3

1-2-3-0

2-3-0-1

3-0-1-2

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

2-3-4-5-6-7-0-1

3-4-5-6-7-0-1-2

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

6-7-0-1-2-3-4-5

7-0-1-2-3-4-5-6

Type = Interleaved

0-1

1-0

0-1-2-3

1-0-3-2

2-3-0-1

3-2-1-0

0-1-2-3-4-5-6-7

1-0-3-2-5-4-7-6

2-3-0-1-6-7-4-5

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-4-7-6-1-0-3-2

6-7-4-5-2-3-0-1

7-6-5-4-3-2-1-0

Notes:

a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block.

a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the block.

a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the block.

er a boundary of the block is reached within a given sequence above, the following access wraps within the block.

Burst Type

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type

and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the start-

ing column address, as shown in Burst Definition on page 13.

Read Latency

The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability

of the first burst of output data. The latency can be programmed 3 clocks for DDR400.

If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with

clock edge n + m.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Operating Mode

The normal operating mode is selected by issuing a Mode Register Set Command with bits A7-A12 to zero, and bits A0-A6 set

to the desired values. A DLL reset is initiated by issuing a Mode Register Set command with bits A7 and A9-A12 each set to

zero, bit A8 set to one, and bits A0-A6 set to the desired values. A Mode Register Set command issued to reset the DLL should

always be followed by a Mode Register Set command to select normal operating mode.

All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states

should not be used as unknown operation or incompatibility with future versions may result.

CAS Latencies

CAS Latency = 3, BL = 4

Command

ReadNOP

CL=3

DQS

NOPNOPNOPNOP

Shown with nominal t

, t

DQSCK

, and t

DQSQ

Don’t Care

CAS Latency = 2.5, BL = 4

Command

ReadNOP

CL=2.5

DQS

NOPNOPNOPNOP

Shown with nominal t

, t

DQSCK

, and t

DQSQ

Don’t Care

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Extended Mode Register

The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions

include DLL enable/disable, bit A0; output drive strength selection, bit A1; and QFC output enable/disable, bit A2 (NTC

optional). These functions are controlled via the bit settings shown in the Extended Mode Register Definition. The Extended

Mode Register is programmed via the Mode Register Set command (with BA0 = 1 and BA1 = 0) and retains the stored informa-

tion until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are

idle, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these require-

ments result in unspecified operation.

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to nor-

mal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically disabled when

entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled,

200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before a Read command

can be issued. This is the reason for introducing timing parameter t

XSRD

for DDR SDRAM’s (Exit Self Refresh to Read Com-

mand). Non- Read commands can be issued 2 clocks after the DLL is enabled via the EMRS command (t

MRD

) or 10 clocks after

the DLL is enabled via self refresh exit command (t

XSNR

, Exit Self Refresh to Non-Read Command).

Output Drive Strength

The normal drive strength for all outputs is specified to be SSTL_2, Class II.

QFC Enable/Disable (Not support in this product; Only for information)

The QFC signal is an optional DRAM output control used to isolate module loads (DIMMs) from the system memory bus by

means of external FET switches when the given module (DIMM) is not being accessed. The QFC function is an optional feature

for NANYA and is not included on all DDR SDRAM devices.

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Extended Mode Register Definition

BA1

BA0

QFC

DLL

Address Bus

Extended

Mode Register

Operating Mode

Drive Strength

A12 - A3

A2 - A0

Valid

Operating Mode

Normal Operation

All other states

Reserved

Drive Strength

Normal

Reserved

−−

QFC

Disable

Enable (Not

Support)

DLL

Enable

Disable

* BA0 and BA1 must be 1, 0 to select the Extended Mode Register

(vs. the base Mode Register)

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Commands

Truth Tables 1a and 1b provide a reference of the commands supported by DDR SDRAM devices. A verbal description of each

commands follows.

Truth Table 1a: Commands

Name (Function)

Deselect (Nop)

No Operation (Nop)

Active (Select Bank And Activate Row)

Read (Select Bank And Column, And Start Read Burst)

Write (Select Bank And Column, And Start Write Burst)

Burst Terminate

Precharge (Deactivate Row In Bank Or Banks)

Auto Refresh Or Self Refresh (Enter Self Refresh Mode)

Mode Register Set

RAS

CAS

Address

Bank/Row

Bank/Col

Code

Op-Code

MNE

NOP

ACT

Read

Write

BST

PRE

AR / SR

MRS

Notes

1, 9

1, 3

1, 4

1, 8

1, 5

1, 6, 7

1, 2

is high for all commands shown except Self Refresh.

0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects

Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode

0-BA1 provide bank address and A0-A12 provide row address.

0, BA1 provide bank address; A0-Ai provide column address (where i = 9 for x8 and 9, 11 for x4); A10 high enables the Auto Pre-

charge feature (non-persistent), A10 low disables the Auto Precharge feature.

5.A10 LOW: BA0, BA1 determine which bank is precharged.

A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care.”

command is auto refresh if CKE is high; Self Refresh if CKE is low.

al refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.

s only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto

Precharge enabled or for write bursts

ct and NOP are functionally interchangeable.

Truth Table 1b: DM Operation

Name (Function)

Write Enable

Write Inhibit

to mask write data; provided coincident with the corresponding data.

DQs

Valid

Notes

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Deselect

The Deselect function prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is

effectively deselected. Operations already in progress are not affected.

No Operation (NOP)

The No Operation (NOP) command is used to perform a NOP to a DDR SDRAM. This prevents unwanted commands from

being registered during idle or wait states. Operations already in progress are not affected.

Mode Register Set

The mode registers are loaded via inputs A0-A12, BA0 and BA1 while issuing the Mode Register Set Command. See mode reg-

ister descriptions in the Register Definition section. The Mode Register Set command can only be issued when all banks are idle

and no bursts are in progress. A subsequent executable command cannot be issued until t

MRD

is met.

Active

The Active command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0,

BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row remains active (or open) for

accesses until a Precharge (or Read or Write with Auto Precharge) is issued to that bank. A Precharge (or Read or Write with

Auto Precharge) command must be issued and completed before opening a different row in the same bank.

Read

The Read command is used to initiate a burst read access to an active (open) row. The value on the BA0, BA1 inputs selects

the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8; where [i = 9, j = 11] for x4) selects the

starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is

selected, the row being accessed is precharged at the end of the Read burst; if Auto Precharge is not selected, the row remains

open for subsequent accesses.

Write

The Write command is used to initiate a burst write access to an active (open) row. The value on the BA0, BA1 inputs selects

the bank, and the address provided on inputs A0-Ai, Aj (where [i = 9, j = don’t care] for x8; where [i = 9, j = 11] for x4) selects the

starting column location. The value on input A10 determines whether or not Auto Precharge is used. If Auto Precharge is

selected, the row being accessed is precharged at the end of the Write burst; if Auto Precharge is not selected, the row remains

open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DM input logic

level appearing coincident with the data. If a given DM signal is registered low, the corresponding data is written to memory; if

the DM signal is registered high, the corresponding data inputs are ignored, and a Write is not executed to that byte/column

location.

Precharge

The Precharge command is used to deactivate (close) the open row in a particular bank or the open row(s) in all banks. The

bank(s) will be available for a subsequent row access a specified time (t

) after the Precharge command is issued. Input A10

determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs

BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle

state and must be activated prior to any Read or Write commands being issued to that bank. A precharge command is treated

as a NOP if there is no open row in that bank, or if the previously open row is already in the process of precharging.

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Auto Precharge

Auto Precharge is a feature which performs the same individual-bank precharge function described above, but without requiring

an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction with a specific Read or Write

command. A precharge of the bank/row that is addressed with the Read or Write command is automatically performed upon

completion of the Read or Write burst. Auto Precharge is non-persistent in that it is either enabled or disabled for each individual

Read or Write command. Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. This is

determined as if an explicit Precharge command was issued at the earliest possible time without violating t

RAS

(min). The user

must not issue another command to the same bank until the precharge (t

) is completed.

The NTC DDR SDRAM devices supports the optional t

RAS

lockout feature. This feature allows a Read command with Auto Pre-

charge to be issued to a bank that has been activated (opened) but has not yet satisfied the t

RAS

(min) specification. The t

RAS

lockout feature essentially delays the onset of the auto precharge operation until two conditions occur. One, the entire burst

length of data has been successfully prefetched from the memory array; and two, t

RAS

(min) has been satisfied.

As a means to specify whether a DDR SDRAM device supports the t

RAS

lockout feature, a new parameter has been defined,

RAP

(RAS Command to Read Command with Auto Precharge or better stated Bank Activate to Read Command with Auto Pre-

charge). For devices that support the t

RAS

lockout feature, t

RAP

= t

RCD

(min). This allows any Read Command (with or without

Auto Precharge) to be issued to an open bank once t

RCD

(min) is satisfied.

RAP

Definition

CL=2, t

=10ns

Command

DQ (BL=2)

RASmin

Command

DQ (BL=4)

NOPACTNOPRD ANOPNOP

DQ0

NOPACTNOPRD ANOPNOP

DQ0

NOP

DQ1

NOPACTNOPNOP

RPmin

NOP

DQ3

ACTNOPNOPNOP

DQ2DQ1

Command

DQ (BL=8)

NOPACTNOPRD ANOPNOP

DQ0

DQ1

RPmin

NOP

DQ3DQ4

NOP

DQ5DQ6

ACT

DQ7

NOPNOP

DQ2

RCDmin

RAPmin

The above timing diagrams show the effects of t

RAP

for devices that support t

RAS

lockout. In these cases, the Read

with Auto Precharge command (RDA) is issued with t

RCD

(min) and dataout is available with the shortest latency from the

Bank Activate command (ACT). The internal precharge operation, however, does not begin until after t

RAS

(min) is satisfied.

Indicates Auto Precharge begins here

RPmin

Burst Terminate

The Burst Terminate command is used to truncate read bursts (with Auto Precharge disabled). The most re-cently registered

Read command prior to the Burst Terminate command is truncated, as shown in the Operation section of this data sheet. Write

burst cycles are not to be terminated with the Burst Terminate command.

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Auto Refresh

Auto Refresh is used during normal operation of the DDR SDRAM and is analogous to CAS Before RAS (CBR) Refresh in pre-

vious DRAM types. This command is nonpersistent, so it must be issued each time a refresh is required.

The refresh addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during an Auto

Refresh command. The 512Mb DDR SDRAM requires Auto Refresh cycles at an average periodic interval of 7.8µs (maximum).

Self Refresh

The Self Refresh command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down.

When in the self refresh mode, the DDR SDRAM retains data without external clocking. The Self Refresh command is initiated

as an Auto Refresh command coincident with CKE transitioning low. The DLL is automatically disabled upon entering Self

Refresh, and is automatically enabled upon exiting Self Refresh (200 clock cycles must then occur before a Read command can

be issued). Input signals except CKE (low) are “Don’t Care” during Self Refresh operation.

The procedure for exiting self refresh requires a sequence of commands. CK (and CK) must be stable prior to CKE returning

high. Once CKE is high, the SDRAM must have NOP commands issued for t

XSNR

because time is required for the completion of

any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200

clock cycles before applying any other command.

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Operations

Bank/Row Activation

Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must be “opened”

(activated). This is accomplished via the Active command and addresses A0-A12, BA0 and BA1 (see Activating a Specific Row

in a Specific Bank), which decode and select both the bank and the row to be activated. After opening a row (issuing an Active

command), a Read or Write command may be issued to that row, subject to the t

RCD

specification. A subsequent Active com-

mand to a different row in the same bank can only be issued after the previous active row has been “closed” (precharged). The

minimum time interval between successive Active commands to the same bank is defined by t

. A subsequent Active com-

mand to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access

overhead. The minimum time interval between successive Active commands to different banks is defined by t

RRD

Activating a Specific Row in a Specific Bank

CKE

RAS

CAS

A0-A12

BA0, BA1

RA = row address.

BA = bank address.

Don’t Care

HIGH

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

RCD

and t

RRD

Definition

Command

A0-A12

BA0, BA1

ACT

ROW

BA x

NOPACT

ROW

BA y

NOPNOPRD/WR

COL

BA y

NOPNOP

RRD

RCD

Don’t Care

Reads

Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are initiated with a

Read command.

The starting column and bank addresses are provided with the Read command and Auto Precharge is either enabled or dis-

abled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge at the completion of the

burst, provided t

RAS

has been satisfied. For the generic Read commands used in the following illustrations, Auto Precharge is

disabled.

During Read bursts, the valid data-out element from the starting column address is available following the CAS latency after the

Read command. Each subsequent data-out element is valid nominally at the next positive or negative clock edge (i.e. at the

next crossing of CK and CK). The following timing figure entitled “Read Burst: CAS Latencies (Burst Length=4)” illustrates the

general timing for each supported CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial low

state on DQS is known as the read preamble; the low state coincident with the last data-out element is known as the read post-

amble. Upon completion of a burst, assuming no other commands have been initiated, the DQs and DQS goes High-Z. Data

from any Read burst may be concatenated with or truncated with data from a subsequent Read command. In either case, a con-

tinuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed

burst or the last desired data element of a longer burst which is being truncated. The new Read command should be issued x

cycles after the first Read command, where x equals the number of desired data element pairs (pairs are required by the 2n

prefetch architecture). This is shown in timing figure entitled “Consecutive Read Bursts: CAS Latencies (Burst Length =4 or 8)”.

A Read command can be initiated on any positive clock cycle following a previous Read command. Nonconsecutive Read data

is shown in timing figure entitled “Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)”. Full-speed Random Read

Accesses: CAS Latencies (Burst Length = 2, 4 or 8) within a page (or pages) can be performed as shown on page 27.

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Read Command

CKE

RAS

CAS

x4: A0-A9, A11

x8: A0-A9

A10

DIS AP

BA0, BA1

CA = column address

BA = bank address

EN AP = enable Auto Precharge

DIS AP = disable Auto Precharge

Don’t Care

EN AP

HIGH

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Read Burst: CAS Latencies (Burst Length = 4)

CAS Latency = 3

Command

Address

Read

BA a,COL n

NOPNOPNOPNOPNOP

CL=3

DQS

QFC

(Optional)

QCS

DOa-n

QCH

CAS Latency = 2.5

Command

Address

Read

BA a,COL n

NOPNOPNOPNOPNOP

CL=2.5

DQS

DOa-n

(Optional)

QFC

QCS

QCH

Don’t Care

DO a-n = data out from bank a, column n.

3 subsequent elements of data out appear in the programmed order following DO a-n.

Shown with nominal t

, t

DQSCK

, and t

DQSQ

QFC is an open drain driver. The output high level is achieved through an external pull up resistor connected to V

DDQ

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Consecutive Read Bursts: CAS Latencies (Burst Length = 4 or 8)

CAS Latency = 3

Command

Address

Read

BAa, COL n

NOPRead

BAa, COL b

NOPNOPNOP

CL=3

DQS

DOa-n

CAS Latency = 2.5

Command

Address

Read

BAa, COL n

NOPRead

BAa,COL b

NOPNOPNOP

CL=2.5

DQS

DOa- n

DOa- b

DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).

When burst length = 4, the bursts are concatenated.

When burst length = 8, the second burst interrupts the first.

3 subsequent elements of data out appear in the programmed order following DO a-n.

3 (or 7) subsequent elements of data out appear in the programmed order following DO a-b.

Shown with nominal t

, t

DQSCK

, and t

DQSQ

Don’t Care

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Non-Consecutive Read Bursts: CAS Latencies (Burst Length = 4)

CAS Latency = 3

Command

Address

Read

BAa, COL n

NOPNOPRead

BAa, COL b

NOPNOP

CL=3

DQS

DO a-n

CAS Latency = 2.5

Command

Address

Read

BAa, COL n

NOPNOPRead

BAa, COL b

NOPNOPNOP

CL=2.5

DQS

DO a-n

DOa- b

DO a-n (or a-b) = data out from bank a, column n (or bank a, column b).

3 subsequent elements of data out appear in the programmed order following DO a-n (and following DO a-b).

Shown with nominal t

, t

DQSCK

, and t

DQSQ

Don’t Care

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)

CAS Latency = 3

Command

Address

Read

BAa, COL n

Read

BAa, COL x

Read

BAa, COL b

Read

BAa, COL g

NOPNOP

CL=3

DQS

DOa-nDOa-n'DOa-xDOa-x'DOa-g

CAS Latency = 2.5

Command

Address

Read

BAa, COL n

Read

BAa, COL x

Read

BAa, COL b

Read

BAa, COL g

NOPNOP

CL=2.5

DQS

DOa-nDOa-n'DOa-xDOa-x'DOa-bDOa-b’

DO a-n, etc. = data out from bank a, column n etc.

n' etc. = odd or even complement of n, etc. (i.e., column address LSB inverted).

Reads are to active rows in any banks.

Shown with nominal t

, t

DQSCK

, and t

DQSQ

Don’t Care

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Data from any Read burst may be truncated with a Burst Terminate command, as shown in timing figure entitled

Terminating a Read Burst: CAS Latencies (Burst Length = 8) on page 29. The Burst Terminate latency is equal to

the read (CAS) latency, i.e. the Burst Terminate command should be issued x cycles after the Read command,

where x equals the number of desired data element pairs.

Data from any Read burst must be completed or truncated before a subsequent Write command can be issued. If

truncation is necessary, the Burst Terminate command must be used, as shown in timing figure entitled Read to

Write: CAS Latencies (Burst Length = 4 or 8) on page 30. The example is shown for t

DQSS

(min). The t

DQSS

(max)

case, not shown here, has a longer bus idle time. t

DQSS

(min) and t

DQSS

(max) are defined in the section on Writes.

A Read burst may be followed by, or truncated with, a Precharge command to the same bank (provided that Auto

Precharge was not activated). The Precharge command should be issued x cycles after the Read command,

where x equals the number of desired data element pairs (pairs are required by the 2n prefetch architecture). This

is shown in timing figure on page 24 for Read latencies of 3. Following the Precharge command, a subsequent

command to the same bank cannot be issued until t

is met. Note that part of the row precharge time is hidden

during the access of the last data elements.

In the case of a Read being executed to completion, a Precharge command issued at the optimum time (as

described above) provides the same operation that would result from the same Read burst with Auto Precharge

enabled. The disadvantage of the Precharge command is that it requires that the command and address busses

be available at the appropriate time to issue the command. The advantage of the Precharge command is that it can

be used to truncate bursts.

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Terminating a Read Burst: CAS Latencies (Burst Length = 8)

CAS Latency = 3

Command

Address

Read

BAa, COL n

NOPBSTNOPNOPNOP

CL=3

DQS

DOa-n

No further output data after this point.

DQS tristated.

CAS Latency = 2.5

Command

Address

Read

BAa, COL n

NOPBSTNOPNOPNOP

CL=2.5

DQS

DOa-n

No further output data after this point.

DQS tristated.

DO a-n = data out from bank a, column n.

Cases shown are bursts of 8 terminated after 4 data elements.

3 subsequent elements of data out appear in the programmed order following DO a-n.

Shown with nominal t

, t

DQSCK

, and t

DQSQ

Don’t Care

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Read to Write: CAS Latencies (Burst Length = 4 or 8)

CAS Latency = 3

Command

Address

Read

BAa, COL n

BSTNOPWrite

BAa, COL b

NOPNOP

CL=3

DQS

DOa-n

DQSS

(min)

DI a-b

CAS Latency = 2.5

Command

Address

Read

BAa, COL n

BSTNOPNOPWrite

BAa, COL b

NOP

CL=2.5

DQS

DOa-n

DQSS

(min)

Dla-b

DO a-n = data out from bank a, column n

DI a-b = data in to bank a, column b

1 subsequent elements of data out appear in the programmed order following DO a-n.

Data In elements are applied following Dl a-b in the programmed order, according to burst length.

Shown with nominal t

, t

DQSCK

, and t

DQSQ

Don’t Care

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Read to Precharge: CAS Latencies (Burst Length = 4 or 8)

CAS Latency = 3

Command

ReadNOPPRENOPNOPACT

Address

BA a, COL n

BA a or all

BA a, ROW

CL=3

DQS

DOa-n

CAS Latency = 2.5

Command

ReadNOPPRENOPNOPACT

Address

BA a, COL n

BA a or all

BA a, ROW

CL=2.5

DQS

DOa-n

DO a-n = data out from bank a, column n.

Cases shown are either uninterrupted bursts of 4 or interrupted bursts of 8.

3 subsequent elements of data out appear in the programmed order following DO a-n.

Shown with nominal t

, t

DQSCK

, and t

DQSQ

Don’t Care

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Writes

Write bursts are initiated with a Write command, as shown in timing figure Write Command on page 33.

The starting column and bank addresses are provided with the Write command, and Auto Precharge is either enabled or dis-

abled for that access. If Auto Precharge is enabled, the row being accessed is precharged at the completion of the burst. For

the generic Write commands used in the following illustrations, Auto Precharge is disabled.

During Write bursts, the first valid data-in element is registered on the first rising edge of DQS following the write command, and

subsequent data elements are registered on successive edges of DQS. The Low state on DQS between the Write command

and the first rising edge is known as the write preamble; the Low state on DQS following the last data-in element is known as

the write postamble. The time between the Write command and the first corresponding rising edge of DQS (t

DQSS

) is specified

with a relatively wide range (from 75% to 125% of one clock cycle), so most of the Write diagrams that follow are drawn for the

two extreme cases (i.e. t

DQSS

(min) and t

DQSS

(max)). Timing figure Write Burst (Burst Length = 4) on page 34 shows the two

extremes of t

DQSS

for a burst of four. Upon completion of a burst, assuming no other commands have been initiated, the DQs

and DQS enters High-Z and any additional input data is ignored.

Data for any Write burst may be concatenated with or truncated with a subsequent Write command. In either case, a continuous

flow of input data can be maintained. The new Write command can be issued on any positive edge of clock following the previ-

ous Write command. The first data element from the new burst is applied after either the last element of a completed burst or

the last desired data element of a longer burst which is being truncated. The new Write command should be issued x cycles

after the first Write command, where x equals the number of desired data element pairs (pairs are required by the 2n prefetch

architecture). Timing figure Write to Write (Burst Length = 4) on page 35 shows concatenated bursts of 4. An example of non-

consecutive Writes is shown in timing figure Write to Write: Max DQSS, Non-Consecutive (Burst Length = 4) on page 36. Full-

speed random write accesses within a page or pages can be performed as shown in timing figure Random Write Cycles (Burst

Length = 2, 4 or 8) on page 37. Data for any Write burst may be followed by a subsequent Read command. To follow a Write

without truncating the write burst, t

WTR

(Write to Read) should be met as shown in timing figure Write to Read: Non-Interrupting

(CAS Latency = 3; Burst Length = 4) on page 38.

Data for any Write burst may be truncated by a subsequent (interrupting) Read command. This is illustrated in timing figures

“Write to Read: Interrupting (CAS Latency =2; Burst Length = 8)”, “Write to Read: Minimum D

QSS

, Odd Number of Data (3 bit

Write), Interrupting (CAS Latency = 2; Burst Length = 8)”, and “Write to Read: Nominal D

QSS

, Interrupting (CAS Latency = 2;

Burst Length = 8)”. Note that only the data-in pairs that are registered prior to the t

WTR

period are written to the internal array,

and any subsequent data-in must be masked with DM, as shown in the diagrams noted previously.

Data for any Write burst may be followed by a subsequent Precharge command. To follow a Write without truncating the write

burst, t

should be met as shown in timing figure Write to Precharge: Non-Interrupting (Burst Length = 4) on page 42.

Data for any Write burst may be truncated by a subsequent Precharge command, as shown in timing figures Write to Pre-

charge: Interrupting (Burst Length = 4 or 8) on page 43 to Write to Precharge: Nominal DQSS (2 bit Write), Interrupting (Burst

Length = 4 or 8) on page 45. Note that only the data-in pairs that are registered prior to the t

period are written to the internal

array, and any subsequent data in should be masked with DM. Following the Precharge command, a subsequent command to

the same bank cannot be issued until t

is met.

In the case of a Write burst being executed to completion, a Precharge command issued at the optimum time (as described

above) provides the same operation that would result from the same burst with Auto Precharge. The disadvantage of the Pre-

charge command is that it requires that the command and address busses be available at the appropriate time to issue the com-

mand. The advantage of the Precharge command is that it can be used to truncate bursts.

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Write Command

CKE

RAS

CAS

A0-A9

EN AP

A10

DIS AP

BA0, BA1

CA = column address

BA = bank address

EN AP = enable Auto Precharge

DIS AP = disable Auto Precharge

Don’t Care

HIGH

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Write Burst (Burst Length = 4)

Maximum D

QSS

Command

Address

Write

BA a, COL b

T2T3T4

NOPNOPNOP

DQSS

(max)

DQS

QFC

(Optional)

QCSW

(max)t

QCHW

(min)

Dla-b

Minimum D

QSS

Command

Address

Write

BA a, COL b

NOPNOPNOP

T2T3T4

DQSS

(min)

DQS

QFC

QCSW

(max)

QCHW

(max)

Dla-b

DI a-b = data in for bank a, column b.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

A non-interrupted burst is shown.

A10 is Low with the Write command (Auto Precharge is disabled).

QFC is an open drain driver. Its output high level is achieved through an externally connected pull up resistor connected to V

DDQ

Don’t Care

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Write to Write (Burst Length = 4)

Maximum D

QSS

T1T2T3T4T5T6

Command

Address

Write

BAa, COL b

NOPWrite

BAa, COL n

NOPNOPNOP

DQSS

(max)

DQS

DI a-bDI a-n

Minimum D

QSS

T1T2T3T4T5T6

Command

Address

Write

BA, COL b

NOPWrite

BA, COL n

NOPNOPNOP

DQSS

(min)

DQS

DI a-bDI a-n

DI a-b = data in for bank a, column b, etc.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

3 subsequent elements of data in are applied in the programmed order following DI a-n.

A non-interrupted burst is shown.

Each Write command may be to any bank.

Don’t Care

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Write to Write: Max DQSS, Non-Consecutive (Burst Length = 4)

Command

Address

Write

BAa, COL b

T2T3T4T5

NOPNOPWrite

BAa, COL n

NOP

DQSS

(max)

DQS

DI a-b

DI a-n

DI a-b, etc. = data in for bank a, column b, etc.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

3 subsequent elements of data in are applied in the programmed order following DI a-n.

A non-interrupted burst is shown.

Each Write command may be to any bank.

Don’t Care

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Random Write Cycles (Burst Length = 2, 4 or 8)

Maximum D

QSS

Command

Address

Write

BAa, COL b

T2T3T4T5

Write

BAa, COL x

Write

BAa, COL n

Write

BAa, COL a

Write

BAa, COL g

DQSS

(max)

DQS

DI a-bDI a-b’DI a-xDI a-x’DI a-nDI a-n’DI a-aDI a-a’

Minimum D

QSS

Command

Address

Write

BAa, COL b

T2T3T4T5

Write

BAa, COL x

Write

BAa, COL n

Write

BAa, COL a

Write

BAa, COL g

DQSS

(min)

DQS

DI a-bDI a-b’DI a-xDI a-x’DI a-nDI a-n’DI a-aDI a-a’

DI a-g

DI a-b, etc. = data in for bank a, column b, etc.

b', etc. = odd or even complement of b, etc. (i.e., column address LSB inverted).

Each Write command may be to any bank.

Don’t Care

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Write to Read: Non-Interrupting (CAS Latency = 3; Burst Length = 4)

Maximum D

QSS

Command

WriteNOPNOPNOPReadNOP

T2T3T4T5T6

WTR

Address

BAa, COL bBAa, COL n

DQSS

(max)

DQS

DI a-b

CL = 3

Minimum D

QSS

Command

WriteNOPNOPNOPReadNOP

T2T3T4T5T6

WTR

Address

BAa, COL b

BAa, COL n

DQSS

(min)

DQS

DI a-b

CL = 3

DI a-b = data in for bank a, column b.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

A non-interrupted burst is shown.

WTR

is referenced from the first positive CK edge after the last data in pair.

A10 is Low with the Write command (Auto Precharge is disabled).

The Read and Write commands may be to any bank.

Don’t Care

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Write to Read: Interrupting (CAS Latency = 3; Burst Length = 8)

Maximum D

QSS

Command

WriteNOPNOPNOPReadNOP

T2T3T4T5T6

WTR

Address

BAa, COL b

BAa, COL n

DQSS

(max)

DQS

DIa- b

CL = 3

Minimum D

QSS

Command

WriteNOPNOPNOPReadNOP

T2T3T4T5T6

WTR

Address

BAa, COL b

BAa, COL n

DQSS

(min)

DQS

DI a-b

CL = 3

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 4 data elements are written.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

WTR

is referenced from the first positive CK edge after the last data in pair.

The Read command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

The Read and Write commands are not necessarily to the same bank.

1 = These bits are incorrectly written into the memory array if DM is low.

Don’t Care

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Write to Read: Minimum DQSS, Odd Number of Data (3 bit Write), Interrupting (CAS

Latency = 3; Burst Length = 8)

Command

Write

T2T3T4T5T6

NOPNOPNOPReadNOP

WTR

Address

BAa, COL b

BAa, COL n

DQSS

(min)

DQS

DI a-b

CL = 3

122

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 3 data elements are written.

2 subsequent elements of data in are applied in the programmed order following DI a-b.

WTR

is referenced from the first positive CK edge after the last desired data in pair (not the last desired data in element)

The Read command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

The Read and Write commands are not necessarily to the same bank.

1 = This bit is correctly written into the memory array if DM is low.

Don’t Care

2 = These bits are incorrectly written into the memory array if DM is low.

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Write to Read: Nominal DQSS, Interrupting (CAS Latency = 3; Burst Length = 8)

Command

Write

T2T3T4T5T6

NOPNOPNOPReadNOP

WTR

Address

BAa, COL b

BAa, COL n

DQSS

(nom)

DQS

DI a-b

CL = 3

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 4 data elements are written.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

WTR

is referenced from the first positive CK edge after the last desired data in pair.

The Read command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

The Read and Write commands are not necessarily to the same bank.

1 = These bits are incorrectly written into the memory array if DM is low.

Don’t Care

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Write to Precharge: Non-Interrupting (Burst Length = 4)

Maximum D

QSS

Command

WriteNOPNOPNOPNOPPRE

T2T3T4T5T6

Address

BA a, COL b

BA (a or all)

DQSS

(max)

DQS

DI a-b

Minimum D

QSS

Command

WriteNOPNOPNOPNOPPRE

T2T3T4T5T6

Address

BA a, COL b

BA (a or all)

DQSS

(min)

DQS

DI a-b

DI a-b = data in for bank a, column b.

3 subsequent elements of data in are applied in the programmed order following DI a-b.

A non-interrupted burst is shown.

is referenced from the first positive CK edge after the last data in pair.

A10 is Low with the Write command (Auto Precharge is disabled).

Don’t Care

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Write to Precharge: Interrupting (Burst Length = 4 or 8)

Maximum D

QSS

Command

WriteNOPNOPNOPPRENOP

T2T3T4T5T6

Address

BA a, COL bBA (a or all)

DQSS

(max)

DQS

DI a-b

Minimum D

QSS

Command

WriteNOPNOPNOPPRENOP

T2T3T4T5T6

Address

BA a, COL b

BA (a or all)

DQSS

(min)

DQS

DI a-b

3311

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 2 data elements are written.

1 subsequent element of data in is applied in the programmed order following DI a-b.

is referenced from the first positive CK edge after the last desired data in pair.

The Precharge command masks the last 2 data elements in the burst, for burst length = 8.

A10 is Low with the Write command (Auto Precharge is disabled).

1 = Can be don't care for programmed burst length of 4.

2 = For programmed burst length of 4, DQS becomes don't care at this point.

3 = These bits are incorrectly written into the memory array if DM is low.

Don’t Care

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Write to Precharge: Minimum DQSS, Odd Number of Data (1 bit Write), Interrupting

(Burst Length = 4 or 8)

Command

Write

T2T3T4T5T6

NOPNOPNOPPRENOP

Address

BA a, COL bBA (a or all)

DQSS

(min)

DQS

DI a-b

344

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 1 data element is written.

is referenced from the first positive CK edge after the last desired data in pair.

The Precharge command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

1 = Can be don't care for programmed burst length of 4.

2 = For programmed burst length of 4, DQS becomes don't care at this point.

3 = This bit is correctly written into the memory array if DM is low.

4 = These bits are incorrectly written into the memory array if DM is low.

Don’t Care

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Write to Precharge: Nominal DQSS (2 bit Write), Interrupting (Burst Length = 4 or 8)

Command

Write

T2T3T4T5T6

NOPNOPNOPPRENOP

Address

BA a, COL b

BA (a or all)

DQSS

(nom)

DQS

DI a-b

3311

DI a-b = Data In for bank a, column b.

An interrupted burst is shown, 2 data elements are written.

1 subsequent element of data in is applied in the programmed order following DI a-b.

is referenced from the first positive CK edge after the last desired data in pair.

The Precharge command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

1 = Can be don't care for programmed burst length of 4.

2 = For programmed burst length of 4, DQS becomes don't care at this point.

3 = These bits are incorrectly written into the memory array if DM is low.

Don’t Care

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Precharge Command

CKE

RAS

CAS

A0-A9, A11

All Banks

A10

BA0, BA1

One Bank

BA = bank address

(if A10 is Low, otherwise Don’t Care).

Don’t Care

HIGH

Precharge

The Precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The

bank(s) is available for a subsequent row access some specified time (t

) after the Precharge command is

issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank

is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are

treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any

Read or Write commands being issued to that bank.

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Power Down

Power Down is entered when CKE is registered low (no accesses can be in progress). If Power Down occurs when all banks

are idle, this mode is referred to as Precharge Power Down; if Power Down occurs when there is a row active in any bank, this

mode is referred to as Active Power Down. Entering Power Down deactivates the input and output buffers, excluding CK, CK

and CKE. The DLL is still running in Power Down mode, so for maximum power savings, the user has the option of disabling the

DLL prior to entering Power Down. In that case, the DLL must be enabled after exiting Power Down, and 200 clock cycles must

occur before a Read command can be issued. In Power Down mode, CKE Low and a stable clock signal must be maintained at

the inputs of the DDR SDRAM, and all other input signals are “Don’t Care”. However, Power Down duration is limited by the

refresh requirements of the device, so in most applications, the self refresh mode is preferred over the DLL-disabled Power

Down mode.

The Power Down state is synchronously exited when CKE is registered high (along with a Nop or Deselect command). A valid,

executable command may be applied one clock cycle later.

Power Down

CKE

Command

VALID

No column

access in

progress

Enter Power Down mode

(Burst Read or Write operation

must not be in progress)

NOP

Exit

power down

mode

PDEX

VALID

Don’t Care

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Truth Table 2: Clock Enable (CKE)

CKE n is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.

Current state is the state of the DDR SDRAM immediately prior to clock edge n.

Command n is the command registered at clock edge n, and action n is a result of command n.

All states and sequences not shown are illegal or reserved.

CKE n-1

Current State

Self Refresh

Power Down

All Banks Idle

Bank(s) Active

Cycle

CKEn

Current

Cycle

Command n

Deselect or NOP

Auto Refresh

Deselect or NOP

See “Truth Table 3: Current State

Bank n - Command to Bank n (Same

Bank)” on page 49

Action n

Maintain Self-Refresh

Exit Self-Refresh

Maintain Power Down

Exit Power Down

Precharge Power Down Entry

Self Refresh Entry

Active Power Down Entry

Notes

ct or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (t

XSNR

) period. A minimum of

200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)

Current State

Any

IdleL

Row ActiveL

Read

(Auto Precharge

Disabled)

RAS

CAS

Command

Deselect

No Operation

Active

Auto Refresh

Mode Register Set

Read

Write

Precharge

Read

Precharge

Burst Terminate

Read

Write

Precharge

Select column and start Read burst

Select column and start Write burst

Deactivate row in bank(s)

Select column and start new Read burst

Truncate Read burst, start Precharge

Burst Terminate

Select column and start Read burst

Select column and start Write burst

Truncate Write burst, start Precharge

Action

NOP. Continue previous operation

Select and activate row

Notes

1-6

1-7

1-6, 10

1-6, 8

1-6, 10

1-6, 8

1-6, 9

1-6, 10, 11

1-6, 10

1-6, 8, 11

Write

(Auto Precharge

Disabled)

table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t

XSNR /

XSRD

has been

met (if the previous state was self refresh).

table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed

to be issued to that bank when in that state. Exceptions are covered in the notes below.

t state definitions:

Idle:The bank has been precharged, and t

has been met.

Row Active:A row in the bank has been activated, and t

RCD

has been met. No data bursts/accesses and no register accesses are in

progress.

Read:A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Write:A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

following states must not be interrupted by a command issued to the same bank.

Precharging:Starts with registration of a Precharge command and ends when t

is met. Once t

is met, the bank is in the idle

state.

Row Activating:Starts with registration of an Active command and ends when t

RCD

is met. Once t

RCD

is met, the bank is in the “row

active” state.

Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when t

has been

met. Once t

is met, the bank is in the idle state.

Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when t

has been

met. Once t

is met, the bank is in the idle state.

Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these

states. Allowable commands to the other bank are determined by its current state and according to Truth Table 4.

following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive

clock edge during these states.

Refreshing: Starts with registration of an Auto Refresh command and ends when t

RFC

is met. Once t

RFC

is met, the DDR SDRAM is

in the “all banks idle” state.

Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when t

MRD

has been met. Once t

MRD

met, the DDR SDRAM is in the “all banks idle” state.

Precharging All: Starts with registration of a Precharge All command and ends when t

is met. Once t

is met, all banks is in the idle

state.

states and sequences not shown are illegal or reserved.

bank-specific; requires that all banks are idle.

or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.

bank-specific; Burst terminate affects the most recent Read burst, regardless of bank.

or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with

Auto Precharge disabled.

es appropriate DM masking.

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Truth Table 4: Current State Bank n - Command to Bank m (Different bank)

Current State

Any

Idle

Row Activating,

Active, or

Precharging

Read

(Auto Precharge

Disabled)

Write

(Auto Precharge

Disabled)

RAS

CAS

Command

Deselect

No Operation

Any Command Otherwise

Allowed to Bank m

Active

Read

Write

Precharge

Active

Read

Precharge

Active

Read

Write

Precharge

Select and activate row

Select column and start Read burst

Select column and start new Write burst

Select and activate row

Select column and start new Read burst

Select and activate row

Select column and start Read burst

Select column and start Write burst

Action

NOP/continue previous operation

Notes

1-6

1-7

1-6

1-7

1-6

1-8

1-7

1-6

table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t

XSNR /

XSRD

has been

met (if the previous state was self refresh).

table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are

those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are cov-

ered in the notes below.

t state definitions:

Idle:

The bank has been precharged, and t

has been met.

Row Active: A row in the bank has been activated, and t

RCD

has been met. No data bursts/accesses and no register accesses are

in progress.

Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Read with Auto Precharge Enabled: See note 10.

Write with Auto Precharge Enabled: See note 10.

Refresh and Mode Register Set commands may only be issued when all banks are idle.

5.A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only.

states and sequences not shown are illegal or reserved.

or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with

Auto Precharge disabled.

es appropriate DM masking.

9.A Write command may be applied after the completion of data output.

Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access

period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with

Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst.

For Write with Auto Precharge, the precharge period begins when t

ends, with t

measured as if Auto Precharge was disabled. The

access period starts with registration of the command and ends where the precharge period (or t

) begins. During the precharge period

of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands to

the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In

either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided).

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Truth Table 4: Current State Bank n - Command to Bank m (Different bank)

Current StateCS

Read (With

Auto Precharge)

Write (With

Auto Precharge)

RAS

CAS

Command

Active

Read

Write

Precharge

Active

Read

Write

Precharge

Select and activate row

Select column and start Read burst

Select column and start new Write burst

Action

Select and activate row

Select column and start new Read burst

Select column and start Write burst

Notes

1-6

1-7,10

1-7,9,10

1-6

1-7,10

1-6

table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after t

XSNR /

XSRD

has been

met (if the previous state was self refresh).

table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are

those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are cov-

ered in the notes below.

t state definitions:

Idle:

The bank has been precharged, and t

has been met.

Row Active: A row in the bank has been activated, and t

RCD

has been met. No data bursts/accesses and no register accesses are

in progress.

Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.

Read with Auto Precharge Enabled: See note 10.

Write with Auto Precharge Enabled: See note 10.

Refresh and Mode Register Set commands may only be issued when all banks are idle.

5.A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only.

states and sequences not shown are illegal or reserved.

or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with

Auto Precharge disabled.

es appropriate DM masking.

9.A Write command may be applied after the completion of data output.

Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access

period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with

Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst.

For Write with Auto Precharge, the precharge period begins when t

ends, with t

measured as if Auto Precharge was disabled. The

access period starts with registration of the command and ends where the precharge period (or t

) begins. During the precharge period

of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands to

the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In

either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided).

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Simplified State Diagram

Power

Applied

Power

Precharge

Preall

Self

Refresh

REFS

REFSX

MRS

EMRS

MRS

Idle

REFA

Auto

Refresh

CKEH

CKEL

Active

Power

Down

CKEH

CKEL

ACT

Precharge

Power

Down

Write

Write A

Write

Row

Active

Burst Stop

Read

Read A

Read

Write A

Read

PRE

Read A

Write

PRE

Read

PRE

Precharge

Preall

Automatic Sequence

Command Sequence

PREALL = Precharge All Banks

MRS = Mode Register Set

EMRS = Extended Mode Register Set

REFS = Enter Self Refresh

REFSX = Exit Self Refresh

REFA = Auto Refresh

CKEL = Enter Power Down

CKEH = Exit Power Down

ACT = Active

Write A = Write with Autoprecharge

Read A = Read with Autoprecharge

PRE = Precharge

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Absolute Maximum Ratings

Symbol

, V

OUT

DDQ

STG

OUT

Parameter

Voltage on I/O pins relative to V

Voltage on Inputs relative to V

Voltage on V

supply relative to V

Voltage on V

DDQ

supply relative to V

Operating Temperature (Ambient)

Storage Temperature (Plastic)

Power Dissipation

Short Circuit Output Current

RatingUnits

−

0.5 to V

DDQ

0.5

−

1.0 to

3.6

−

1.0 to

3.6

−

1.0 to

3.6

0 to

−

55 to

150

1.0

Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rat-

ing only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci-

fication is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Capacitance

Parameter

Input Capacitance: CK, CK

Delta Input Capacitance: CK, CK

Input Capacitance: All other input-only pins (except DM)

Delta Input Capacitance: All other input-only pins (except DM)

Input/Output Capacitance: DQ, DQS, DM

Delta Input/Output Capacitance: DQ, DQS, DM

Symbol

delta CI

delta C

4.0

2.0

Min.

2.0

Max.

3.0

0.25

3.0

0.5

5.0

0.5

Units

Notes

1, 2

1.V

DDQ

= V

= 2.5V ±

0.2V (minimum range to maximum range), f = 100MHz, T

= 25

C, VO

= V

DDQ/2

, VO

Peak -Peak

=0.2V.

gh DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is

required to match input propagation times of DQ, DQS and DM in the system.

DC Electrical Characteristics and Operating Conditions

Symbol

DDQ

REF

IH(DC)

IL(DC)

IN(DC)

ID(DC)

IX(DC)

Ratio

Supply Voltage DDR333

Supply Voltage DDR400

I/O Supply Voltage DDR333

I/O Supply Voltage DDR400

I/O Reference Voltage

I/O Termination Voltage (System)

Input High (Logic1) Voltage

Input Low (Logic0) Voltage

Input Voltage Level, CK and CK Inputs

Input Differential Voltage, CK and CK Inputs

Input Crossing Point Voltage, CK and CK Inputs

V-I Matching Pullup Current to Pulldown Current Ratio

Input Leakage Current

Any input 0V ≤ V

≤

; (All other pins not under test

0V)

Output Leakage Current

(DQs are disabled; 0V ≤ V

out

≤

DDQ

Output Current: Nominal Strength Driver

High current (V

OUT

= V

DDQ

-0.373V, min V

REF

, min V

)

Low current (V

OUT

= 0.373V, max V

REF

, max V

)

Parameter

(0 °C ≤ T

≤ 70 °C; V

DDQ

= V

2.6V

0.1V(DDR400), V

DDQ

= V

2.5V

0.2V(DDR333), see AC Characteristics)

Min

2.3

2.5

2.3

2.5

0.49 x V

DDQ

REF

− 0.04

REF

+ 0.15

− 0.3

0.36

0.30

0.71

− 2

− 5

− 16.2

16.2

Max

2.7

0.51 x V

DDQ

REF

+ 0.04

DDQ

+ 0.3

REF

− 0.15

DDQ

+ 0.3

DDQ

+ 0.6

DDQ

+ 0.6

1.4

Units

Notes

1, 2

1, 3

1, 4

µA

are not recognized as valid until V

REF

stabilizes.

2.V

REF

is expected to be equal to 0.5 V

DDQ

of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak

noise on V

REF

may not exceed ± 2% of the DC value.

3.V

is not applied directly to the device. V

is a system supply for signal termination resistors, is expected to be set equal to V

REF

, and

must track variations in the DC level of V

REF

4.V

is the magnitude of the difference between the input level on CK and the input level on CK.

ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and

voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference

between pullup and pulldown drivers due to process variation.

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Normal Strength Driver Pulldown and Pullup Characteristics

full variation in driver pulldown current from minimum to maximum process, temperature and voltage will lie within the

outer bounding lines of the V-I curve.

is recommended that the “typical” IBIS pulldown V-I curve lie within the shaded region of the V-I curve.

Normal Strength Driver Pulldown Characteristics

140

Maximum

Typical High

Typical Low

Minimum

(

)

OUT

(V)

2.7

full variation in driver pullup current from minimum to maximum process, temperature and voltage will lie within the

outer bounding lines of the V-I curve.

is recommended that the “typical” IBIS pullup V-I curve lie within the shaded region of the V-I curve.

Normal Strength Driver Pullup Characteristics

Minimum

(

)

Typical Low

Typical High

-200

OUT

(V)

2.7

Maximum

full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7, for device drain

to source voltages from 0.1 to 1.0.

full variation in the ratio of the “typical” IBIS pullup to “typical” IBIS pulldown current should be unity + 10%, for device

drain to source voltages from 0.1 to 1.0. This specification is a design objective only. It is not guaranteed.

characteristics are intended to obey the SSTL_2 class II standard.

specification is intended for DDR SDRAM only.

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Normal Strength Driver Pulldown and Pullup Currents

Pulldown Current (mA)

Voltage (V)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

Typical

Low

6.0

12.2

18.1

24.1

29.8

34.6

39.4

43.7

47.5

51.3

54.1

56.2

57.9

59.3

60.1

60.5

61.0

61.5

62.0

62.5

62.9

63.3

63.8

64.1

64.6

64.8

65.0

Typical

High

6.8

13.5

20.1

26.6

33.0

39.1

44.2

49.8

55.2

60.3

65.2

69.9

74.2

78.4

82.3

85.9

89.1

92.2

95.3

97.2

99.1

100.9

101.9

102.8

103.8

104.6

105.4

Min

4.6

9.2

13.8

18.4

23.0

27.7

32.2

36.8

39.6

42.6

44.8

46.2

47.1

47.4

47.7

48.0

48.4

48.9

49.1

49.4

49.6

49.8

49.9

50.0

50.2

50.4

50.5

Max

9.6

18.2

26.0

33.9

41.8

49.4

56.8

63.2

69.9

76.3

82.5

88.3

93.8

99.1

103.8

108.4

112.1

115.9

119.6

123.3

126.5

129.5

132.4

135.0

137.3

139.2

140.8

Typical

Low

-6.1

-12.2

-18.1

-24.0

-29.8

-34.3

-38.1

-41.1

-43.8

-46.0

-47.8

-49.2

-50.0

-50.5

-50.7

-51.0

-51.1

-51.3

-51.5

-51.6

-51.8

-52.0

-52.2

-52.3

-52.5

-52.7

-52.8

Pullup Current (mA)

Typical

High

-7.6

-14.5

-21.2

-27.7

-34.1

-40.5

-46.9

-53.1

-59.4

-65.5

-71.6

-77.6

-83.6

-89.7

-95.5

-101.3

-107.1

-112.4

-118.7

-124.0

-129.3

-134.6

-139.9

-145.2

-150.5

-155.3

-160.1

Min

-4.6

-9.2

-13.8

-18.4

-23.0

-27.7

-32.2

-36.0

-38.2

-38.7

-39.0

-39.2

-39.4

-39.6

-39.9

-40.1

-40.2

-40.3

-40.4

-40.5

-40.6

-40.7

-40.8

-40.9

-41.0

-41.1

-41.2

Max

-10.0

-20.0

-29.8

-38.8

-46.8

-54.4

-61.8

-69.5

-77.3

-85.2

-93.0

-100.6

-108.1

-115.5

-123.0

-130.4

-136.7

-144.2

-150.5

-156.9

-163.2

-169.6

-176.0

-181.3

-187.6

-192.9

-198.2

Normal Strength Driver Evaluation Conditions

Typical

Temperature (T

ambient

)

DDQ

Process conditions

25 °C

2.5V

typical process

Minimum

70 °C

2.3V

slow-slow process

Maximum

0 °C

2.7V

fast-fast process

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

AC Characteristics

(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, I

Specifications and Conditions, and Electrical Characteristics and AC Timing.)

voltages referenced to V

for AC timing, I

, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage

levels, but the related specifications and device operation are guaranteed for the full voltage range specified.

s measured with equivalent load. Refer to the AC Output Load Circuit below.

timing and I

tests may use a V

to V

swing of up to 1.5V in the test environment, but input timing is still referenced

to V

REF

(or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels

under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between V

IL(AC)

and

IH(AC)

AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a

result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above

(below) the DC input low (high) level.

AC Output Load Circuit Diagrams

50Ω

Output

OUT

)

Timing Reference Point

30pF

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

AC Input Operating Conditions

SymbolParameter/Condition

(0 °C ≤ T

≤ 70 °C; V

DDQ

= V

2.6V

0.1V(DDR400), V

DDQ

= V

2.5V

0.2V(DDR333); See AC Characteristics)

Min

REF

+ 0.31

MaxUnit

Notes

1, 2

1, 2, 3

1, 2, 4

IH(AC)

Input High (Logic 1) Voltage, DQ, DQS, and DM Signals

IL(AC)

Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals

ID(AC)

Input Differential Voltage, CK and CK Inputs

IX(AC)

Input Crossing Point Voltage, CK and CK Inputs

REF

− 0.31

0.7

0.5*V

DDQ

− 0.2

DDQ

+ 0.6

0.5*V

DDQ

+ 0.2

Input slew rate = 1V/ns.

Inputs are not recognized as valid until V

REF

stabilizes.

is the magnitude of the difference between the input level on CK and the input level on CK.

The value of V

is expected to equal 0.5*V

DDQ

of the transmitting device and must track variations in the DC level of the same.

Specifications and Conditions

Symbol

(0 °C ≤ T

≤ 70 °C; V

DDQ

= V

2.6V

0.1V(DDR400), V

DDQ

= V

2.5V

0.2V(DDR333); See AC Characteristics)

Parameter/Condition

Operating Current: one bank; active / precharge; t

= t

(min); DQ, DM, and

DQS inputs changing twice per clock cycle; address and control inputs changing

once per clock cycle

Operating Current: one bank; active / read / precharge; Burst = 2; t

= t

(min);

CL = 2.5;

OUT

= 0mA; address and control inputs changing once per clock cycle

x4/x8

x16

x4/x8

x16

DDR333DDR400(

5T)(6K)

=6nst

=5ns

4.6

115

120

175

x4/x8

x16

205

230

110

4.6

135

190

230

250

Unit

Note

DD0

DD1

DD2P

DD2F

DD2Q

DD3P

DD3N

Precharge Power Down Standby Current: all banks idle; Power Down mode; CKE ≤ V

(max)

Idle Standby Current: CS ≥ V

(min); all banks idle; CKE ≥ V

(min);

address and control inputs changing once per clock cycle

Precharge floating standby current: CS ≥ V

(min); all banks idle; CKE ≥ V

(min);

address and control inputs changing once per clock cycle

Active Power Down Standby Current: one bank active; Power Down mode; CKE ≤ V

(max)

Active Standby Current: one bank; active / precharge; CS ≥ V

(min);

CKE ≥ V

(min); t

= t

RAS

(max); DQ, DM, and DQS inputs changing twice per

clock cycle; address and control inputs changing once per clock cycle

Operating Current: one bank; Burst = 2; reads; continuous burst; address and

control inputs changing once per clock cycle; DQ and DQS outputs changing twice

per clock cycle; CL = 2.5; I

OUT

= 0mA

Operating Current: one bank; Burst = 2; writes; continuous burst; address and

control inputs changing once per clock cycle; DQ and DQS inputs changing twice

per clock cycle; CL = 2.5

Auto-Refresh Current: t

= t

RFC

(min)

Self-Refresh Current: CKE ≤ 0.2V

Operating current: four bank; four bank interleaving with BL = 4, address

and con-

trol inputs randomly changing; 50% of data changing at every transfer;

= t

(min); I

OUT

= 0mA.

x4/x8

x16

x4/x8

x16

x4/x8

x16

DD4R

DD4W

DD5

DD6

DD7

1, 2

1.I

specifications are tested after the device is properly initialized.

s on-chip refresh and address counters.

Values are averaged from high and low temp values using x16 devices.

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Electrical Characteristics & AC Timing - Absolute Specifications

Symbol

Parameter

DQ output access time from CK/CK

DDR333 (6K)

Min

- 0.7

- 0.6

0.45

CL = 3.0

CL = 2.56

0.45

2.2

1.75

+ 0.7

- 0.7

TSOP Package

BGA Package

min

, t

)

- t

QHS

TSOP Package

BGA Package

Write command to 1st DQS latching

transition

DQS input high pulse width (write cycle)

DQS input low pulse width (write cycle)

DQS falling edge to CK setup time (write cycle)

DQS falling edge hold time from CK (write cycle)

Mode register set command cycle time

0.75

0.35

0.2

0.4

0.25

0.75

0.8

0.9

0.4

0.6

70,000

0.6

0.55

0.5

1.250.72

0.35

0.2

0.40

max(0.25

tCK, 1.5ns)

0.6

0.7

0.9

0.4

1.1

0.6

70,000

0.60

+ 0.7

+ 0.45

+ 0.4

min

, t

)

- t

QHS

0.5

1.25

− 0.7

0.4

2.2

1.75

+ 0.7

+ 0.4

5, 10-12

5, 11-13

1,2

Max

+ 0.7

+ 0.6

0.55

DDR400 (5T)

Min

− 0.7

− 0.6

0.45

Max

+ 0.7

+ 0.6

0.55

7.5

(0 °C ≤ T

≤ 70 °C; V

DDQ

= V

2.6V

0.1V(DDR400), V

DDQ

= V

2.5V

0.2V(DDR333); See AC Characteristics)

Unit

Notes

DQSCK

DQS output access time from CK/CK

IPW

DIPW

CK high-level width

CK low-level width

Clock cycle time

DQ and DM input hold time

DQ and DM input setup time

Input pulse width

DQ and DM input pulse width (each input)

Data-out high-impedance time from CK/CK

Data-out low-impedance time from CK/CK

DQSQ

DQS-DQ skew

(DQS & associated DQ signals)

QHS

DQSS

DQSH

DQSL

DSS

DSH

MRD

Minimum half clk period for any given cycle;

defined by clk high (t

) or clk low (t

) time

Data output hold time from DQS

Data hold Skew Factor

WPRES

Write preamble setup time

WPST

Write postamble

WPRE

Write preamble

RPRE

RPST

RAS

Address and control input hold time

(fast slew rate)

Address and control input setup time

(fast slew rate)

Address and control input hold time

(slow slew rate)

Address and control input setup time

(slow slew rate)

Read preamble

Read postamble

Active to Precharge command

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Electrical Characteristics & AC Timing - Absolute Specifications

Symbol

RFC

RCD

RAP

RRD

DAL

WTR

XSNR

XSRD

REFI

Parameter

Active to Active/Auto-refresh command period

Auto-refresh to Active/Auto-refresh command period

Active to Read or Write delay

Active to Read Command with Autoprecharge

Precharge command period

Active bank A to Active bank B command

Write recovery time

Auto precharge write recovery + precharge time

Internal write to read command delay

Exit self-refresh to non-read command

Exit self-refresh to read command

Average Periodic Refresh Interval

DDR333 (6K)

Min

min

RCD

, t

RAS

)

200

7.8

Max

DDR400 (5T)

Min

min

RCD

, t

RAS

)

200

7.8

Max

(0 °C ≤ T

≤ 70 °C; V

DDQ

= V

2.6V

0.1V(DDR400), V

DDQ

= V

2.5V

0.2V(DDR333); See AC Characteristics)

Unit

µs4, 17

Notes

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

(tCL, tCH) referes to the smaller of the actual clock low time and actual clock high time as provided to the

device. (i.e. this value can be greater than the minimum specification limits for tCL and tCH).

= tHP - tQHS, where tHP = minimum half clock period for any given cycle and is defined by clock high or

clock low (tCH, tCL). tQHS accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2) The

worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition,

both of which are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel

variation of the output drivers.

only time that the clock frequency is allowed to change is during self-refresh mode.

refresh time or tDS/tDH is viloated, data corruption may occur and the data must be re-written with valid

data before a valid READ can be executed.

parameters quarantee device timing, but they are not necessarily tested on each device. They may be

guaranteed by device design or tester correlation.

and tLZ transitions occur in the same access time windows as valid data transitions. These parameters

are reference to a specific voltage level that specifies when the device output is no longer driving (tHZ) or

begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement points

are not critical as long as the calculation is consistent.

consists of datapin skew and output pattern effects and p-channel to n-channel variation of the output

drivers for any given cycle.

specific requirement is that DQS be valid (High, Low, or at same point on a valid transition) on or before

this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the

device. When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic

Low. If a previous write was in process, DQS could be HIGH, LOW, or transitioning from High to Low at this

time, depending on DQSS.

maximum limit for this parameter is not a device limit. The device will operate with a greater value for this

parameter, but system performance (bus turn-arround) will degrade accordingly.

command/address input slew rate >= 1.0V/ns.

CK & CK slew rate >= 1.0V/ns (single-ended).

Rate is measured between VOH(ac) and VOL(ac).

command/address input slew rate >= 0.5V/ns and <1.0V/ns.

end point and tRPRE begin point are not reference to a specific voltage level but specify when the

device output is no longer driving (tRPRE) by measuring the signal at two different voltages. The actual

voltage measurement points are not critical as long as the calculation is consistent.

= (tWR/tCK) + (tRP/tCK)

all circumstances, tXSNR can be satisfied using tXSNR = tRFCmin + 1*tCK.

17.A maximum of eight Auto Refresh commands can be posted to any given DDR SDRAM.

Component Notes

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Data Input (Write)

(Timing Burst Length = 4)

DSL

DSH

DQS

DI n

DI n = Data In for column n.

3 subsequent elements of data in are applied in programmed order following DI n.

Don’t Care

Data Output (Read)

(Timing Burst Length = 4)

DQS

DQSQ

QH1

DQSQ

QH2

DQSQ

QH3

QH4

HP1

HP2

HP3

HP4

is the half cycle pulse width for each half cycle clock. t

is referenced to the clock duty cycle only

and not to the data strobe (DQS) duty cycle.

Data Output hold time from Data Strobe is shown as t

. t

is a function of the clock high or low time (t

)

for that given clock cycle. Note correlation of t

to t

in the diagram above (t

HP1

to t

QH1

, etc.).

DQSQ

(max) occurs when DQS is the earliest among DQS and DQ signals to transition.

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

512Mb DDR SDRAM

Dec 2007

REV 1.0

(

)

Initialize and Mode Register Sets

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

’

(

)

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

Power Down Mode

512Mb DDR SDRAM

Dec 2007

REV 1.0

’

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

(

)

(

)

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

512Mb DDR SDRAM

Dec 2007

REV 1.0

Auto Refresh Mode

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

(

)

;

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

’

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

512Mb DDR SDRAM

Dec 2007

REV 1.0

Self Refresh Mode

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

(

)

’

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

512Mb DDR SDRAM

Dec 2007

REV 1.0

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

Read without Auto Precharge (Burst Length = 4)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

’

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

;

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

512Mb DDR SDRAM

Dec 2007

REV 1.0

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

Read with Auto Precharge (Burst Length = 4)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

;

’

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

512Mb DDR SDRAM

Dec 2007

REV 1.0

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

Bank Read Access (Burst Length = 4)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

;

’

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

512Mb DDR SDRAM

Dec 2007

REV 1.0

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

Write without Auto Precharge (Burst Length = 4)

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

;

’

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

512Mb DDR SDRAM

Dec 2007

REV 1.0

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

Write with Auto Precharge (Burst Length = 4)

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

;

’

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

512Mb DDR SDRAM

Dec 2007

REV 1.0

Bank Write Access (Burst Length = 4)

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

;

’

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

512Mb DDR SDRAM

Dec 2007

REV 1.0

Write DM Operation (Burst Length = 4)

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

(

)

;

’

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Package Dimensions

(60 balls; 0.8mmx1.0mm Pitch; wBGA Package)

10.0

6.40

0.80

Dia.

0.40 min.

0.50 max.

0.25 min.

0.40 max.

1.20 max.

Note : All dimensions are typical unless otherwise stated.

Unit : Millimeters

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Package Dimensions

(400mil; 66 lead TSOP Package)

0.127

9.600 +/- 0.050

22.22 +/- 0.10

Unit: mm

7 Max.

0.50 +/- 0.10

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

0.710.650.30

-0.08

+0.03

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Revision Log

Rev

0.1

0.2

0.3

1.0

Date

Jan 2004

Dec 2007

Preliminary Release

Support NT5DS64M8CG, NT5DS64M8CS, NT5DS32M16CG, NT5DS32M16CS

Support NT5DS128M4CS

Official Release

Modification

REV 1.0

Dec 2007

NANYA TECHNOLOGY CORP

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

NT5DS32M16CG

NT5DS64M8CG

NT5DS128M4CG

NT5DS32M16CS

NT5DS64M8CS

NT5DS128M4CS

512Mb DDR SDRAM

Nanya Technology Corporation.

Printed in Taiwan, R.O.C.

The following are trademarks of NANYA TECHNOLOGY CORPORATION: NANYA and the NANYA logo

Other company, product and service names may be trademarks or service marks of others.

NANYA TECHNOLOGY CORPORATION (NTC) reserves the right to make changes without notice. NTC warrants performance

of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with NTC’s

standard warranty. Testing and other quality control techniques are utilize to the extent NTC deems necessary to support this

warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government

requirements.

Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or

environmental damage (“Critical Applications”).

NTC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTEND, AUTHORIZED, OR WARRANTED TO BE SUITABLE

FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.

Inclusion of NTC products in such applications is understood to be fully at the risk of the customer. Use of NTC products in such

applications requires the written approval of an appropriate NTC officer. Question concerning potential risk applications should

be directed to NTC through a local sales office.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards should be

provided by customer to minimize the inherent or procedural hazards.

NTC assumes no liability of applications assistance, customer product design, software performance, or infringement of patents

or services described herein. Nor does NTC warrant or represent that any license, either express or implied, is granted under

any patent right, copyright, mask work right, or other intellectual property right of NTC covering or relating to any combination,

machine, or process in which such semiconductor products or services might be or are used.

NANYA TECHNOLOGY CORPORATION

HWA YA Technology Park

669, FU HSING 3rd Rd., Kueishan,

Taoyuan, Taiwan, R.O.C.

The NANYA TECHNOLOGY CORPORATION home page can be found at: http: