ZingOEM开发板硬件手册-USB迷|专注于互联网分享

2024年2月20日发(作者：公含之)

ZingOEM平台硬件用户手册

Ver:1.0

ZingOEM平台硬件用户手册

修订记录

版本修订日期修订内容

0.9

2012年9月17日用户手册初始版本

1.0

2012年10月20日更新内容和统一格式

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ZingOEM平台硬件用户手册

修订记录 ............................................................................................................................................ - 2 -

1 产品概述 ........................................................................................................................................ - 4 -

2 相关文档 ........................................................................................................................................ - 5 -

3 结构框图 ........................................................................................................................................ - 6 -

4 配套信息 ........................................................................................................................................ - 7 -

5 开发板硬件资源............................................................................................................................. - 8 -

5.1 Zynq-7000 XC7Z020-1CLG484芯片 ...................................................................................... - 9 -

5.2 DDR3内存颗粒 ..................................................................................................................... - 10 -

5.2 系统时钟源 ........................................................................................................................... - 13 -

5.4 SDIO连接器 .......................................................................................................................... - 14 -

5.5 USB2.0 ULPI收发器 ............................................................................................................. - 15 -

5.6 10/100/1，000 MHz的三速以太网口 .................................................................................. - 18 -

5.7 USB_UART接口 ................................................................................................................... - 19 -

5.8 CAN总线接口 ....................................................................................................................... - 20 -

5.9 I2C总线接口.......................................................................................................................... - 20 -

5.10 RTC实时时钟 ...................................................................................................................... - 21 -

5.11 XADC接口 .......................................................................................................................... - 22 -

5.12 FMC连接器 ......................................................................................................................... - 23 -

5.13 HDMI接口 ........................................................................................................................... - 25 -

5.14 用户I/O ............................................................................................................................... - 27 -

6 Zing开发板UCF列表 ................................................................................................................. - 29 -

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ZingOEM平台硬件用户手册

1 产品概述

Zing是一块由北京威视锐公司推出的基于赛灵思可扩展处理平台架构的高性能开发板。它使用了赛灵思最新推出的Zynq-7000系列芯片，它采用28nm制程工艺，具有高性能、低功耗等特点，其最主要的特色是将双核ARM® Cortex™-A9（处理器系统PS）和赛灵思的可编程逻辑（可编程逻辑PL）集成到一个单独芯片上。从而将ARM®处理系统和与Xilinx 7系列可编程逻辑完美地结合在一起，使用户可以创建独特而强大的设计。

其中，处理器系统PS部分除了包括双核的A9内核外，还包括了片上存储器、外部存储器接口和一系列丰富的I/O外设。这些外设主要包括DDR3颗粒内存、JTAG接口、UART接口、USB接口、CAN总线接口、I2C总线接口、SPI总线接口、XADC接口、TF卡插槽和以太网接口等。而可编程逻辑PL部分则是提供了更好的灵活性和可扩展性，它可以根据用户定制的逻辑完成信号的实时处理和高速传输。

基于Zing的产品特色，它的应用范围主要包括几个领域：

● 工业控制、工业网络、机器视觉；

● 智能相机；

● 多功能打印机；

● 医疗诊断和成像；

● 汽车驾驶辅助设备和信息娱乐；

● 视频和夜视设备；

● LTE射频和基带。

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ZingOEM平台硬件用户手册

2 相关文档

 Zing开发板硬件手册

 Zing开发板实验教程

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ZingOEM平台硬件用户手册

3 结构分布框图

CAN 总线USB_UARTTF卡USB2.0Ethernet1000MPower

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PL_PJTAGHDMIXADCRTCZYNQXC7Z020EPP33MHz时钟用户按键和拨码开关用户LED灯50MHz时钟DDR4DDR3DDR2DDR150MHz时钟JTAGFMC2FMC1

Zing开发板结构分布框图

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ZingOEM平台硬件用户手册

4 配套信息

ZingOEM产品清单

项目内容数量

Zing开发板 1块

Red-Cable-USB下载电缆 1套

Mini USB2.0电缆 1条

配套DVD光盘 1张

USB2.0电缆 1条

电源适配器 1个

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ZingOEM平台硬件用户手册

5 开发板硬件资源

下图5.1为Zing开发板硬件资源分布图。

图5.1 Zing开发板硬件资源分布图

根据图5.1，我们将Zing开发板的硬件资源总结如下：

● Zynq-7000 XC7Z020-1CLG484C EPP；

● 1GB的DDR3内存颗粒（4个256Mb×8装置）；

● 时钟源：

固定的33.33MHz LVCMOS晶振；

固定的50MHz LVCMOS晶振；

● USB2.0 ULPI收发器；

● TF卡连接器；

● CAN总线收发器；

● I2C总线，它主要多路复用于以下模块：

SiI9134CTU HDMI接口；

24LC02 EEPROM(1KB)；

RTC-8564JE 实时时钟；

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ZingOEM平台硬件用户手册

● USB-to-UART接口；

● 带有RJ45连接器的千兆以太网接口；

● HDMI接口；

● 两个FMC LPC I/O扩展接口；

● 4个LED灯，分别为DU1、DU2、DU3、DU4；

● 按键（PD1、PD2、PU1、PU2）和拨码开关(PD3、PD4)；

● XADC连接器、JTAG接口等。

以下我们将分别详细介绍这些硬件资源的主要特点。

5.1 Zynq-7000 XC7Z020-1CLG484芯片

Zing开发板使用了XC7Z020-1CLG484C Zynq-7000 EPP芯片。XC7Z020 EPP将SoC集成处理系统（PS）和可编程逻辑器件（PL）包含在单个芯片上。Zing开发板中的XC7Z020 EPP芯片的总体方框图如图5.2所示，其中，PS集成了两个ARM®的Cortex™-A9 MPCore的™应用处理器，AMBA®互连，内部存储器，外部存储器接口和外设。这些外设主要包括USB总线接口，以太网接口，SD/ SDIO接口，I2C总线接口，CAN总线接口，UART接口，GPIO等。PS可以独立运行并在上电或复位下启动。

图5.2 XC7Z020 EPP芯片的总体方框图

它的系统级方框图如图5.3所示，

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图5.3 XC7Z020 EPP芯片的系统级方框图

5.2 DDR3内存颗粒

DDR3是一种电脑内存规格。它属于SDRAM家族的内存产品，提供了相较于DDR2 SDRAM更高的运行效能与更低的电压，是DDR2 SDRAM（四倍资料率同步动态随机存取内存）的后继者（增加至八倍），也是现时流行的内存产品。

Zing开发板使用了型号为MT41J256M8HX_15E的DDR3存储系统。它由4片内存颗粒组成（共计1GB），总线宽度为32bit。该存储系统直接连接到了XC7Z020 EPP处理系统（PS）的bank502的存储器接口上。

其原理图如图5.4所示，

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DGNDRM1VTTVREF_PSZingOEM平台硬件用户手册

1.5V_PS240UM1K3L7L3K2L8L2M8M2N8M3H7M7K7N3N7J2K8J3H3F3G3F7G7G9ZQVREFCAVREFDQVDDQ1VDDQ2VDDQ3VDDQ4VDD1VDD2VDD3VDD4VDD5VDD6VDD7VDD8VDD9A2A9D7G2G8K1K9M1M9H8B9C1E2E9J8E1PS_DDR3_A0PS_DDR3_A1PS_DDR3_A2PS_DDR3_A3PS_DDR3_A4PS_DDR3_A5PS_DDR3_A6PS_DDR3_A7PS_DDR3_A8PS_DDR3_A9PS_DDR3_A10PS_DDR3_A11PS_DDR3_A12PS_DDR3_A13PS_DDR3_A14PS_DDR3_BA0PS_DDR3_BA1PS_DDR3_BA2PS_DDR3_WE_BPS_DDR3_RAS_BPS_DDR3_CAS_BPS_DDR3_CLK_PPS_DDR3_CLK_NPS_DDR3_CKEA0A1A2A3A4A5A6A7A8A9A10A11A12A13A14BA0BA1BA2WE_BRAS_BCAS_BCKCK_BCKERESET_BODTDQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7B3

E3E8D2E7PS_DDR3_DQ0PS_DDR3_DQ1PS_DDR3_DQ2PS_DDR3_DQ3PS_DDR3_DQ4PS_DDR3_DQ5PS_DDR3_DQ6PS_DDR3_DQ7MT41J256M8HX_15EDQSDQS_BDM_TDQSNF_TDQS_BC3D3B7A7PS_DDR3_DQS0_PPS_DDR3_DQS0_NPS_DDR3_DM0PS_DDR3_RESET_BN2PS_DDR3_ODTPS_DDR3_CS_BG1H2VSSQ1VSSQ2VSSQ3VSSQ4VSSQ5CS_BB2B8C9D1D9A1

VSS1VSS2VSS3VSS4VSS5VSS6VSS7VSS8VSS9VSS10VSS11VSS12NC1NC2NC3NC4NC5NC6A3F1F9H1H9J7DGND

图5.4 DDR3内存颗粒原理图

DDR3的管脚列表如表5.1所示，

表5.1 DDR3管脚列表

XC7Z020管脚

管脚名称

PS_DDR3_DQ0

PS_DDR3_DQ1

PS_DDR3_DQ2

PS_DDR3_DQ3

PS_DDR3_DQ4

PS_DDR3_DQ5

PS_DDR3_DQ6

PS_DDR3_DQ7

PS_DDR3_DQ8

PS_DDR3_DQ9

PS_DDR3_DQ10

PS_DDR3_DQ11

PS_DDR3_DQ12

DDR3 管脚

管脚名称

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

参考标示

UM1

UM2

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参考标示

UM2

UM3

UM4

UM1

UM2

UM3

UM4

UM1，UM2，UM3，UM4

XC7Z020管脚

AA1

AA3

AA2

管脚名称

PS_DDR3_DQ13

PS_DDR3_DQ14

PS_DDR3_DQ15

PS_DDR3_DQ16

PS_DDR3_DQ17

PS_DDR3_DQ18

PS_DDR3_DQ19

PS_DDR3_DQ20

PS_DDR3_DQ21

PS_DDR3_DQ22

PS_DDR3_DQ23

PS_DDR3_DQ24

PS_DDR3_DQ25

PS_DDR3_DQ26

PS_DDR3_DQ27

PS_DDR3_DQ28

PS_DDR3_DQ29

PS_DDR3_DQ30

PS_DDR3_DQ31

PS_DDR3_DM0

PS_DDR3_DQS0_P

PS_DDR3_DQS0_N

PS_DDR3_DM1

PS_DDR3_DQS1_P

PS_DDR3_DQS1_N

PS_DDR3_DM2

PS_DDR3_DQS2_P

PS_DDR3_DQS2_N

PS_DDR3_DM3

PS_DDR3_DQS3_P

PS_DDR3_DQS3_N

PS_DDR3_A0

PS_DDR3_A1

PS_DDR3_A2

PS_DDR3_A3

PS_DDR3_A4

PS_DDR3_A5

PS_DDR3_A6

PS_DDR3_A7

PS_DDR3_A8

DDR3 管脚

管脚名称

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DM0

DQS0_P

DQS0_N

DM1

DQS1_P

DQS1_N

DM2

DQS2_P

DQS2_N

DM3

DQS3_P

DQS3_N

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ZingOEM平台硬件用户手册

参考标示

UM1，UM2，UM3，UM4

XC7Z020管脚

管脚名称

PS_DDR3_A9

PS_DDR3_A10

PS_DDR3_A11

PS_DDR3_A12

PS_DDR3_A13

PS_DDR3_A14

PS_DDR3_BA0

PS_DDR3_BA1

PS_DDR3_BA2

PS_DDR3_CLK_P

PS_DDR3_CLK_N

PS_DDR3_CKE

PS_DDR3_WE_B

PS_DDR3_CAS_B

PS_DDR3_RAS_B

PS_DDR3_RESET_B

PS_DDR3_CS_B

PS_DDR3_ODT

PS_VRN

PS_VRP

VTTVREF_PS

DDR3管脚

管脚名称

A10

A11

A12

A13

A14

BA0

BA1

BA2

CK_B

CKE

WE_B

CAS_B

RAS_B

RESET_B

CS_B

ODT

5.2 系统时钟源

Ziing开发板为XC7Z020EPP提供了三个时钟源，如表5.2所示。

表5.2 Ziing开发板时钟源列表

时钟名称

SYSCLK

USRCLK

PS_CLK

这三个时钟源的原理图分别如图5.5，图5.6和图5.7所示，

1.8VFBX1BLM21PG331SN1D4CX10.1uF2X1VCCOUTGNDNC33.3333MHzDGND3331RX9PS_CLK时钟源

相关描述

3.3V供电，单端，50MHz时钟源

1.8V供电，单端，33.33MHz时钟源

PS_CLK

图5.5 PS的系统时钟

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3.3VFBX4BLM21PG331SN1D4CX20.1uF2X2VCCOUTGNDNC50MHzDGND3331RX10ZingOEM平台硬件用户手册

SYSCLK_P

图5.6 PL的系统时钟

3.3VFBX5BLM21PG331SN1D4CX70.1uF2X3VCCOUTGNDNC50MHzDGND3331RX11USRCLK_P

图5.7 PL的用户时钟

这三个时钟的管脚列表如表5.3所示，

表5.3 Zing开发板的系统时钟源

时钟源管脚

X1.3

X2.3

X3.3

信号名称

PS_CLK

SYSCLK_P

USRCLK_P

XC7Z020管脚

D18

5.4 SDIO连接器

Zing开发板中包括一个安全数字输入/输出（SDIO）接口，以提供用户逻辑访问通用的非易失性SDIO存储卡和外围设备。SDIO信号被连接到了XC7Z020 EPP 中PS 501BANK，该BANK的VCCMIO设置为1.8V。

SDIO连接器的原理图如图5.8所示，

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UM6VCCMIO5SDIO_DAT0_LSSDIO_DAT1_LSSDIO_DAT2_LSSDIO_CD_DAT3_LSSDIO_CMD_LS67134VCCADAT0ADAT1ADAT2ADAT3ACMDAVCCB0VCCB1DAT0B0DAT0B1DAT1B0DAT1B1DAT2B0DAT2B1DAT3B0DAT3B1CMDB0CMDB1CLKB0CLKB15238221.3VZingOEM平台硬件用户手册

JM1TF01ASDIO_DAT0SDIO_DAT1SDIO_DAT2SDIO_CD_DAT3SDIO_CMDSDIO_DAT2SDIO_CD_DAT3SDIO_CMDSDIO_CLK3.3VSDIO_DAT0SDIO_DAT1SDIO_SDDETDAT2DAT3CMDVCCCLKVSSDAT0DAT1GNDCDSh1Sh2Sh31112139SDIO_CLK_LS4.7K24DGNDRM30DGND211SDIO_CLKCLKASELGND1GND2TXS02612RTWRPAD25DGNDSDIO_CMDSDIO_SDDETRM38RM393.3V68K10K3.3VVCCMIO_PSVCCMIOCM810.1uFDGND3.3VCM780.1uFDGND3.3VCM790.1uFDGNDDGNDCM800.1uF

图5.8 SDIO连接器的原理图

其管脚列表如表5.4所示，

表5.4 SDIO连接器管脚列表

XC7Z020管脚

管脚名称

PS_MIO0

PS_MIO41

PS_MIO40

PS_MIO44

PS_MIO43

PS_MIO42

PS_MIO45

BANK

500

501

管脚号

E14

E13

B11

信号名称

SDIO_SDDET

SDIO_CMD_LS

SDIO_CLK_LS

SDIO_DAT2_LS

SDIO_DAT1_LS

SDIO_DAT0_LS

SDIO_CD_DAT3_LS

电平转换器(UM6)

管脚号

N/A

管脚名称

N/A

CMDA

CLKA

DAT2A

DAT1A

DAT0A

DAT3A

SDIO连接器(JM1)

管脚号

管脚名称

CMD

CLK

DAT2

DAT1

DAT0

DAT3

5.5 USB2.0 ULPI收发器

Zing开发板使用了标准的USB2.0收发器，支持USB连接到主机。其中A型口连接到主机，B型口则连接到Zing开发板的JB1端口上。该USB是一个高速的物理层支持UTMI+低引脚接口（ULPI）的接口标准。该ULPI标准定义了USB控制器IP和PHY设备（驱动USB物理总线）之间的接口。ULPI标准的使用，减少了USB控制器IP和PHY设备之间的接口引脚数。

USB3320C-EZK收发器的接口是通过存在于XC7Z020 EPP处理器系统中的IP来实现的。该收发器由一个24MHz的晶振提供时钟，其原理图下图5.9所示，

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18pFCB1ZingOEM平台硬件用户手册

USB_RESET_BUSB_STPUSB_DIRVCCMIOVCCMIOVCCMIO1MRB5YB124.000MHz18pFCB2323EFCLK_26UB1USB_CLKOUTUSB_NXTUSB_DATA0USB_DATA1USB_DATA2USB_DATA3USB_DATA4VCCMIO12345678STP_29DIR_31RESETB_27VDD18_30VDD18_28VDDIO_32XO_2525CLKOUT_1NXT_2DATA0_3DATA1_4DATA2_5DATA3_6DATA4_7RBIAS_23ID_23VBUS_22VBAT_21VDD33_PDM_19DP_019181733DGNDUSB_ID8.06KRB1DGND5VUSB_VDD33USB_D_NUSB_D_PREFSEL1_11REFSEL2_14REFSEL0_8CPEN33_17DATA6_10DATA7_13SPK_R_16SPK_L_15DATA5_9NC_12CTR_GND_331VCCMIOVCCMIOUSB_DATA5USB_DATA6USB_DATA7169USB3320C-EZK

图5.9 USB3320C-EZK收发器原理图

该USB的管脚列表如表5.5所示，

表5.5 USB的管脚列表

XC7Z020

管脚名称

PS_MIO36

PS_MIO31

PS_MIO32

PS_MIO33

PS_MIO34

PS_MIO35

PS_MIO28

PS_MIO37

PS_MIO38

PS_MIO39

PS_MIO30

PS_MIO29

PS_MIO7

BANK

501

500

管脚号

G13

B12

F14

A12

B14

F13

C13

A11

信号名称

USB_CLKOUT

USB_NXT

USB_DATA0

USB_DATA1

USB_DATA2

USB_DATA3

USB_DATA4

USB_DATA5

USB_DATA6

USB_DATA7

USB_STP

USB_DIR

USB_RESET_B_AND

USB3320（UB1）管脚

27（经UB3的AND门）

USB连接器的管脚功能如表5.6所示，

表5.5 USB的管脚功能表

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ZingOEM平台硬件用户手册

USB3320(UB1)管脚

USB连接器

管脚

管脚名称

VBUS

D_N

D_P

GND

信号名称

USB_VBUS_SEL

USB_D_N

USB_D_P

GND

描述

来自主机的+5V电压

双向差分串行数据的N端

双向差分串行数据的P端

信号地

该USB设备在是使用时需要对其进行跳线设置，以满足用户不同的开发要求，其跳线原理图如图5.10所示，

USB_VBUS_SELRB25VJB610K1231-2 DEVICE MODE2-3 HOST OR OTG MODEDGNDSIP312USB_VBUS_SELSIP2ECB1+OUT1INOUT2NC28765150uF5VDGND5VVCCMIOCB30.1uFDGNDUSB_VBUS_SELFBB1CB105.6uFFBB2DGNDJB41USB_ID23USB_VDD33CB122.2uFDGNDSIP31-2 = A/B CABLE DETECT2-3 = ID NOT USEDVCCMIODGNDJB1BLM21P221SNCB90.1uFBLM21P221SNUSB2.0-ABCB80.1uFDGNDUSB_D_NUSB_D_P123456JB312SIP2DGND1KUSB_RESET_B_ANDPS_POR_BRB6VCCMIO1365VCCABCGND2SN74LVC1G11DCKRY4USB_RESET_BJB2ON = HOST OR OTG MODEOFF = DEVICE MODECB40.1uFRB31KUB23.3VRB4LEDDB1261RedDGND1234ENFLGGNDNCMIC2025-1BMDGNDJB5123SIP31uFCB11ECB2+UB3CVBUS Select:120uF1-2: OTG Mode2-3: Host ModeDGND

图5.10 USB设备跳线设置原理图

USB设备的跳线设置及功能如表5.6所示，

表5.6 USB设备的跳线设置及功能表

跳线

JB3

JB4

JB5

JB6

功能

USB 复位

电缆 ID 设置

CVBUS 模式选择

RVBUS模式选择

跳线设置

ON = USB 复位

OFF= USB 正常工作

1-2 = A/B 型电缆探测

2-3 = 不使用该ID

1-2 = OTG模式

2-3 = Host模式

1–2 = Device模式

2–3 = Host or OTG模式

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ZingOEM平台硬件用户手册

跳线设置

ON = Host or OTG模式

OFF = Device模式

跳线

JB2

功能

Host/OTG 或 device模式选择

5.6 10/100/1，000 MHz的三速以太网口

Zing开发板板采用Marvell Alaska的PHY装置（88E1111），它支持10 MB/ s，100 Mb / s或1000

Mb / s的以太网通讯。本板卡只支持RGMII模式。该以太网口的原理图如图5.11所示，

UE1-1VCCMIORE264.7KPHY_MDIOPHY_MDCJE1VCCMIORE1DGND1KPHY_TX_CLKPHY_TX_CTRLPHY_TXD3PHY_TXD2PHY_TXD1PHY_TXD0PHY_RX_CLKPHY_RX_CTRLPHY_RXD3PHY_RXD2PHY_RXD1PHY_RXD54515RE3RE41K1K5710MDIOMDCTX_CLKTX_CTRLTXD3TXD2TXD1TXD0RX_CLKRX_CTRLRXD3RXD2RXD1RXD0CONFIIG3CONFIIG2CONFIIG1CONFIIG0XTAL_INXTAL_OUTCOMA_BVREFRESET_BTCKTMSTDITDORSETCTRL18DIS_REG12LED0LED1LED2HSDAC_PHSDAC_NTSTPTTRST_B33321142414344RE54.99KDGNDMDI0_PMDI0_NMDI1_PMDI1_NMDI2_PMDI2_NMDI3_PMDI3_N3139PHY_MDI0_PPHY_MDI0_NPHY_MDI1_PPHY_MDI1_NPHY_MDI2_PPHY_MDI2_NPHY_MDI3_PPHY_MDI3_N123SIP3JE2123PHY_LED1PHY_LED0VCCMIOPHY_LED0SIP3JE3123PHY_LED0PHY_LED1PHY_LED2PHY_HSDAC_PPHY_HSDAC_N12JE5SIP3JE412PHY_LED0VCCMIORE21KSIP2DGNDVCCMIODGNDPHY_XTAL_INPHY_XTAL_OUTSIP2PHY_RESET_BCE118pFPHY_XTAL_IN4.7KNCNCYE125.000MHzCE218pFPHY_XTAL_OUT88E1116RRE8RE6RE7DGND

图5.11 三速以太网口的原理图

三速以太网口的管脚列表如表5.7所示，

表5.7 三速以太网口的管脚列表

XC7Z020 EPP

管脚名称

PS_MIO53

PS_MIO52

PS_MIO16

PS_MIO21

PS_MIO20

PS_MIO19

PS_MIO18

BANK

501

管脚号

C12

D10

F11

E10

信号名称

PHY_MDIO

PHY_MDC

PHY_TX_CLK

PHY_TX_CTRL

PHY_TXD3

PHY_TXD2

PHY_TXD1

M88E1116R PHY(UE1-1)

管脚号

管脚名称

MDIO

MDC

TX_CLK

TX_CTRL

TXD3

TXD2

TXD1

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ZingOEM平台硬件用户手册

M88E1116R PHY(UE1-1)

管脚号

管脚名称

TXD0

RX_CLK

RX_CTRL

RXD3

RXD2

RXD1

RXD0

XC7Z020 EPP

管脚名称

PS_MIO17

PS_MIO22

PS_MIO27

PS_MIO26

PS_MIO25

PS_MIO24

PS_MIO23

BANK

501

管脚号

A14

A13

F12

E11

信号名称

PHY_TXD0

PHY_RX_CLK

PHY_RX_CTRL

PHY_RXD3

PHY_RXD2

PHY_RXD1

PHY_RXD0

5.7 USB_UART接口

Zing开发板中包含一个Silicon Labs公司的CP2103GM USB-UART桥接设备（UU1），它允许一台主机连接到一个USB端口。主机PC的USB电缆连接到Zing开发板的USB端口上时，也就为CP2103GM提供了5V的供电电压。

CP2013GM TX和RX引脚连接到了XC7Z020的EPP PS IO外设集中的UART_1 IP块上。

XC7Z020 EPP支持USB-UART桥接器使用两个信号引脚：发送（TX）和接收（RX）。

Silicon Labs为主机PC提供了虚拟COM端口（VCP）驱动程序。这些驱动程序允许CP2103GM

USB-UART桥接设备在通信应用软件（例如，TeraTerm或超级终端）显示为一个COM端口。 VCP设备驱动程序必须在PC主机与Zing开发板板建立通信前进行安装。

CP2103GM 的原理图如图5.12所示，

JU1123456USB UART5V_UARTDU-DU+7865349UU1REGINVBUSVDDVIOD+D-RST#TXD_ORXD_ICTSRTSDSRDTRDCDRISUSSUS#2524222326272821USB_UART_TXUSB_UART_RXVCCUVCCMIODU+DU-4.7KRU23VCCU5V_UARTDU+DU-RU21510QU1BAT54SQU2BAT54S5V_UARTDGNDDGND5V_UART22930DGNDNC1NC2NC3NC4GPIO3GPIO2GPIO1GND1GPIO0CNR_GNDNC9CTR_GNDNC10CP2103-GM331DU5LED12122

图5.12 USB_UART接口原理图

USB_UART接口的管脚列表表5.8所示，

表5.8 USB_UART接口管脚列表

XC7Z020 EPP

管脚名称

PS_MIO48

PS_MIO49

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BANK

501

管脚号

D11

C14

UART功能

TX,数据输出

RX,数据输入

信号名称

USB_UART_RX

USB_UART_TX

CP2103GM(UU1)

管脚

UART功能

RXD，数据输入

TXD，数据输出

ZingOEM平台硬件用户手册

5.8 CAN总线接口

TJA1040（U14）是一种先进的高速控制器区域网络（CAN）收发器，用于汽车和一般工业应用。它支持差分总线信号表示的国际标准和车辆高速CAN应用程序（ISO 11898）。在本开发板中其原理图如图5.13所示，

UN1VCCMIO12CAN_TXD_LS3CAN_RXD_LS4CAN_STB_B_LS567DGNDVCCAVCCBA1B1A2B2A3B3A4B4NC1NC2GNDOETXS0104EDJN3IDC10SCANLECN1+47uF85VCAN_TXDCAN_RXDCAN_STB_BCAN_TXDCAN_RXD5VUN2314VCCTXDRXDSTBTJA10405VCANHCANLSPLITGND765CANHCANL60.4RN2RN1CANHCN3SIP218pFDGNDSIP2CANL60.4CN418pFDGNDVCCMIOCN50.1uFDGNDDGNDDGND5VCN60.1uFDGND21JN212JN1VCCMIOCANH0.1uFDGNDCN14700pFCN2CAN_STB_B82

图5.13 CAN总线接口原理图

其管脚列表如表5.9所示，

表5.9 CAN总线接口的管脚列表

TJA1040(UN2)

管脚号

信号名称

CAN_TXD

CAN_RXD

CAN_STB_B

TXS104ED电平转换器（UN1）

信号名称

CAN_TXD_LS

CAN_RXD_LS

CAN_STB_B_LS

XC7Z020 EPP

信号名称

PS_MIO47

PS_MIO46

PS_MIO9

BANK

501

500

管脚号

B10

D12

5.9 I2C总线接口

Zing开饭板中实现了XC7Z020 EPP（IIC_SDA_MAIN，IIC_SDA_SCL）的一个I2C总线接口，该总线接口的运行速度可高达400 kHz。用户可以通过选择相应的跳线来使I2C配置所需的下游设备。其在开发板中的原理图如图5.14所示，

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TP1TPIIC_SDA_HDMIIIC_EEPROM_SDAIIC_RTC_SDA246IIC_SDA_MAINIIC_SDA_MAINIIC_SDA_MAIN1ZingOEM平台硬件用户手册

UM7NC11NC12CLKOEVDDCLKOUTSCLSDA( GND )GND/ INTNC10NC9NC8NC7NC6NC5NC4NC3NC2NC2423222120JM21351BATTIIC_SCL_HDMIIIC_EEPROM_SCLIIC_RTC_SCLHEADER 3X2JM3214365HEADER 3X2IIC_SCL_MAINIIC_SCL_MAINIIC_SCL_MAINIIC_RTC_SCLIIC_RTC_SDAVADJRM3510KIIC_RTC_IRQ_1_B3.3VRM361KRTC8564JEVCCMIORM311KRM341KVCCMIOVADJ1VADJ1PS_SDA_MAIN2QD23IIC_SDA_MAINPS_SCL_MAIN2QD13RM371K3.3VIIC_SCL_MAINNDS331N3.3VNDS331NBATTCM82CM83DM1B0520LWSD0.01uF12340.1uF8765DGNDIIC_EEPROM_SCLIIC_EEPROM_SDA1DM3B0520LWSDDM22.5VLL4148STRM32NCRM330UM8A0A1A2VSSVCCWPSCLSDABAT22V224LC02DGND

图5.14 I2C总线接口原理图

IIC总线可对多个外设进行配置，其配置列表及功能如表5.10所示，

表5.10 IIC总线的配置列表

跳线

JM2

跳线功能

IIC配置设备数据选择

跳线设置

1-2 = IIC配置HDMI数据

3-4 = IIC配置EEPROM数据

5-6 = IIC配置RTC数据

1-2 = IIC配置HDMI时钟

3-4 = IIC配置EEPROM时钟

5-6 = IIC配置RTC时钟

JM3

IIC配置设备时钟选择

5.10 RTC实时时钟

Zing开发板使用了Epson RTC-8564JE型的12C总线接口实时时钟，它内置了一个32.768 KHz的时钟振荡器。主要有以下特点，

•频率输出选项：32.768KHz，1024Hz，32 Hz或1 Hz

•日历输出功能：年，月，日，星期，小时，分钟和秒

•时钟计数器，报警和固定周期的定时中断功能

关于RTC-8564JE的原理图如图5.15所示，

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TP1TPZingOEM平台硬件用户手册

29282726252423222120UM7NC11NC12CLKOEVDDCLKOUTSCLSDA( GND )GND/ INTNC10NC9NC8NC7NC6NC5NC4NC3NC2NC111BATTIIC_RTC_SCLIIC_RTC_SDAVADJRM3510KIIC_RTC_IRQ_1_BRTC8564JE

图5.15 RTC-8564JE的原理图

它在开发板中的管脚列表如表5.11所示，

表5.11 RTC-8564JE管脚列表

RTC-8564JE(UM7)管脚

信号名称

IIC_RTC_SCL

IIC_RTC_SDA

IIC_RTC_IRQ_1_B

连接引脚

JM3.6

JM2.6

U7(XC7Z020 EPP PL BANK 13)

5.11 XADC接口

XC7Z020 EPP提供了模拟前端XADC块。XADC模块块包括了一个双12-bit，1 MSPS的模数转换器（ADC）和片上传感器。更多详细信息用户可参考Xilinx 7系列FPGA有关XADC的用户指南。其原理图如图5.16所示，

VCCAUX5V_XADC1CD10.1uF23UD1VINGNDENADJ42.7KVOUT5RD1ECD1+10uFRD21K5V5V_XADCFBD1BLM21P221SNXADC_VCC123DGND5V_XADCJD3ECD2+10uFSIP3DGNDUD2REF3012AIDBZJD41001001000pF1001001000pFDGNDRD8RD7RD6RD5XADC_VAUX8PXADC_VAUX8NXADC_VAUX0PXADC_VAUX0N1INOUTGND32ECD3+10uFXADC_VREFXADC_VREFP123SIP3TST-110-01-G-DSIP3XADC_VCCXADC_VCC_HEADER123JD1JD2XADC_VNXADC_VAUX0PDGNDXADC_VAUX8NXADC_DXPXADC_VREF5V_XADCVADJXADC_GPIO_1XADC_GPIO_3171924681XADC_VPDGNDXADC_VAUX0NXADC_VAUX8PDGNDXADC_DXNXADC_VCC_HEADERDGNDXADC_GPIO_0XADC_GPIO_2ADP123AUJZDGNDDGNDXADC_VP_RCD2XADC_VN_R1000pFXADC_VAUX8P_RCD3XADC_VAUX8N_RXADC_VAUX0P_RCD4XADC_VAUX0N_R100RD4XADC_VN100RD3XADC_VPDGND

图5.16 XADC原理图

Zing主板上的XADC同时具有内部XC7Z020 EPP传感器测量和外部测量的能力。VCCINT，VCCAUX，VCCBRAM等内部测量都是可实现的。

JD4跳线可以用来选择一个外部的参考电压（VREF）或片上参考电压来作为模数转换器的参考电压。

XADC外部测量插头（JD2）可以用来作为XC7Z020 EPP的专用VP / VN信道的模拟输入，同时也可以作为VAUXP[0] / VAUXN[0]，VAUXP[8] / VAUXN[8]辅助模拟输入通道。支持通道0和通威视锐旗下品牌

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ZingOEM平台硬件用户手册

道8的同时采样。

用户还可以使用一个模拟信号的多路复用器来对外部模拟输入信号进行采样，其中使用了4个GPIO引脚上作为XADC多路复用器的地址线。

XADC插头（JD2)的引脚分配如表5.12所示，

表5.12 XADC插头（JD2)的引脚分配表

信号名称

VN,VP

XADC_VAUX0P,N

XADC_VAUX8N,P

DXP,DXN

XADC_VREF

5V_XADC

XADC_VCC_HEADER

VADJ

DGND

XADC_GPIO3，2，1，0

管脚号

1，2

3，6

7，8

9，12

4,5,10,16

19，20，17，18

描述

XADC专用模拟输入通道。

辅助模拟输入通道0。同时当抗混叠电容时不存在时还可作为IO输入

热敏二极管通道

模拟参考地

来自开发板的5V电源

XADC模拟1.8V供电

DIO引脚所在BANK的VCCO供电

数字参考地

数字IO口。这些引脚应来自同一BANK。这些IO不应该与其他功能共享，因为它们要求支持三态操作。

5.12 FMC连接器

Zing板支持VITA57.1 FPGA FMC（LPC）标准扩展接口JL1和JL2。这两种连接器是10×40形式的，这里使用了其中的160个管脚。

其中FMC1的管脚列表如表5.13所示，FMC2的管脚列表如表5.14所示，

表5.13 FMC1的管脚列表

FMC1管脚

信号名称

XC7Z020管脚

FMC1管脚

信号名称

XC7Z020管脚

C30

C31

G10

FMC1_LPC_CLK0_M2C_N

FMC1_LPC_CLK0_M2C_P

FMC1_LPC_CLK1_M2C_N

FMC1_LPC_CLK1_M2C_P

FMC1_LPC_IIC_SCL

FMC1_LPC_IIC_SDA

FMC1_LPC_LA00_CC_N

FMC1_LPC_LA00_CC_P

FMC1_LPC_LA01_CC_N

FMC1_LPC_LA01_CC_P

FMC1_LPC_LA02_N

FMC1_LPC_LA02_P

FMC1_LPC_LA03_N

L19

L18

M20

M19

P18

P17

K20

K19

N20

N19

L22

L21

K21

G19

G18

D21

D20

C23

C22

H23

H22

G22

G21

H26

H25

G25

FMC1_LPC_LA16_N

FMC1_LPC_LA16_P

FMC1_LPC_LA17_CC_N

FMC1_LPC_LA17_CC_P

FMC1_LPC_LA18_CC_N

FMC1_LPC_LA18_CC_P

FMC1_LPC_LA19_N

FMC1_LPC_LA19_P

FMC1_LPC_LA20_N

FMC1_LPC_LA20_P

FMC1_LPC_LA21_N

FMC1_LPC_LA21_P

FMC1_LPC_LA22_N

P15

N15

B20

B19

C20

D20

E20

E19

G21

G20

F22

F21

F17

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ZingOEM平台硬件用户手册

信号名称

XC7Z020管脚

G17

FMC1管脚

信号名称

H11

H10

D12

D11

C11

C10

H14

H13

G13

G12

D15

D14

C15

C14

H17

H16

G16

G15

D18

D17

C19

C18

H20

H19

FMC1_LPC_LA03_P

FMC1_LPC_LA04_N

FMC1_LPC_LA04_P

FMC1_LPC_LA05_N

FMC1_LPC_LA05_P

FMC1_LPC_LA06_N

FMC1_LPC_LA06_P

FMC1_LPC_LA07_N

FMC1_LPC_LA07_P

FMC1_LPC_LA08_N

FMC1_LPC_LA08_P

FMC1_LPC_LA09_N

FMC1_LPC_LA09_P

FMC1_LPC_LA10_N

FMC1_LPC_LA10_P

FMC1_LPC_LA11_N

FMC1_LPC_LA11_P

FMC1_LPC_LA12_N

FMC1_LPC_LA12_P

FMC1_LPC_LA13_N

FMC1_LPC_LA13_P

FMC1_LPC_LA14_N

FMC1_LPC_LA14_P

FMC1_LPC_LA15_N

FMC1_LPC_LA15_P

XC7Z020管脚

J20

FMC1管脚

G24

M22

M21

N18

N17

K18

J18

K15

J15

J22

J21

M16

M15

M17

L17

R21

R20

P22

N22

R16

P16

J17

J16

P21

P20

D24

D23

H29

H28

G28

G27

D27

D26

C27

C26

H32

H31

G31

G30

H35

H34

G34

G33

H38

H37

G37

G36

FMC1_LPC_LA22_P

FMC1_LPC_LA23_N

FMC1_LPC_LA23_P

FMC1_LPC_LA24_N

FMC1_LPC_LA24_P

FMC1_LPC_LA25_N

FMC1_LPC_LA25_P

FMC1_LPC_LA26_N

FMC1_LPC_LA26_P

FMC1_LPC_LA27_N

FMC1_LPC_LA27_P

FMC1_LPC_LA28_N

FMC1_LPC_LA28_P

FMC1_LPC_LA29_N

FMC1_LPC_LA29_P

FMC1_LPC_LA30_N

FMC1_LPC_LA30_P

FMC1_LPC_LA31_N

FMC1_LPC_LA31_P

FMC1_LPC_LA32_N

FMC1_LPC_LA32_P

FMC1_LPC_LA33_N

FMC1_LPC_LA33_P

FMC1_LPC_PG_C2M

FMC1_LPC_PRSNT_M2C_B

G16

G15

A22

A21

B15

C15

E18

F18

C18

C17

C22

D22

B17

B16

D21

E21

A17

A16

B22

B21

A19

A18

H19

H20

表5.13 FMC2的管脚列表

FMC2管脚

信号名称

XC7Z020管脚

FMC2管脚

信号名称

XC7Z020管脚

C30

C31

FMC2_LPC_CLK0_M2C_N

FMC2_LPC_CLK0_M2C_P

FMC2_LPC_CLK1_M2C_N

FMC2_LPC_CLK1_M2C_P

FMC2_LPC_IIC_SCL

FMC2_LPC_IIC_SDA

FMC2_LPC_LA00_CC_N

FMC2_LPC_LA00_CC_P

FMC2_LPC_LA01_CC_N

AA18

Y18

AA19

Y19

Y16

G19

G18

D21

D20

C23

C22

H23

H22

G22

FMC2_LPC_LA16_N

FMC2_LPC_LA16_P

FMC2_LPC_LA17_CC_N

FMC2_LPC_LA17_CC_P

FMC2_LPC_LA18_CC_N

FMC2_LPC_LA18_CC_P

FMC2_LPC_LA19_N

FMC2_LPC_LA19_P

FMC2_LPC_LA20_N

AB15

AB14

AA6

AA7

AA8

AA9

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ZingOEM平台硬件用户手册

信号名称

XC7Z020管脚

FMC2管脚

信号名称

G10

H11

H10

D12

D11

C11

C10

H14

H13

G13

G12

D15

D14

C15

C14

H17

H16

G16

G15

D18

D17

C19

C18

H20

H19

FMC2_LPC_LA01_CC_P

FMC2_LPC_LA02_N

FMC2_LPC_LA02_P

FMC2_LPC_LA03_N

FMC2_LPC_LA03_P

FMC2_LPC_LA04_N

FMC2_LPC_LA04_P

FMC2_LPC_LA05_N

FMC2_LPC_LA05_P

FMC2_LPC_LA06_N

FMC2_LPC_LA06_P

FMC2_LPC_LA07_N

FMC2_LPC_LA07_P

FMC2_LPC_LA08_N

FMC2_LPC_LA08_P

FMC2_LPC_LA09_N

FMC2_LPC_LA09_P

FMC2_LPC_LA10_N

FMC2_LPC_LA10_P

FMC2_LPC_LA11_N

FMC2_LPC_LA11_P

FMC2_LPC_LA12_N

FMC2_LPC_LA12_P

FMC2_LPC_LA13_N

FMC2_LPC_LA13_P

FMC2_LPC_LA14_N

FMC2_LPC_LA14_P

FMC2_LPC_LA15_N

FMC2_LPC_LA15_P

XC7Z020管脚

W16

FMC2管脚

G21

V15

V14

AB16

AA16

W13

V13

AB20

AB19

V17

U17

U21

T21

AB17

AA17

U16

U15

Y21

Y20

AA14

Y14

Y15

W15

W22

V22

U22

T22

AA13

Y13

H26

H25

G25

G24

D24

D23

H29

H28

G28

G27

D27

D26

C27

C26

H32

H31

G31

G30

H35

H34

G34

G33

H38

H37

G37

G36

FMC2_LPC_LA20_P

FMC2_LPC_LA21_N

FMC2_LPC_LA21_P

FMC2_LPC_LA22_N

FMC2_LPC_LA22_P

FMC2_LPC_LA23_N

FMC2_LPC_LA23_P

FMC2_LPC_LA24_N

FMC2_LPC_LA24_P

FMC2_LPC_LA25_N

FMC2_LPC_LA25_P

FMC2_LPC_LA26_N

FMC2_LPC_LA26_P

FMC2_LPC_LA27_N

FMC2_LPC_LA27_P

FMC2_LPC_LA28_N

FMC2_LPC_LA28_P

FMC2_LPC_LA29_N

FMC2_LPC_LA29_P

FMC2_LPC_LA30_N

FMC2_LPC_LA30_P

FMC2_LPC_LA31_N

FMC2_LPC_LA31_P

FMC2_LPC_LA32_N

FMC2_LPC_LA32_P

FMC2_LPC_LA33_N

FMC2_LPC_LA33_P

FMC2_LPC_PG_C2M

FMC2_LPC_PRSNT_M2C_B

U10

W12

V12

AB12

AA12

U11

U12

AB1

AB2

AB4

AB5

AB11

AA11

AB6

AB7

AB9

AB10

AA4

Y10

Y11

W10

5.13 HDMI接口

Zing开发板板提供了一个高清晰度多媒体视频输出接口（HDMI），这里使用了Sil9134CTU型的HDMI发送器芯片。

Sil9134发送器提供了完整的HDMI数字视频/音频传输解决方案。发射器内的专业音频/视频处理功能使它在消费电子设备中变得容易，并且提高了成本效益。

其原理图如图5.16所示，

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UH939296059585756D0D1D2D3D4_B0D5_B1D6_B2D7_B3D8_B4D9_B5D10_B6D11_B7D12D13D14D15D16_G0_Y0D17_G1_Y1D18_G2_Y2D19_G3_Y3D20_G4_Y4D21_G5_Y5D22_G6_Y6D23_G7_Y7D24D25D26D27D28_R0_C0D29_R1_C1D30_R2_C2D31_R3_C3D32_R4_C4D33_R5_C5D34_R6_C6D35_R7_C7DEHSYNCIDCKVSYNCDL0DL1DL2DL3DR0DR1DR2DR3SD0SD1SD2SD3SCKDCLKMCLKWSSPDIFSiI9134CTUZingOEM平台硬件用户手册

3946254948523884245135465871HDMI_OUT_TXC-HDMI_OUT_TXC+HDMI_OUT_TX0-HDMI_OUT_TX0+HDMI_OUT_TX1-HDMI_OUT_TX1+HDMI_OUT_TX2-HDMI_OUT_TX2+RH6698 1%1.8VTXC-TXC+TX0-TX0+TX1-TX1+TX2-TX2+EXT_SWGHPDRSVDLINTDSDADSCLnRESETCSDACSCLCI2CAIOVCC33_1IOVCC33_2IOVCC33_3IOVCC33_4AVCC33AVCC18_1AVCC18_2CVCC18_1CVCC18_2CVCC18_3CVCC18_4CVCC18_5PVCC1PVCC2DDCPWR5VGND1GND2GND3GND4GND5AGND1AGND2AGND3AGND4AGND5HDMI_OUT_HPDHDMI_INTHDMI_OUT_DDCSCLHDMI_OUT_DDCSDAHDMI_OUT_RST#IIC_SDA_HDMIIIC_SCL_HDMIHDMI_OUT_CA3.3VHDMI_R_D8HDMI_R_D9HDMI_R_D10HDMI_R_D11HDMI_R_D12HDMI_R_D13HDMI_R_D14HDMI_R_D15RH10RH11RH12RH13RH14RH15RH16RH173030HDMI_D8HDMI_D9HDMI_D10HDMI_D11HDMI_D12HDMI_D13HDMI_D14HDMI_D15HDMI_R_D0HDMI_R_D1HDMI_R_D2HDMI_R_D3HDMI_R_D4HDMI_R_D5HDMI_R_D6HDMI_R_D7HDMI_R_DEHDMI_R_HSYNCHDMI_R_CLKHDMI_R_VSYNCRH18RH19RH20RH21RH22RH23RH24RH25RH26RH27RH28RH293HDMI_D0HDMI_D1HDMI_D2HDMI_D3HDMI_D4HDMI_D5HDMI_D6HDMI_D73.3VA1.8V1HDMI_DEHDMI_HSYNC288HDMI_CLKHDMI_VSYNC3821045VHDMI_R_MCLKHDMI_R_SPDIFRH3330HDMI_MCLKRH3230HDMI_SPDIF

图5.16 HDMI接口原理图

HDMI接口芯片9134的管脚列表如表5.14所示，

表5.14 HDMI芯片的管脚列表

XC7Z020管脚

AB21

AA21

AB22

AA22

V19

V18

V20

U20

W21

W20

信号名称

HDMI_R_D0

HDMI_R_D1

HDMI_R_D2

HDMI_R_D3

HDMI_R_D4

HDMI_R_D5

HDMI_R_D6

HDMI_R_D7

HDMI_R_D8

HDMI_R_D9

SiI9134CTU(UH1)

管脚

管脚名称

D28_R0_C0

D29_R1_C1

D30_R2_C2

D31_R3_C3

D32_R4_C4

D33_R5_C5

D34_R6_C6

D35_R7_C7

D16_G0_Y0

D17_G1_Y1

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ZingOEM平台硬件用户手册

SiI9134CTU(UH1)

管脚名称

D18_G2_Y2

D19_G3_Y3

D20_G4_Y4

D21_G5_Y5

D22_G6_Y6

D23_G7_Y7

SPDIF

VSYNC

HSYNC

INT

MCLK

XC7Z020管脚

W18

T19

U19

R19

T17

T16

T18

R15

H15

R18

U14

W11

信号名称

HDMI_R_D10

HDMI_R_D11

HDMI_R_D12

HDMI_R_D13

HDMI_R_D14

HDMI_R_D15

HDMI_R_DE

HDMI_R_SPDIF

HDMI_R_VSYNC

HDMI_R_HSYNC

HDMI_INT

HDMI_R_MCLK

管脚

Sil9134型HDMI芯片与HDMI连接器间的管脚分配如表5.15所示，

表5.15 HDMI芯片与连接器的管脚分配表

SiI9134CTU（UH1）管脚

信号名称

HDMI_OUT_TX0+

HDMI_OUT_TX0-

HDMI_OUT_TX1+

HDMI_OUT_TX1-

HDMI_OUT_TX2+

HDMI_OUT_TX2-

HDMI_OUT_TXC+

HDMI_OUT_TXC-

HDMI_OUT_DDCSCL（经IP4776CZ38）

HDMI_OUT_DDCSDA（经IP4776CZ38）

HDMI_OUT_HPD（经IP4776CZ38）

HDMI连接器(JH1)管脚

5.14 用户I/O

Zing开发板为用户提供了4个用户LED灯（属于PL部分），分别为DU1、DU2、DU3、DU4；4个按键，分别为PU1、PU2、PD1、PD2（其中PU1和PU2属于PL部分，PD1和PD2属于PS部分）；两个拨码开关（属于PS部分），分别为PD3、PD4。

其中，用户LED灯的原理图如图5.17所示，而用户按键和拨码开关的原理图如图5.18所示。

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DU4PMOD1_0_LSQU69014LEDRed3.3VRU111KPMOD1_2_LSZingOEM平台硬件用户手册

LEDRedRU93.3V1KDU2QU49014DGNDDU3PMOD1_1_LSQU59014LEDRed3.3VRU101KPMOD1_3_LSDGNDDU1QU39014LEDRedRU83.3V1KDGNDDGND

图5.17 用户LED灯原理图

PS_DIP_SW0VCCMIO_PSPD1RF64.7KDGNDPS_DIP_SW1VCCMIO_PSPD2RF74.7KDGNDPS_DIP_SW0PD3PS_DIP_SW1PD4VCCMIO_PSGPIO_SW_SGPIO_SW_NVADJPU1RU134.7KDGNDVADJPU2RU124.7KDGND

图5.18用户按键和拨码开关原理图

用户I/O的管脚列表如表5.16所示，

表5.16 用户I/O管脚列表

设备名称

QU3

QU4

QU5

QU6

PU1

PU2

PD1

PD2

PD3

PD4

信号名称

PMOD1_3 LS

PMOD1_2 LS

PMOD1_1 LS

PMOD1_0 LS

GPIO_SW_N

GPIO_SW_S

PS_DIP_SW0

PS_DIP_SW1

PS_DIP_SW0

PS_DIP_SW1

XC7Z020管脚

W17

D15

E15

G19

F19

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ZingOEM平台硬件用户手册

6 Zing开发板UCF列表

#NET FPGA_DONE LOC = T12 ; # Bank 0 - DONE_0

#NET XADC_DXP LOC = N11 ; # Bank 0 - DXP_0

#NET DGND LOC = K12 ; # Bank 0 - GNDADC_0

#NET XADC_VCC LOC = K11 ; # Bank 0 - VCCADC_0

#NET XADC_VREFP LOC = M11 ; # Bank 0 - VREFP_0

#NET XADC_VN_R LOC = M12 ; # Bank 0 - VN_0

#NET FPGA_VBATT LOC = G9 ; # Bank 0 - VCCBATT_0

#NET FPGA_TCK_BUF LOC = G11 ; # Bank 0 - TCK_0

#NET XADC_DXN LOC = N12 ; # Bank 0 - DXN_0

#NET DGND LOC = L12 ; # Bank 0 - VREFN_0

#NET XADC_VP_R LOC = L11 ; # Bank 0 - VP_0

#NET DGND LOC = G10 ; # Bank 0 - RSVDGND

#NET VCC2V5 LOC = T10 ; # Bank 0 - RSVDVCC

#NET VCC2V5 LOC = T8 ; # Bank 0 - RSVDVCC

#NET FPGA_INIT_B LOC = T14 ; # Bank 0 - INIT_B_0

#NET FPGA_TDI_BUF LOC = H13 ; # Bank 0 - TDI_0

#NET JTAG_TDO_BUF LOC = G14 ; # Bank 0 - TDO_0

#NET VCC2V5 LOC = T7 ; # Bank 0 - RSVDVCC

#NET FPGA_CFGBVS LOC = T13 ; # Bank 0 - CFGBVS_0

#NET FPGA_PROG_B LOC = T11 ; # Bank 0 - PROGRAM_B_0

#NET FPGA_TMS_BUF LOC = G12 ; # Bank 0 - TMS_0

NET PL_PJTAG_TDO_R LOC = R7 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_0_13

NET PL_PJTAG_TCK LOC = V10 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L1P_T0_13

NET PL_PJTAG_TMS LOC = V9 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L1N_T0_13

NET PL_PJTAG_TDI LOC = V8 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L2P_T0_13

NET HDMI_R_CLK LOC = W11 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L3P_T0_DQS_13

NET FMC2_LPC_PRSNT_M2C_B LOC = W10 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L3N_T0_DQS_13

NET FMC2_LPC_LA23_P LOC = V12 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L4P_T0_13

NET FMC2_LPC_LA23_N LOC = W12 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L4N_T0_13

NET FMC2_LPC_LA26_P LOC = U12 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L5P_T0_13

NET FMC2_LPC_LA26_N LOC = U11 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L5N_T0_13

NET FMC2_LPC_LA22_P LOC = U10 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L6P_T0_13

NET FMC2_LPC_LA22_N LOC = U9 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L6N_T0_VREF_13

NET FMC2_LPC_LA25_P LOC = AA12 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L7P_T1_13

NET FMC2_LPC_LA25_N LOC = AB12 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L7N_T1_13

NET FMC2_LPC_LA29_P LOC = AA11 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L8P_T1_13

NET FMC2_LPC_LA29_N LOC = AB11 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L8N_T1_13

NET FMC2_LPC_LA31_P LOC = AB10 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L9P_T1_DQS_13

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ZingOEM平台硬件用户手册

NET FMC2_LPC_LA31_N LOC = AB9 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L9N_T1_DQS_13

NET FMC2_LPC_LA33_P LOC = Y11 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L10P_T1_13

NET FMC2_LPC_LA33_N LOC = Y10 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L10N_T1_13

NET FMC2_LPC_LA18_CC_P LOC = AA9 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L11P_T1_SRCC_13

NET FMC2_LPC_LA18_CC_N LOC = AA8 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L11N_T1_SRCC_13

NET USRCLK_P LOC = Y9 | IOSTANDARD=LVDS; # Bank 13 VCCO - VADJ - IO_L12P_T1_MRCC_13

NET USRCLK_N LOC = Y8 | IOSTANDARD=LVDS; # Bank 13 VCCO - VADJ - IO_L12N_T1_MRCC_13

NET FMC2_LPC_CLK1_M2C_P LOC = Y6 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L13P_T2_MRCC_13

NET FMC2_LPC_CLK1_M2C_N LOC = Y5 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L13N_T2_MRCC_13

NET FMC2_LPC_LA17_CC_P LOC = AA7 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L14P_T2_SRCC_13

NET FMC2_LPC_LA17_CC_N LOC = AA6 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L14N_T2_SRCC_13

NET FMC2_LPC_LA27_P LOC = AB2 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L15P_T2_DQS_13

NET FMC2_LPC_LA27_N LOC = AB1 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L15N_T2_DQS_13

NET FMC2_LPC_LA28_P LOC = AB5 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L16P_T2_13

NET FMC2_LPC_LA28_N LOC = AB4 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L16N_T2_13

NET FMC2_LPC_LA30_P LOC = AB7 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L17P_T2_13

NET FMC2_LPC_LA30_N LOC = AB6 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L17N_T2_13

NET FMC2_LPC_LA32_P LOC = Y4 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L18P_T2_13

NET FMC2_LPC_LA32_N LOC = AA4 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L18N_T2_13

NET FMC2_LPC_LA19_P LOC = R6 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L19P_T3_13

NET FMC2_LPC_LA19_N LOC = T6 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L19N_T3_VREF_13

NET FMC2_LPC_LA20_P LOC = T4 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L20P_T3_13

NET FMC2_LPC_LA20_N LOC = U4 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L20N_T3_13

NET FMC2_LPC_LA21_P LOC = V5 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L21P_T3_DQS_13

NET FMC2_LPC_LA21_N LOC = V4 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L21N_T3_DQS_13

NET FMC2_LPC_LA24_P LOC = U6 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L22P_T3_13

NET FMC2_LPC_LA24_N LOC = U5 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L22N_T3_13

NET FMC2_LPC_PG_C2M LOC = V7 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L23P_T3_13

NET FMC2_LPC_IIC_SDA LOC = W7 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L23N_T3_13

NET FMC2_LPC_IIC_SCL LOC = W6 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L24P_T3_13

NET PMOD1_3_LS LOC = W5 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_L24N_T3_13

NET IIC_RTC_IRQ_1_B LOC = U7 | IOSTANDARD=LVCMOS25; # Bank 13 VCCO - VADJ - IO_25_13

NET HDMI_R_D12 LOC = U19 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_0_33

NET FMC2_LPC_LA07_P LOC = T21 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L1P_T0_33

NET FMC2_LPC_LA07_N LOC = U21 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L1N_T0_33

NET FMC2_LPC_LA14_P LOC = T22 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L2P_T0_33

NET FMC2_LPC_LA14_N LOC = U22 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L2N_T0_33

NET FMC2_LPC_LA13_P LOC = V22 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L3P_T0_DQS_33

NET FMC2_LPC_LA13_N LOC = W22 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L3N_T0_DQS_33

NET HDMI_R_D9 LOC = W20 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L4P_T0_33

NET HDMI_R_D8 LOC = W21 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L4N_T0_33

NET HDMI_R_D7 LOC = U20 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L5P_T0_33

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ZingOEM平台硬件用户手册

NET HDMI_R_D6 LOC = V20 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L5N_T0_33

NET HDMI_R_D5 LOC = V18 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L6P_T0_33

NET HDMI_R_D4 LOC = V19 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L6N_T0_VREF_33

NET HDMI_R_D3 LOC = AA22 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L7P_T1_33

NET HDMI_R_D2 LOC = AB22 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L7N_T1_33

NET HDMI_R_D1 LOC = AA21 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L8P_T1_33

NET HDMI_R_D0 LOC = AB21 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L8N_T1_33

NET FMC2_LPC_LA10_P LOC = Y20 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L9P_T1_DQS_33

NET FMC2_LPC_LA10_N LOC = Y21 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L9N_T1_DQS_33

NET FMC2_LPC_LA05_P LOC = AB19 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L10P_T1_33

NET FMC2_LPC_LA05_N LOC = AB20 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L10N_T1_33

NET FMC2_LPC_LA00_CC_P LOC = Y19 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L11P_T1_SRCC_33

NET FMC2_LPC_LA00_CC_N LOC = AA19 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L11N_T1_SRCC_33

NET FMC2_LPC_CLK0_M2C_P LOC = Y18 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L12P_T1_MRCC_33

NET FMC2_LPC_CLK0_M2C_N LOC = AA18 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L12N_T1_MRCC_33

NET PMOD1_2_LS LOC = W17 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L13P_T2_MRCC_33

NET HDMI_R_D10 LOC = W18 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L13N_T2_MRCC_33

NET FMC2_LPC_LA01_CC_P LOC = W16 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L14P_T2_SRCC_33

NET FMC2_LPC_LA01_CC_N LOC = Y16 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L14N_T2_SRCC_33

NET FMC2_LPC_LA09_P LOC = U15 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L15P_T2_DQS_33

NET FMC2_LPC_LA09_N LOC = U16 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L15N_T2_DQS_33

NET FMC2_LPC_LA06_P LOC = U17 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L16P_T2_33

NET FMC2_LPC_LA06_N LOC = V17 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L16N_T2_33

NET FMC2_LPC_LA08_P LOC = AA17 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L17P_T2_33

NET FMC2_LPC_LA08_N LOC = AB17 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L17N_T2_33

NET FMC2_LPC_LA03_P LOC = AA16 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L18P_T2_33

NET FMC2_LPC_LA03_N LOC = AB16 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L18N_T2_33

NET FMC2_LPC_LA02_P LOC = V14 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L19P_T3_33

NET FMC2_LPC_LA02_N LOC = V15 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L19N_T3_VREF_33

NET FMC2_LPC_LA04_P LOC = V13 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L20P_T3_33

NET FMC2_LPC_LA04_N LOC = W13 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L20N_T3_33

NET FMC2_LPC_LA12_P LOC = W15 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L21P_T3_DQS_33

NET FMC2_LPC_LA12_N LOC = Y15 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L21N_T3_DQS_33

NET FMC2_LPC_LA11_P LOC = Y14 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L22P_T3_33

NET FMC2_LPC_LA11_N LOC = AA14 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L22N_T3_33

NET FMC2_LPC_LA15_P LOC = Y13 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L23P_T3_33

NET FMC2_LPC_LA15_N LOC = AA13 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L23N_T3_33

NET FMC2_LPC_LA16_P LOC = AB14 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L24P_T3_33

NET FMC2_LPC_LA16_N LOC = AB15 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_L24N_T3_33

NET HDMI_INT LOC = U14 | IOSTANDARD=LVCMOS25; # Bank 33 VCCO - VADJ - IO_25_33

NET HDMI_R_VSYNC LOC = H15 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_0_34

NET FMC1_LPC_LA07_P LOC = J15 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L1P_T0_34

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NET FMC1_LPC_LA07_N LOC = K15 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L1N_T0_34

NET FMC1_LPC_LA14_P LOC = J16 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L2P_T0_34

NET FMC1_LPC_LA14_N LOC = J17 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L2N_T0_34

NET HDMI_R_CLK LOC = L16 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L3N_T0_DQS_34

NET FMC1_LPC_LA10_P LOC = L17 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L4P_T0_34

NET FMC1_LPC_LA10_N LOC = M17 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L4N_T0_34

NET FMC1_LPC_LA05_P LOC = N17 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L5P_T0_34

NET FMC1_LPC_LA05_N LOC = N18 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L5N_T0_34

NET FMC1_LPC_LA09_P LOC = M15 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L6P_T0_34

NET FMC1_LPC_LA09_N LOC = M16 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L6N_T0_VREF_34

NET FMC1_LPC_LA06_P LOC = J18 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L7P_T1_34

NET FMC1_LPC_LA06_N LOC = K18 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L7N_T1_34

NET FMC1_LPC_LA08_P LOC = J21 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L8P_T1_34

NET FMC1_LPC_LA08_N LOC = J22 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L8N_T1_34

NET FMC1_LPC_LA03_P LOC = J20 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L9P_T1_DQS_34

NET FMC1_LPC_LA03_N LOC = K21 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L9N_T1_DQS_34

NET FMC1_LPC_LA02_P LOC = L21 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L10P_T1_34

NET FMC1_LPC_LA02_N LOC = L22 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L10N_T1_34

NET FMC1_LPC_LA00_CC_P LOC = K19 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L11P_T1_SRCC_34

NET FMC1_LPC_LA00_CC_N LOC = K20 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L11N_T1_SRCC_34

NET FMC1_LPC_CLK0_M2C_P LOC = L18 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L12P_T1_MRCC_34

NET FMC1_LPC_CLK0_M2C_N LOC = L19 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L12N_T1_MRCC_34

NET FMC1_LPC_CLK1_M2C_P LOC = M19 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L13P_T2_MRCC_34

NET FMC1_LPC_CLK1_M2C_N LOC = M20 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L13N_T2_MRCC_34

NET FMC1_LPC_LA01_CC_P LOC = N19 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L14P_T2_SRCC_34

NET FMC1_LPC_LA01_CC_N LOC = N20 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L14N_T2_SRCC_34

NET FMC1_LPC_LA04_P LOC = M21 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L15P_T2_DQS_34

NET FMC1_LPC_LA04_N LOC = M22 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L15N_T2_DQS_34

NET FMC1_LPC_LA12_P LOC = N22 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L16P_T2_34

NET FMC1_LPC_LA12_N LOC = P22 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L16N_T2_34

NET FMC1_LPC_LA11_P LOC = R20 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L17P_T2_34

NET FMC1_LPC_LA11_N LOC = R21 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L17N_T2_34

NET FMC1_LPC_LA15_P LOC = P20 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L18P_T2_34

NET FMC1_LPC_LA15_N LOC = P21 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L18N_T2_34

NET FMC1_LPC_LA16_P LOC = N15 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L19P_T3_34

NET FMC1_LPC_LA16_N LOC = P15 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L19N_T3_VREF_34

NET FMC1_LPC_IIC_SDA LOC = P17 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L20P_T3_34

NET FMC1_LPC_IIC_SCL LOC = P18 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L20N_T3_34

NET HDMI_R_D15 LOC = T16 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L21P_T3_DQS_34

NET HDMI_R_D14 LOC = T17 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L21N_T3_DQS_34

NET HDMI_R_D13 LOC = R19 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L22P_T3_34

NET HDMI_R_D11 LOC = T19 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L22N_T3_34

NET HDMI_R_HSYNC LOC = R18 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L23P_T3_34

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NET HDMI_R_DE LOC = T18 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L23N_T3_34

NET FMC1_LPC_LA13_P LOC = P16 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L24P_T3_34

NET FMC1_LPC_LA13_N LOC = R16 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_L24N_T3_34

NET HDMI_R_SPDIF LOC = R15 | IOSTANDARD=LVCMOS25; # Bank 34 VCCO - VADJ - IO_25_34

NET XADC_GPIO_0 LOC = H17 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_0_35

NET XADC_VAUX0P_R LOC = F16 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L1P_T0_AD0P_35

NET XADC_VAUX0N_R LOC = E16 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L1N_T0_AD0N_35

NET XADC_VAUX8P_R LOC = D16 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L2P_T0_AD8P_35

NET XADC_VAUX8N_R LOC = D17 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L2N_T0_AD8N_35

NET PMOD1_0_LS LOC = E15 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L3P_T0_DQS_AD1P_35

NET PMOD1_1_LS LOC = D15 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L3N_T0_DQS_AD1N_35

NET FMC1_LPC_LA23_P LOC = G15 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L4P_T0_35

NET FMC1_LPC_LA23_N LOC = G16 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L4N_T0_35

NET FMC1_LPC_LA26_P LOC = F18 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ- IO_L5P_T0_AD9P_35

NET FMC1_LPC_LA26_N LOC = E18 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L5N_T0_AD9N_35

NET FMC1_LPC_LA22_P LOC = G17 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L6P_T0_35

NET FMC1_LPC_LA22_N LOC = F17 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L6N_T0_VREF_35

NET FMC1_LPC_LA25_P LOC = C15 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L7P_T1_AD2P_35

NET FMC1_LPC_LA25_N LOC = B15 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L7N_T1_AD2N_35

NET FMC1_LPC_LA29_P LOC = B16 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L8P_T1_AD10P_35

NET FMC1_LPC_LA29_N LOC = B17 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L8N_T1_AD10N_35

NET FMC1_LPC_LA31_P LOC = A16 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L9P_T1_DQS_AD3P_35

NET FMC1_LPC_LA31_N LOC = A17 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L9N_T1_DQS_AD3N_35

NET FMC1_LPC_LA33_P LOC = A18 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L10P_T1_AD11P_35

NET FMC1_LPC_LA33_N LOC = A19 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L10N_T1_AD11N_35

NET FMC1_LPC_LA27_P LOC = C17 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L11P_T1_SRCC_35

NET FMC1_LPC_LA27_N LOC = C18 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L11N_T1_SRCC_35

NET SYSCLK_P LOC = D18 | IOSTANDARD=LVDS; # Bank 35 VCCO - VADJ - IO_L12P_T1_MRCC_35

NET SYSCLK_N LOC = C19 | IOSTANDARD=LVDS; # Bank 35 VCCO - VADJ - IO_L12N_T1_MRCC_35

NET FMC1_LPC_LA17_CC_P LOC = B19 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L13P_T2_MRCC_35

NET FMC1_LPC_LA17_CC_N LOC = B20 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L13N_T2_MRCC_35

NET FMC1_LPC_LA18_CC_P LOC = D20 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L14P_T2_AD4P_SRCC_35

NET FMC1_LPC_LA18_CC_N LOC = C20 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L14N_T2_AD4N_SRCC_35

NET FMC1_LPC_LA24_P LOC = A21 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L15P_T2_DQS_AD12P_35

NET FMC1_LPC_LA24_N LOC = A22 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L15N_T2_DQS_AD12N_35

NET FMC1_LPC_LA28_P LOC = D22 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L16P_T2_35

NET FMC1_LPC_LA28_N LOC = C22 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L16N_T2_35

NET FMC1_LPC_LA30_P LOC = E21 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L17P_T2_AD5P_35

NET FMC1_LPC_LA30_N LOC = D21 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L17N_T2_AD5N_35

NET FMC1_LPC_LA32_P LOC = B21 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L18P_T2_AD13P_35

NET FMC1_LPC_LA32_N LOC = B22 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L18N_T2_AD13N_35

NET FMC1_LPC_PG_C2M LOC = H19 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L19P_T3_35

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NET FMC1_LPC_PRSNT_M2C_B LOC = H20 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L19N_T3_VREF_35

NET GPIO_SW_N LOC = G19 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L20P_T3_AD6P_35

NET GPIO_SW_S LOC = F19 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L20N_T3_AD6N_35

NET FMC1_LPC_LA19_P LOC = E19 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L21P_T3_DQS_AD14P_35

NET FMC1_LPC_LA19_N LOC = E20 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L21N_T3_DQS_AD14N_35

NET FMC1_LPC_LA20_P LOC = G20 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L22P_T3_AD7P_35

NET FMC1_LPC_LA20_N LOC = G21 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L22N_T3_AD7N_35

NET FMC1_LPC_LA21_P LOC = F21 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L23P_T3_35

NET FMC1_LPC_LA21_N LOC = F22 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L23N_T3_35

NET XADC_GPIO_1 LOC = H22 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L24P_T3_AD15P_35

NET XADC_GPIO_2 LOC = G22 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_L24N_T3_AD15N_35

NET XADC_GPIO_3 LOC = H18 | IOSTANDARD=LVCMOS25; # Bank 35 VCCO - VADJ - IO_25_35

#NET PS_CLK LOC = F7 ; # Bank 500 - PS_CLK_500

#NET PS_POR_B LOC = B5 ; # Bank 500 - PS_POR_B_500

#NET PS_DIP_SW0 LOC = B6 ; # Bank 500 - PS_MIO14_500

#NET PS_DIP_SW1 LOC = C5 ; # Bank 500 - PS_MIO12_500

#NET PHY_RESET_B_AND LOC = B4 ; # Bank 500 - PS_MIO11_500

#NET PS_LED1 LOC = G7 ; # Bank 500 - PS_MIO10_500

#NET CAN_STB_B_LS LOC = C4 ; # Bank 500 - PS_MIO9_500

#NET PS_MIO8_LED0 LOC = E5 ; # Bank 500 - PS_MIO8_500

#NET USB_RESET_B_AND LOC = D5 ; # Bank 500 - PS_MIO7_500

#NET QSPI_CLK LOC = A4 ; # Bank 500 - PS_MIO6_500

#NET QSPI_IO3 LOC = A3 ; # Bank 500 - PS_MIO5_500

#NET QSPI_IO2 LOC = E4 ; # Bank 500 - PS_MIO4_500

#NET QSPI_IO1 LOC = F6 ; # Bank 500 - PS_MIO3_500

#NET QSPI_IO0 LOC = A2 ; # Bank 500 - PS_MIO2_500

#NET QSPI_CS_B LOC = A1 ; # Bank 500 - PS_MIO1_500

#NET SDIO_SDDET LOC = G6 ; # Bank 500 - PS_MIO0_500

#NET PHY_TXD0 LOC = E9 ; # Bank 501 - PS_MIO17_501

#NET PHY_TXD2 LOC = E10 ; # Bank 501 - PS_MIO19_501

#NET PHY_TX_CTRL LOC = F11 ; # Bank 501 - PS_MIO21_501

#NET PHY_RXD0 LOC = E11 ; # Bank 501 - PS_MIO23_501

#NET PHY_RXD2 LOC = F12 ; # Bank 501 - PS_MIO25_501

#NET PHY_RX_CTRL LOC = D7 ; # Bank 501 - PS_MIO27_501

#NET USB_DIR LOC = E8 ; # Bank 501 - PS_MIO29_501

#NET USB_NXT LOC = F9 ; # Bank 501 - PS_MIO31_501

#NET USB_DATA1 LOC = G13 ; # Bank 501 - PS_MIO33_501

#NET USB_DATA3 LOC = F14 ; # Bank 501 - PS_MIO35_501

#NET USB_DATA6 LOC = F13 ; # Bank 501 - PS_MIO38_501

#NET SDIO_CLK_LS LOC = E14 ; # Bank 501 - PS_MIO40_501

#NET SDIO_DAT0_LS LOC = D8 ; # Bank 501 - PS_MIO42_501

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#NET SDIO_DAT2_LS LOC = E13 ; # Bank 501 - PS_MIO44_501

#NET CAN_RXD_LS LOC = D12 ; # Bank 501 - PS_MIO46_501

#NET USB_UART_RX LOC = D11 ; # Bank 501 - PS_MIO48_501

#NET PS_SCL_MAIN LOC = D13 ; # Bank 501 - PS_MIO50_501

#NET PHY_MDC LOC = D10 ; # Bank 501 - PS_MIO52_501

#NET PS_SRST_B LOC = C9 ; # Bank 501 - PS_SRST_B_501

#NET PHY_TX_CLK LOC = D6 ; # Bank 501 - PS_MIO16_501

#NET PHY_TXD1 LOC = A7 ; # Bank 501 - PS_MIO18_501

#NET PHY_TXD3 LOC = A8 ; # Bank 501 - PS_MIO20_501

#NET PHY_RX_CLK LOC = A14 ; # Bank 501 - PS_MIO22_501

#NET PHY_RXD1 LOC = B7 ; # Bank 501 - PS_MIO24_501

#NET PHY_RXD3 LOC = A13 ; # Bank 501 - PS_MIO26_501

#NET USB_DATA4 LOC = A12 ; # Bank 501 - PS_MIO28_501

#NET USB_STP LOC = A11 ; # Bank 501 - PS_MIO30_501

#NET USB_DATA0 LOC = C7 ; # Bank 501 - PS_MIO32_501

#NET USB_DATA2 LOC = B12 ; # Bank 501 - PS_MIO34_501

#NET USB_CLKOUT LOC = A9 ; # Bank 501 - PS_MIO36_501

#NET USB_DATA5 LOC = B14 ; # Bank 501 - PS_MIO37_501

#NET USB_DATA7 LOC = C13 ; # Bank 501 - PS_MIO39_501

#NET SDIO_CMD_LS LOC = C8 ; # Bank 501 - PS_MIO41_501

#NET SDIO_DAT1_LS LOC = B11 ; # Bank 501 - PS_MIO43_501

#NET SDIO_CD_DAT3_LS LOC = B9 ; # Bank 501 - PS_MIO45_501

#NET CAN_TXD_LS LOC = B10 ; # Bank 501 - PS_MIO47_501

#NET USB_UART_TX LOC = C14 ; # Bank 501 - PS_MIO49_501

#NET PS_SDA_MAIN LOC = C10 ; # Bank 501 - PS_MIO51_501

#NET PHY_MDIO LOC = C12 ; # Bank 501 - PS_MIO53_501

#NET PS_DDR3_RESET_B LOC = F3 ; # Bank 502 - PS_DDR_DRST_B_502

#NET PS_DDR3_DQ3 LOC = D1 ; # Bank 502 - PS_DDR_DQ0_502

#NET PS_DDR3_DQ1 LOC = C3 ; # Bank 502 - PS_DDR_DQ1_502

#NET PS_DDR3_DQ6 LOC = B2 ; # Bank 502 - PS_DDR_DQ2_502

#NET PS_DDR3_DQ7 LOC = D3 ; # Bank 502 - PS_DDR_DQ3_502

#NET PS_DDR3_DM0 LOC = B1 ; # Bank 502 - PS_DDR_DM0_502

#NET PS_DDR3_DQS0_P LOC = C2 ; # Bank 502 - PS_DDR_DQS_P0_502

#NET PS_DDR3_DQS0_N LOC = D2 ; # Bank 502 - PS_DDR_DQS_N0_502

#NET PS_DDR3_DQ0 LOC = E3 ; # Bank 502 - PS_DDR_DQ4_502

#NET PS_DDR3_DQ5 LOC = E1 ; # Bank 502 - PS_DDR_DQ5_502

#NET PS_DDR3_DQ2 LOC = F2 ; # Bank 502 - PS_DDR_DQ6_502

#NET PS_DDR3_DQ4 LOC = F1 ; # Bank 502 - PS_DDR_DQ7_502

#NET PS_DDR3_DQ8 LOC = G2 ; # Bank 502 - PS_DDR_DQ8_502

#NET PS_DDR3_DQ10 LOC = G1 ; # Bank 502 - PS_DDR_DQ9_502

#NET PS_DDR3_DQ9 LOC = L1 ; # Bank 502 - PS_DDR_DQ10_502

#NET PS_DDR3_DQ13 LOC = L2 ; # Bank 502 - PS_DDR_DQ11_502

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#NET PS_DDR3_DM1 LOC = H3 ; # Bank 502 - PS_DDR_DM1_502

#NET PS_DDR3_DQS1_P LOC = H2 ; # Bank 502 - PS_DDR_DQS_P1_502

#NET PS_DDR3_DQS1_N LOC = J2 ; # Bank 502 - PS_DDR_DQS_N1_502

#NET PS_DDR3_DQ12 LOC = L3 ; # Bank 502 - PS_DDR_DQ12_502

#NET PS_DDR3_DQ11 LOC = K1 ; # Bank 502 - PS_DDR_DQ13_502

#NET PS_DDR3_DQ14 LOC = J1 ; # Bank 502 - PS_DDR_DQ14_502

#NET PS_DDR3_DQ15 LOC = K3 ; # Bank 502 - PS_DDR_DQ15_502

#NET PS_DDR3_A14 LOC = G4 ; # Bank 502 - PS_DDR_A14_502

#NET PS_DDR3_A13 LOC = F4 ; # Bank 502 - PS_DDR_A13_502

#NET PS_DDR3_A12 LOC = H4 ; # Bank 502 - PS_DDR_A12_502

#NET PS_DDR3_A11 LOC = G5 ; # Bank 502 - PS_DDR_A11_502

#NET PS_DDR3_A10 LOC = J3 ; # Bank 502 - PS_DDR_A10_502

#NET PS_DDR3_A9 LOC = H5 ; # Bank 502 - PS_DDR_A9_502

#NET PS_DDR3_A8 LOC = J5 ; # Bank 502 - PS_DDR_A8_502

#NET PS_DDR3_A7 LOC = J6 ; # Bank 502 - PS_DDR_A7_502

#NET PS_DDR3_A6 LOC = J7 ; # Bank 502 - PS_DDR_A6_502

#NET PS_DDR3_A5 LOC = K5 ; # Bank 502 - PS_DDR_A5_502

#NET PS_DDR3_A4 LOC = K6 ; # Bank 502 - PS_DDR_A4_502

#NET PS_DDR3_A3 LOC = L4 ; # Bank 502 - PS_DDR_A3_502

#NET PS_VRN LOC = M7 ; # Bank 502 - PS_DDR_VRN_502

#NET PS_VRP LOC = N7 ; # Bank 502 - PS_DDR_VRP_502

#NET PS_DDR3_CLK_P LOC = N4 ; # Bank 502 - PS_DDR_CKP_502

#NET PS_DDR3_CLK_N LOC = N5 ; # Bank 502 - PS_DDR_CKN_502

#NET PS_DDR3_A2 LOC = K4 ; # Bank 502 - PS_DDR_A2_502

#NET PS_DDR3_A1 LOC = M5 ; # Bank 502 - PS_DDR_A1_502

#NET PS_DDR3_A0 LOC = M4 ; # Bank 502 - PS_DDR_A0_502

#NET PS_DDR3_BA2 LOC = M6 ; # Bank 502 - PS_DDR_BA2_502

#NET PS_DDR3_BA1 LOC = L6 ; # Bank 502 - PS_DDR_BA1_502 = 1.5v

#NET PS_DDR3_BA0 LOC = L7 ; # Bank 502 - PS_DDR_BA0_502

#NET PS_DDR3_ODT LOC = P5 ; # Bank 502 - PS_DDR_ODT_502

#NET PS_DDR3_CS_B LOC = P6 ; # Bank 502 - PS_DDR_CS_B_502

#NET PS_DDR3_CKE LOC = V3 ; # Bank 502 - PS_DDR_CKE_502

#NET PS_DDR3_WE_B LOC = R4 ; # Bank 502 - PS_DDR_WE_B_502

#NET PS_DDR3_CAS_B LOC = P3 ; # Bank 502 - PS_DDR_CAS_B_502

#NET PS_DDR3_RAS_B LOC = R5 ; # Bank 502 - PS_DDR_RAS_B_502

#NET PS_DDR3_DQ16 LOC = M1 ; # Bank 502 - PS_DDR_DQ16_502

#NET PS_DDR3_DQ17 LOC = T3 ; # Bank 502 - PS_DDR_DQ17_502

#NET PS_DDR3_DQ18 LOC = N3 ; # Bank 502 - PS_DDR_DQ18_502

#NET PS_DDR3_DQ19 LOC = T1 ; # Bank 502 - PS_DDR_DQ19_502

#NET PS_DDR3_DM2 LOC = P1 ; # Bank 502 - PS_DDR_DM2_502

#NET PS_DDR3_DQS2_P LOC = N2 ; # Bank 502 - PS_DDR_DQS_P2_502

#NET PS_DDR3_DQS2_N LOC = P2 ; # Bank 502 - PS_DDR_DQS_N2_502

#NET PS_DDR3_DQ20 LOC = R3 ; # Bank 502 - PS_DDR_DQ20_502

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ZingOEM平台硬件用户手册

#NET PS_DDR3_DQ21 LOC = T2 ; # Bank 502 - PS_DDR_DQ21_502

#NET PS_DDR3_DQ22 LOC = M2 ; # Bank 502 - PS_DDR_DQ22_502

#NET PS_DDR3_DQ23 LOC = R1 ; # Bank 502 - PS_DDR_DQ23_502

#NET PS_DDR3_DQ27 LOC = AA3 ; # Bank 502 - PS_DDR_DQ24_502

#NET PS_DDR3_DQ24 LOC = U1 ; # Bank 502 - PS_DDR_DQ25_502

#NET PS_DDR3_DQ25 LOC = AA1 ; # Bank 502 - PS_DDR_DQ26_502

#NET PS_DDR3_DQ26 LOC = U2 ; # Bank 502 - PS_DDR_DQ27_502

#NET PS_DDR3_DM3 LOC = AA2 ; # Bank 502 - PS_DDR_DM3_502

#NET PS_DDR3_DQS3_P LOC = V2 ; # Bank 502 - PS_DDR_DQS_P3_502

#NET PS_DDR3_DQS3_N LOC = W2 ; # Bank 502 - PS_DDR_DQS_N3_502

#NET PS_DDR3_DQ28 LOC = W1 ; # Bank 502 - PS_DDR_DQ28_502

#NET PS_DDR3_DQ29 LOC = Y3 ; # Bank 502 - PS_DDR_DQ29_502

#NET PS_DDR3_DQ30 LOC = W3 ; # Bank 502 - PS_DDR_DQ30_502

#NET PS_DDR3_DQ31 LOC = Y1 ; # Bank 502 - PS_DDR_DQ31_502

#NET GND LOC = A5 ; # Bank 999 - GND

#NET GND LOC = A15 ; # Bank 999 - GND

#NET GND LOC = AA5 ; # Bank 999 - GND

#NET GND LOC = AA15 ; # Bank 999 - GND

#NET GND LOC = AB8 ; # Bank 999 - GND

#NET GND LOC = AB18 ; # Bank 999 - GND

#NET GND LOC = B8 ; # Bank 999 - GND

#NET GND LOC = B18 ; # Bank 999 - GND

#NET GND LOC = C1 ; # Bank 999 - GND

#NET GND LOC = C11 ; # Bank 999 - GND

#NET GND LOC = C21 ; # Bank 999 - GND

#NET GND LOC = D4 ; # Bank 999 - GND

#NET GND LOC = D14 ; # Bank 999 - GND

#NET GND LOC = E7 ; # Bank 999 - GND

#NET GND LOC = E17 ; # Bank 999 - GND

#NET GND LOC = F10 ; # Bank 999 - GND

#NET GND LOC = F20 ; # Bank 999 - GND

#NET GND LOC = G3 ; # Bank 999 - GND

#NET GND LOC = H6 ; # Bank 999 - GND

#NET GND LOC = H8 ; # Bank 999 - GND

#NET GND LOC = H12 ; # Bank 999 - GND

#NET GND LOC = H14 ; # Bank 999 - GND

#NET GND LOC = H16 ; # Bank 999 - GND

#NET GND LOC = J9 ; # Bank 999 - GND

#NET GND LOC = J11 ; # Bank 999 - GND

#NET GND LOC = J13 ; # Bank 999 - GND

#NET GND LOC = J19 ; # Bank 999 - GND

#NET GND LOC = K2 ; # Bank 999 - GND

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ZingOEM平台硬件用户手册

#NET GND LOC = K8 ; # Bank 999 - GND

#NET GND LOC = K10 ; # Bank 999 - GND

#NET GND LOC = K14 ; # Bank 999 - GND

#NET GND LOC = K22 ; # Bank 999 - GND

#NET GND LOC = L5 ; # Bank 999 - GND

#NET GND LOC = L9 ; # Bank 999 - GND

#NET GND LOC = L13 ; # Bank 999 - GND

#NET GND LOC = L15 ; # Bank 999 - GND

#NET GND LOC = M8 ; # Bank 999 - GND

#NET GND LOC = M10 ; # Bank 999 - GND

#NET GND LOC = M14 ; # Bank 999 - GND

#NET GND LOC = M18 ; # Bank 999 - GND

#NET GND LOC = N1 ; # Bank 999 - GND

#NET GND LOC = N9 ; # Bank 999 - GND

#NET GND LOC = N13 ; # Bank 999 - GND

#NET GND LOC = N21 ; # Bank 999 - GND

#NET GND LOC = P4 ; # Bank 999 - GND

#NET GND LOC = P8 ; # Bank 999 - GND

#NET GND LOC = P10 ; # Bank 999 - GND

#NET GND LOC = P12 ; # Bank 999 - GND

#NET GND LOC = P14 ; # Bank 999 - GND

#NET GND LOC = R9 ; # Bank 999 - GND

#NET GND LOC = R11 ; # Bank 999 - GND

#NET GND LOC = R13 ; # Bank 999 - GND

#NET GND LOC = R17 ; # Bank 999 - GND

#NET GND LOC = T20 ; # Bank 999 - GND

#NET GND LOC = U3 ; # Bank 999 - GND

#NET GND LOC = U13 ; # Bank 999 - GND

#NET GND LOC = V6 ; # Bank 999 - GND

#NET GND LOC = V16 ; # Bank 999 - GND

#NET GND LOC = W9 ; # Bank 999 - GND

#NET GND LOC = W19 ; # Bank 999 - GND

#NET GND LOC = Y2 ; # Bank 999 - GND

#NET GND LOC = Y12 ; # Bank 999 - GND

#NET GND LOC = Y22 ; # Bank 999 - GND

#NET VCCINT LOC = J12 ; # Bank 999 - VCCINT

#NET VCCINT LOC = J14 ; # Bank 999 - VCCINT

#NET VCCINT LOC = K13 ; # Bank 999 - VCCINT

#NET VCCINT LOC = L14 ; # Bank 999 - VCCINT

#NET VCCINT LOC = M13 ; # Bank 999 - VCCINT

#NET VCCINT LOC = N14 ; # Bank 999 - VCCINT

#NET VCCINT LOC = P13 ; # Bank 999 - VCCINT

#NET VCCINT LOC = R14 ; # Bank 999 - VCCINT

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ZingOEM平台硬件用户手册

#NET VCCAUX LOC = L10 ; # Bank 999 - VCCAUX

#NET VCCAUX LOC = N10 ; # Bank 999 - VCCAUX

#NET VCCAUX LOC = P11 ; # Bank 999 - VCCAUX

#NET VCCAUX LOC = R10 ; # Bank 999 - VCCAUX

#NET 2.5V_PL LOC = R12 ; # Bank 0 - VCCO_0

#NET VADJ LOC = AA10 ; # Bank 13 - VCCO_13

#NET VADJ LOC = AB3 ; # Bank 13 - VCCO_13

#NET VADJ LOC = T5 ; # Bank 13 - VCCO_13

#NET VADJ LOC = U8 ; # Bank 13 - VCCO_13

#NET VADJ LOC = V11 ; # Bank 13 - VCCO_13

#NET VADJ LOC = W4 ; # Bank 13 - VCCO_13

#NET VADJ LOC = Y7 ; # Bank 13 - VCCO_13

#NET VADJ LOC = AA20 ; # Bank 33 - VCCO_33

#NET VADJ LOC = AB13 ; # Bank 33 - VCCO_33

#NET VADJ LOC = U18 ; # Bank 33 - VCCO_33

#NET VADJ LOC = V21 ; # Bank 33 - VCCO_33

#NET VADJ LOC = W14 ; # Bank 33 - VCCO_33

#NET VADJ LOC = Y17 ; # Bank 33 - VCCO_33

#NET VADJ LOC = K17 ; # Bank 34 - VCCO_34

#NET VADJ LOC = L20 ; # Bank 34 - VCCO_34

#NET VADJ LOC = N16 ; # Bank 34 - VCCO_34

#NET VADJ LOC = P19 ; # Bank 34 - VCCO_34

#NET VADJ LOC = R22 ; # Bank 34 - VCCO_34

#NET VADJ LOC = T15 ; # Bank 34 - VCCO_34

#NET VADJ LOC = A20 ; # Bank 35 - VCCO_35

#NET VADJ LOC = C16 ; # Bank 35 - VCCO_35

#NET VADJ LOC = D19 ; # Bank 35 - VCCO_35

#NET VADJ LOC = E22 ; # Bank 35 - VCCO_35

#NET VADJ LOC = F15 ; # Bank 35 - VCCO_35

#NET VADJ LOC = G18 ; # Bank 35 - VCCO_35

#NET VADJ LOC = H21 ; # Bank 35 - VCCO_35

#NET VCCBRAM LOC = H11 ; # Bank 999 - VCCBRAM

#NET VCCBRAM LOC = J10 ; # Bank 999 - VCCBRAM

#NET 1.5V_PS LOC = E2 ; # Bank 502 - VCCO_DDR_502 = 1.5v

#NET 1.5V_PS LOC = F5 ; # Bank 502 - VCCO_DDR_502 = 1.5v

#NET 1.5V_PS LOC = H1 ; # Bank 502 - VCCO_DDR_502 = 1.5v

#NET 1.5V_PS LOC = J4 ; # Bank 502 - VCCO_DDR_502 = 1.5v

#NET 1.5V_PS LOC = K7 ; # Bank 502 - VCCO_DDR_502 = 1.5v

#NET 1.5V_PS LOC = M3 ; # Bank 502 - VCCO_DDR_502 = 1.5v

#NET 1.5V_PS LOC = N6 ; # Bank 502 - VCCO_DDR_502 = 1.5v

#NET 1.5V_PS LOC = R2 ; # Bank 502 - VCCO_DDR_502 = 1.5v

#NET 1.5V_PS LOC = V1 ; # Bank 502 - VCCO_DDR_502 = 1.5v

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ZingOEM平台硬件用户手册

#NET VCCPAUX LOC = H10 ; # Bank 999 - VCCPLL

#NET VCCPAUX LOC = K9 ; # Bank 999 - VCCPAUX

#NET VCCPAUX LOC = M9 ; # Bank 999 - VCCPAUX

#NET VCCPAUX LOC = P9 ; # Bank 999 - VCCPAUX

#NET VCCPAUX LOC = T9 ; # Bank 999 - VCCPAUX

#NET VCCPINT LOC = G8 ; # Bank 999 - VCCPINT

#NET VCCPINT LOC = H9 ; # Bank 999 - VCCPINT

#NET VCCPINT LOC = J8 ; # Bank 999 - VCCPINT

#NET VCCPINT LOC = L8 ; # Bank 999 - VCCPINT

#NET VCCPINT LOC = N8 ; # Bank 999 - VCCPINT

#NET VCCPINT LOC = R8 ; # Bank 999 - VCCPINT

#NET VCCMIO_PS LOC = B3 ; # Bank 500 - VCCO_MIO0_500 = 1.8v

#NET VCCMIO_PS LOC = C6 ; # Bank 500 - VCCO_MIO0_500 = 1.8v

#NET VCCMIO_PS LOC = A10 ; # Bank 501 - VCCO_MIO1_501 = 1.8v

#NET VCCMIO_PS LOC = B13 ; # Bank 501 - VCCO_MIO1_501 = 1.8v

#NET VCCMIO_PS LOC = D9 ; # Bank 501 - VCCO_MIO1_501 = 1.8v

#NET VCCMIO_PS LOC = E12 ; # Bank 501 - VCCO_MIO1_501 = 1.8v

#NET VTTVREF_PS LOC = H7 ; # Bank 502 - PS_DDR_VREF0_502 = 0.75v

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