2024年2月21日发(作者：伦如冰)

题分为两部分！

第一部分画图制pcb 版！

分9个图，要分别进行练习！

如下：

1、用protel99画出原理图，并制出相应的3000*3000（mil）PCB板

其中：U1的封装为DIP14，U2的封装为DIP16，R1、R2的封装为AXIAL0.3，C1的封装为RAD0.2，Y1的封装为XTAL1，S1的封装为DIP16，J2的封装为SIP2。

2、用protel99画出原理图，并制出相应的3000*3000（mil）PCB板

其中：R1、R2、R3、R4、Rc、RL的封装为AXIAL0.4，Rw的封装为VR3，C1、C2、Ce的封装为RB.2/.4，Q1的封装为TO-92A，J1、

J2的封装为SIP2。

3、用protel99画出原理图，并制出相应的2000*2000（mil）PCB板

其中：R1、R2、R3的封装为AXIAL0.4，R的封装为VR2，UA741的封装为DIP8，JP1、JP2的封装为SIP2。

4、用protel99画出原理图，并制出相应的3000*3000（mil）PCB板

其中：R1、R2、R3、R4、R5、R6、R7的封装为AXIAL0.4，U1、U2、DS1的封装为DIP16。

5、用protel99画出原理图，并制出相应的2000*2000（mil）PCB板

其中：U1、U2的封装为DIP14，J1、J2的封装为SIP2。

6、用protel99画出原理图，并制出相应的2000*2000（mil）PCB板

其中：U1的封装为DIP16，U2、U3的封装为DIP14， J2的封装为SIP3。

7、用protel99画出原理图，并制出相应的2000*3000（mil）PCB板

其中：R1、R2、R3、R4、R5、R6、R7的封装为AXIAL0.4，Rw的封装为VR3，U1的封装为DIP8， J1的封装为SIP2。

8、用protel99画出原理图，并制出相应的2000*2000（mil）PCB板

其中： U1的封装为DIP16，U2的封装为DIP14，J1的封装为SIP6。

9、用protel99画出原理图，并制出相应的2000*2000（mil）PCB板

其中：U1的封装为DIP14，J1的封装为SIP2，R1、RS的封装为AXIAL0.4，R2的封装为VR3，C1的封装为RAD0.2。

第二部分，eda 的仿真实验！一共19种类型；

如下：

1、用VHDL语言编程设计四选一电路，并在MAX+PLUSⅡ上进行仿真验证。198页

LIBRARY IEEE;

USE _logic_;

ENTITY MUX41 IS

PORT(

A,B : IN STD_LOGIC;

X : IN STD_LOGIC_VECTOR(3 downto 0);

Y : OUT STD_LOGIC);

END ENTITY MUX41;

ARCHITECTURE ART OF MUX41 IS

SIGNAL SEL : STD_LOGIC_VECTOR(1 downto 0);

BEGIN

SEL<=B&A;

PROCESS (X, SEL)IS

BEGIN

IF(SEL="00") THEN

Y<=X(0);

ELSIF (SEL="01") THEN

Y<=X(1);

ELSIF (SEL="10")THEN

Y<=X(2);

ELSE

Y<=X(3);

END IF;

END PROCESS ;

END ART;

2、用VHDL语言编程设计四舍五入判别电路，输入为BCD码，输入大于等于五时，输出为1，否则为0，并在MAX+PLUSⅡ上进行仿真验证。讲过。

LIBRARY IEEE;

USE _LOGIC_;

ENTITY SHE IS

PORT(

A,B,C,D : IN STD_LOGIC;

y : OUT STD_LOGIC);

END SHE;

ARCHITECTURE A OF SHE IS

BEGIN

Y<=D OR (C AND A)OR(C AND B);

END A;

3、用VHDL语言编程设计八位双向总线缓冲器，EN=0时缓冲器工作，DIR=0时，由A向B传送数据，DIR=1时，由B向A传送数据，并在MAX+PLUSⅡ上进行仿真验证。200页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY BIDIR IS

PORT(

EN,DIR

A,B

: IN STD_LOGIC;

: INOUT STD_LOGIC_VECTOR(7 downto 0));

END BIDIR;

ARCHITECTURE a OF BIDIR IS

SIGNAL AOUT,BOUT: STD_LOGIC_VECTOR(7 DOWNTO 0);

BEGIN

PROCESS (A,EN,DIR) IS

BEGIN

IF (EN='0')AND(DIR='1') THEN BOUT<=A;

ELSE BOUT <="ZZZZZZZZ";

END IF;

B<=BOUT;

END PROCESS ;

PROCESS(B,EN,DIR) IS

BEGIN

IF (EN='0'AND DIR='1') THEN AOUT <=B;

ELSE AOUT<="ZZZZZZZZ";

END IF;

A<=AOUT;

END PROCESS;

END a;

4、用VHDL语言编程设计带使能端的8-3线优先编码器，并在MAX+PLUSⅡ上进行仿真验证。196页

LIBRARY IEEE;

USE _LOGIC_;

USE _LOGIC_;

ENTITY ENCODER1 IS

PORT(

A,B,C,D,E,F,G,H : IN STD_LOGIC;

Y0,Y1,Y2 : OUT STD_LOGIC);

END ENCODER1;

ARCHITECTURE ART OF ENCODER1 IS

SIGNAL SY: STD_LOGIC_VECTOR(2 DOWNTO 0);

BEGIN

PROCESS (H,G,F,E,D,C,B,A)IS

BEGIN

IF H='1' THEN SY<="111";

ELSIF G='1' THEN SY<="110";

ELSIF F='1' THEN SY<="101";

ELSIF E='1' THEN SY<="100";

ELSIF D='1' THEN SY<="011";

ELSIF C='1' THEN SY<="010";

ELSIF B='1' THEN SY<="001";

ELSIF A='1' THEN SY<="000";

ELSE SY<="XXX";

END IF;

END PROCESS;

Y0<=SY(0);

Y1<=SY(1);

Y2<=SY(2);

END ART;

5、用VHDL语言编程设计带使能端的JK触发器，并在MAX+PLUSⅡ上进行仿真验证。202页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY JKCFQ IS

PORT(

J,K,CLK : IN STD_LOGIC;

Q,QB : OUT STD_LOGIC);

END JKCFQ;

ARCHITECTURE ART OF JKCFQ IS

SIGNAL Q_S,QB_S: STD_LOGIC;

BEGIN

PROCESS (J,K,CLK)IS

BEGIN

IF (CLK'EVENT AND CLK='1') THEN

IF (J='1'AND K='0') THEN

Q_S<='1';QB_S<='0';

ELSIF (J='0'AND K='1') THEN

Q_S<='0';QB_S<='1';

ELSIF (J='1'AND K='1') THEN

Q_S<=NOT Q_S;QB_S<=NOT QB_S;

END IF;

END IF;

Q<=Q_S;

QB<=QB_S;

END PROCESS;

END ART;

6、用VHDL语言编程设计一位全加器，并在MAX+PLUSⅡ上进行仿真验证192页

--or

LIBRARY IEEE;

USE _LOGIC_;

ENTITY OR2A IS

PORT(

A, B : IN STD_LOGIC;

C : OUT STD_LOGIC);

END OR2A;

ARCHITECTURE a OF OR2A IS

BEGIN

C<=A OR B;

END a;

--h_adder

LIBRARY IEEE;

USE _LOGIC_;

ENTITY H_ADDER IS

PORT(

A, B : IN

SO, CO

STD_LOGIC;

: OUT STD_LOGIC);

END H_ADDER;

ARCHITECTURE a OF H_ADDER IS

BEGIN

SO<=(A OR B)AND(A NAND B);

CO<=NOT(A NAND B);

END a;

F_adder

LIBRARY IEEE;

USE _LOGIC_;

ENTITY F_ADDER IS

PORT(

AIN,BIN,CIN

SUM,CO

: IN STD_LOGIC;

: OUT STD_LOGIC);

END F_ADDER;

ARCHITECTURE a OF F_ADDER IS

COMPONENT H_ADDER

PORT(

A, B : IN STD_LOGIC;

SO, CO : OUT STD_LOGIC);

END COMPONENT;

COMPONENT OR2A

PORT(

A, B : IN STD_LOGIC;

C : OUT STD_LOGIC);

END COMPONENT;

SIGNAL S1,S2,S3 : STD_LOGIC;

BEGIN

U1: H_ADDER PORT MAP (AIN,BIN,CO=>S1,SO=>S2);

U2: H_ADDER PORT MAP (S2,CIN,S3,SUM);

U3: OR2A PORT MAP (A=>S1,B=>S3,C=>CO);

END a;

7、用VHDL语言编程设计一个8位的单向总线缓冲器，并在MAX+PLUSⅡ上进行仿真验证。200页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY TRI_BUFS IS

PORT(

EN: IN STD_LOGIC;

DIN

DOUT

: IN STD_LOGIC_VECTOR(7 downto 0);

: OUT STD_LOGIC_VECTOR(7 downto 0));

END ENTITY TRI_BUFS;

ARCHITECTURE ART OF TRI_BUFS IS

BEGIN

PROCESS (EN, DIN) IS

BEGIN

IF (EN='1') THEN

DOUT<=DIN;

ELSE

DOUT<="ZZZZZZZZ";

END IF;

END PROCESS ;

END ART;

7、用VHDL语言编程设计一个16位的单向总线缓冲器，并在MAX+PLUSⅡ上进行仿真验证。原理同上

LIBRARY IEEE;

USE _LOGIC_;

ENTITY TRI_BUFS1 IS

PORT(

EN: IN STD_LOGIC;

DIN

DOUT

: IN STD_LOGIC_VECTOR(15 downto 0);

: OUT STD_LOGIC_VECTOR(15 downto 0));

END ENTITY TRI_BUFS1;

ARCHITECTURE ART OF TRI_BUFS1 IS

BEGIN

PROCESS (EN, DIN) IS

BEGIN

IF (EN='1') THEN

DOUT<=DIN;

ELSE

DOUT<="ZZZZZZZZZZZZZZZZ";

END IF;

END PROCESS ;

END ART;

8、用VHDL语言编程设计设计同步复位的T触发器，并在MAX+PLUSⅡ上进行仿真验证。

LIBRARY IEEE;

USE _LOGIC_;

ENTITY TBTPCFQ IS

PORT(

CLK, CLR

Q , QB

: IN

STD_LOGIC;

: BUFFER STD_LOGIC);

END TBTPCFQ;

ARCHITECTURE a OF TBTPCFQ IS

BEGIN

PROCESS (CLK,CLR)

BEGIN

IF (CLK='1' AND CLK'EVENT) THEN

IF (CLR='1') THEN

Q <= '0';

QB <= '1';

ELSE

Q <= NOT Q;

QB <= NOT QB;

END IF;

END IF;

END PROCESS ;

END a;

9、用VHDL语言编程设计同步复位的T触发器，并在MAX+PLUSⅡ上进行仿真验证。

LIBRARY IEEE;

USE _LOGIC_;

ENTITY TBTCFQ IS

PORT(

CLK, CLR, T : IN STD_LOGIC;

Q , QB : BUFFER STD_LOGIC);

END TBTCFQ;

ARCHITECTURE a OF TBTCFQ IS

BEGIN

PROCESS (CLK,CLR,T)

BEGIN

IF (CLK='1' AND CLK'EVENT) THEN

IF (CLR='1') THEN

Q <= '0';

QB <= '1';

ELSIF(T='0') THEN

Q <= Q;

QB <= QB;

ELSE

Q <= NOT Q;

QB <= NOT QB;

END IF;

END IF;

END PROCESS ;

END a;

9、用VHDL语言编程设计带使能端的T触发器，并在Ⅱ上进行仿真验证。

LIBRARY IEEE;

USE _LOGIC_;

ENTITY SNTCFQ IS

PORT(

CLK, EN, T : IN STD_LOGIC;

Q , QB : BUFFER STD_LOGIC);

END SNTCFQ;

ARCHITECTURE a OF SNTCFQ IS

BEGIN

PROCESS (CLK,EN,T)

BEGIN

MAX+PLUS

IF EN='0' THEN

NULL;

ELSIF (CLK='1' AND CLK'EVENT) THEN

IF(T='0') THEN

Q <= Q;

QB <= QB;

ELSE

Q <= NOT Q;

QB <= NOT QB;

END IF;

END IF;

END PROCESS ;

END a;

10、用VHDL语言编程设计8位寄存器，并在MAX+PLUSⅡ上进行仿真验证。203页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY REG IS

PORT(

CLK : IN STD_LOGIC;

D : IN STD_LOGIC_VECTOR(8 downto 0);

Q : OUT STD_LOGIC_VECTOR(8 downto 0));

END ENTITY REG;

ARCHITECTURE ART OF REG IS

BEGIN

PROCESS (CLK, D) IS

BEGIN

IF (CLK'EVENT AND CLK='1') THEN

Q<=D;

END IF;

END PROCESS ;

END ART;

11、用VHDL语言编程设计一个8位的移位寄存器，具有左移一位或右移一位、并行输入和同步复位的功能，并在MAX+PLUSⅡ上进行仿真验证。204页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY SFTREG1 IS

PORT(

CLK ,RESET : IN STD_LOGIC;

LSFT,RSFT : IN STD_LOGIC;

DATA : IN STD_LOGIC_VECTOR(7 downto 0);

MODE : IN STD_LOGIC_VECTOR(1 downto 0);

QOUT : BUFFER STD_LOGIC_VECTOR(7 downto

0));

END ENTITY SFTREG1;

ARCHITECTURE ART OF SFTREG1 IS

BEGIN

PROCESS IS

BEGIN

WAIT UNTIL(RISING_EDGE(CLK));

IF (RESET='1') THEN

QOUT<="00000000";

ELSE

CASE MODE IS

WHEN "01" =>

QOUT<=RSFT&QOUT(7 DOWNTO 1);

WHEN "10"=>

QOUT<=QOUT(7 DOWNTO 1)&LSFT;

WHEN "11"=>

QOUT<=DATA;

WHEN OTHERS =>

NULL;

END CASE;

END IF;

END PROCESS;

END ARCHITECTURE ART;

12、用VHDL语言编程设计带使能端的RS触发器，并在MAX+PLUSⅡ上进行仿真验证。

LIBRARY IEEE;

USE _LOGIC_;

ENTITY SNRSCFQ IS

PORT(

CLK, R, S, EN

Q , QB

: IN STD_LOGIC;

: BUFFER STD_LOGIC);

END SNRSCFQ;

ARCHITECTURE a OF SNRSCFQ IS

BEGIN

PROCESS (CLK,R,S,EN)

BEGIN

IF(EN='0') THEN

NULL;

ELSIF (CLK='1' AND CLK'EVENT) THEN

IF (S='0' AND R='0') THEN

Q <= Q;

QB <= QB;

ELSIF(S='0' AND R='1') THEN

Q <= '0';

QB <= '1';

ELSIF(S='1' AND R='0') THEN

Q <= '1';

QB <= '0';

ELSE NULL;

END IF;

END IF;

END PROCESS ;

END a;

13、用VHDL语言编程设计带使能端、同步复位的RS触发器，并在MAX+PLUSⅡ上进行仿真验证。

LIBRARY IEEE;

USE _LOGIC_;

ENTITY SNTFRSCFQ IS

PORT(

CLK, R, S, EN, RES : IN

Q , QB

STD_LOGIC;

: BUFFER STD_LOGIC);

END SNTFRSCFQ;

ARCHITECTURE a OF SNTFRSCFQ IS

BEGIN

PROCESS (CLK,R,S,EN,RES)

BEGIN

IF(EN='0') THEN

NULL;

ELSIF (CLK='1' AND CLK'EVENT) THEN

IF(RES='1')THEN

Q <='0';

QB <='1';

ELSIF (S='0' AND R='0') THEN

Q <= Q;

QB <= QB;

ELSIF(S='0' AND R='1') THEN

Q <= '0';

QB <= '1';

ELSIF(S='1' AND R='0') THEN

Q <= '1';

QB <= '0';

ELSE NULL;

END IF;

END IF;

END PROCESS ;

END a;

14、用VHDL语言编程设计异步复位的D触发器，并在MAX+PLUSⅡ上进行仿真验证。201页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY ASYNDCFQ IS

PORT(

D,CLK,PRESET,CLR : IN STD_LOGIC;

Q : OUT STD_LOGIC

);

END ENTITY ASYNDCFQ;

ARCHITECTURE ART OF ASYNDCFQ IS

BEGIN

PROCESS(CLK,PRESET,CLR)IS

BEGIN

IF (PRESET='1') THEN

Q<='1';

ELSIF (CLR='1') THEN

Q<='0';

ELSIF (CLK'EVENT AND CLK='1')THEN

Q<=D;

END IF;

END PROCESS;

END ARCHITECTURE ART;

15、用VHDL语言编程设计带同步复位功能的D触发器，并在

MAX+PLUSⅡ上进行仿真验证。202页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY SYNDCFQ1 IS

PORT(

D,CLK,RESET : IN STD_LOGIC;

Q : OUT STD_LOGIC

);

END ENTITY SYNDCFQ1;

ARCHITECTURE ART OF SYNDCFQ1 IS

BEGIN

PROCESS(CLK)IS

BEGIN

IF (CLK'EVENT AND CLK ='1')THEN

IF (RESET='0') THEN

Q<='0';

ELSE

Q<=D;

END IF;

END IF;

END PROCESS;

END ARCHITECTURE ART;

16、用VHDL语言编程设计带使能引脚的D触发器，并在MAX+PLUSⅡ上进行仿真验证。201页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY DCFQ IS

PORT(

D,CLK : IN STD_LOGIC;

Q : OUT STD_LOGIC

);

END ENTITY DCFQ;

ARCHITECTURE ART OF DCFQ IS

BEGIN

PROCESS(CLK)IS

BEGIN

IF (CLK'EVENT AND CLK='1') THEN

Q<=D;

END IF;

END PROCESS;

END ARCHITECTURE ART;

16、用VHDL语言编程设计带使能端的D触发器，并在MAX+PLUSⅡ上进行仿真验证。201页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY DCFQ IS

PORT(

D,CLK : IN STD_LOGIC;

Q : OUT STD_LOGIC

);

END ENTITY DCFQ;

ARCHITECTURE ART OF DCFQ IS

BEGIN

PROCESS(CLK)IS

BEGIN

IF (CLK'EVENT AND CLK='1') THEN

Q<=D;

END IF;

END PROCESS;

END ARCHITECTURE ART;

17、用VHDL语言编程设计模为12的同步复位计数器，并在MAX+PLUSⅡ上进行仿真验证。205页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY CNT12 IS

PORT(

CLK : IN STD_LOGIC;

CLR : IN STD_LOGIC;

ENA : IN

CQ

STD_LOGIC;

: OUT INTEGER RANGE 0 TO 15;

STD_LOGIC); CO : OUT

END entity CNT12;

ARCHITECTURE ART OF CNT12 IS

SIGNAL CQI : INTEGER RANGE 0 TO 15;

BEGIN

PROCESS (CLK, CLR, ENA) IS

BEGIN

IF CLK'EVENT AND CLK='1' THEN

IF(CLR='1')THEN

CQI<=0;

ELSIF (ENA='1') THEN

IF(CQI=12)THEN

CQI<=0;

ELSE CQI<=CQI+1;

END IF;

END IF;

END IF;

END PROCESS;

PROCESS (CLK, CQI) IS

BEGIN

IF CLK'EVENT AND CLK='1' THEN

IF CQI=12 THEN CO<='1';

ELSE

CO<='0';END IF;

END IF;

END PROCESS ;

CQ<=CQI;

END ART;

18、用VHDL语言编程设计模6计数器，并在MAX+PLUSⅡ上进行仿真验证。205页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY CNT6 IS

PORT(

ENA : IN

CQ

STD_LOGIC;

: OUT INTEGER RANGE 0 TO 7;

STD_LOGIC); CO : OUT

END entity CNT6;

ARCHITECTURE ART OF CNT6 IS

SIGNAL CQI : INTEGER RANGE 0 TO 7;

BEGIN

PROCESS (ENA) IS

BEGIN

IF ENA='1' THEN

IF CQI=6 THEN CQI<=0;

ELSE CQI<=CQI+1; END IF;

END IF;

END PROCESS;

PROCESS (CQI) IS

BEGIN

IF CQI=6 THEN CO<='1';

ELSE

CO<='0';END IF;

END PROCESS ;

CQ<=CQI;

END ART;

18、用VHDL语言编程设计模8的计数器，并在MAX+PLUSⅡ上进行仿真验证。205页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY CNT8 IS

PORT(

ENA : IN

CQ

STD_LOGIC;

: OUT INTEGER RANGE 0 TO 15;

STD_LOGIC); CO : OUT

END entity CNT8;

ARCHITECTURE ART OF CNT8 IS

SIGNAL CQI : INTEGER RANGE 0 TO 15;

BEGIN

PROCESS (ENA) IS

BEGIN

IF ENA='1' THEN

IF CQI=8 THEN CQI<=0;

ELSE CQI<=CQI+1; END IF;

END IF;

END PROCESS;

PROCESS (CQI) IS

BEGIN

IF CQI=8 THEN CO<='1';

ELSE

CO<='0';END IF;

END PROCESS ;

CQ<=CQI;

END ART;

19、用VHDL语言编程设计带使能端、同步复位的模5计数器，并在MAX+PLUSⅡ上进行仿真验证。205页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY CNT5 IS

PORT(

CLK,EN : IN

CLR : IN

STD_LOGIC;

STD_LOGIC;

ENA : IN

CQ

STD_LOGIC;

: OUT INTEGER RANGE 0 TO 15;

STD_LOGIC); CO : OUT

END entity CNT5;

ARCHITECTURE ART OF CNT5 IS

SIGNAL CQI : INTEGER RANGE 0 TO 15;

BEGIN

PROCESS (CLK, CLR, ENA,EN) IS

BEGIN

IF EN='0' THEN

NULL;

ELSIF CLK'EVENT AND CLK='1' THEN

IF CLR='1' THEN CQI<=0;

ELSIF ENA='1' THEN

IF CQI=5 THEN CQI<=0;

ELSE CQI<=CQI+1; END IF;

END IF;

END IF;

END PROCESS ;

PROCESS (CLK, CQI) IS

BEGIN

IF CLK'EVENT AND CLK='1' THEN

IF CQI=5 THEN CO<='1';

ELSE

CO<='0';END IF;

END IF;

END PROCESS ;

CQ<=CQI;

END ART;

19、用VHDL语言编程设计带使能端、同步复位的模7计数器，并在MAX+PLUSⅡ上进行仿真验证。205页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY CNT7 IS

PORT(

CLK,EN : IN STD_LOGIC;

CLR : IN STD_LOGIC;

ENA : IN

CQ

STD_LOGIC;

: OUT INTEGER RANGE 0 TO 15;

STD_LOGIC); CO : OUT

END entity CNT7;

ARCHITECTURE ART OF CNT7 IS

SIGNAL CQI : INTEGER RANGE 0 TO 15;

BEGIN

PROCESS (CLK, CLR, ENA,EN) IS

BEGIN

IF EN='0' THEN

NULL;

ELSIF CLK'EVENT AND CLK='1' THEN

IF CLR='1' THEN

CQI<=0;

ELSIF ENA='1' THEN

IF CQI=7 THEN CQI<=0;

ELSE CQI<=CQI+1; END IF;

END IF;

END IF;

END PROCESS;

PROCESS (CLK, CQI) IS

BEGIN

IF CLK'EVENT AND CLK='1' THEN

IF CQI=7 THEN CO<='1';

ELSE

CO<='0';END IF;

END IF;

END PROCESS ;

CQ<=CQI;

END ART;

19、用VHDL语言编程设计带使能端、同步复位的模17计数器，并在MAX+PLUSⅡ上进行仿真验证。205页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY CNT17 IS

PORT(

CLK,EN : IN

CLR : IN

STD_LOGIC;

STD_LOGIC;

ENA : IN

CQ

STD_LOGIC;

: OUT INTEGER RANGE 0 TO 31;

STD_LOGIC); CO : OUT

END entity CNT17;

ARCHITECTURE ART OF CNT17 IS

SIGNAL CQI : INTEGER RANGE 0 TO 31;

BEGIN

PROCESS (CLK, CLR, ENA,EN) IS

BEGIN

IF(EN='0')THEN

NULL;

ELSIF CLK'EVENT AND CLK='1' THEN

IF(CLR='1')THEN

CQI<=0;

ELSIF (ENA='1') THEN

IF(CQI=17)THEN

CQI<=0;

ELSE CQI<=CQI+1;

END IF;

END IF;

END IF;

END PROCESS;

PROCESS (CLK, CQI) IS

BEGIN

IF CLK'EVENT AND CLK='1' THEN

IF CQI=17 THEN CO<='1';

ELSE

CO<='0';END IF;

END IF;

END PROCESS ;

CQ<=CQI;

END ART;

19、用VHDL语言编程设计带使能端、同步复位的模35计数器，并在MAX+PLUSⅡ上进行仿真验证。205页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY CNT35 IS

PORT(

CLK,EN : IN

CLR : IN

STD_LOGIC;

STD_LOGIC;

ENA : IN

CQ

STD_LOGIC;

: OUT INTEGER RANGE 0 TO 63;

STD_LOGIC); CO : OUT

END entity CNT35;

ARCHITECTURE ART OF CNT35 IS

SIGNAL CQI : INTEGER RANGE 0 TO 63;

BEGIN

PROCESS (CLK, CLR, ENA,EN) IS

BEGIN

IF EN='0' THEN

NULL;

ELSIF CLK'EVENT AND CLK='1' THEN

IF CLR='1' THEN

CQI<=0;

ELSIF ENA='1' THEN

IF CQI=35 THEN CQI<=0;

ELSE CQI<=CQI+1; END IF;

END IF;

END IF;

END PROCESS;

PROCESS (CLK, CQI) IS

BEGIN

IF CLK'EVENT AND CLK='1' THEN

IF CQI=35 THEN CO<='1';

ELSE

CO<='0';END IF;

END IF;

END PROCESS ;

CQ<=CQI;

END ART;

19、用VHDL语言编程设计带使能端、同步复位的模59计数器，并

在MAX+PLUSⅡ上进行仿真验证。205页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY CNT59 IS

PORT(

CLK,EN : IN

CLR : IN

STD_LOGIC;

STD_LOGIC;

ENA : IN

CQ

STD_LOGIC;

: OUT INTEGER RANGE 0 TO 59;

STD_LOGIC); CO : OUT

END entity CNT59;

ARCHITECTURE ART OF CNT59 IS

SIGNAL CQI : INTEGER RANGE 0 TO 63;

BEGIN

PROCESS (CLK, CLR, ENA,EN) IS

BEGIN

IF EN='0' THEN

NULL;

ELSIF CLK'EVENT AND CLK='1' THEN

IF CLR='1' THEN

CQI<=0;

ELSIF ENA='1' THEN

IF CQI=59 THEN CQI<=0;

ELSE CQI<=CQI+1; END IF;

END IF;

END IF;

END PROCESS;

PROCESS (CLK, CQI) IS

BEGIN

IF CLK'EVENT AND CLK='1' THEN

IF CQI=59 THEN CO<='1';

ELSE

CO<='0';END IF;

END IF;

END PROCESS ;

CQ<=CQI;

END ART;

____over!~

2024年2月21日发(作者：伦如冰)

题分为两部分！

第一部分画图制pcb 版！

分9个图，要分别进行练习！

如下：

1、用protel99画出原理图，并制出相应的3000*3000（mil）PCB板

其中：U1的封装为DIP14，U2的封装为DIP16，R1、R2的封装为AXIAL0.3，C1的封装为RAD0.2，Y1的封装为XTAL1，S1的封装为DIP16，J2的封装为SIP2。

2、用protel99画出原理图，并制出相应的3000*3000（mil）PCB板

其中：R1、R2、R3、R4、Rc、RL的封装为AXIAL0.4，Rw的封装为VR3，C1、C2、Ce的封装为RB.2/.4，Q1的封装为TO-92A，J1、

J2的封装为SIP2。

3、用protel99画出原理图，并制出相应的2000*2000（mil）PCB板

其中：R1、R2、R3的封装为AXIAL0.4，R的封装为VR2，UA741的封装为DIP8，JP1、JP2的封装为SIP2。

4、用protel99画出原理图，并制出相应的3000*3000（mil）PCB板

其中：R1、R2、R3、R4、R5、R6、R7的封装为AXIAL0.4，U1、U2、DS1的封装为DIP16。

5、用protel99画出原理图，并制出相应的2000*2000（mil）PCB板

其中：U1、U2的封装为DIP14，J1、J2的封装为SIP2。

6、用protel99画出原理图，并制出相应的2000*2000（mil）PCB板

其中：U1的封装为DIP16，U2、U3的封装为DIP14， J2的封装为SIP3。

7、用protel99画出原理图，并制出相应的2000*3000（mil）PCB板

其中：R1、R2、R3、R4、R5、R6、R7的封装为AXIAL0.4，Rw的封装为VR3，U1的封装为DIP8， J1的封装为SIP2。

8、用protel99画出原理图，并制出相应的2000*2000（mil）PCB板

其中： U1的封装为DIP16，U2的封装为DIP14，J1的封装为SIP6。

9、用protel99画出原理图，并制出相应的2000*2000（mil）PCB板

其中：U1的封装为DIP14，J1的封装为SIP2，R1、RS的封装为AXIAL0.4，R2的封装为VR3，C1的封装为RAD0.2。

第二部分，eda 的仿真实验！一共19种类型；

如下：

1、用VHDL语言编程设计四选一电路，并在MAX+PLUSⅡ上进行仿真验证。198页

LIBRARY IEEE;

USE _logic_;

ENTITY MUX41 IS

PORT(

A,B : IN STD_LOGIC;

X : IN STD_LOGIC_VECTOR(3 downto 0);

Y : OUT STD_LOGIC);

END ENTITY MUX41;

ARCHITECTURE ART OF MUX41 IS

SIGNAL SEL : STD_LOGIC_VECTOR(1 downto 0);

BEGIN

SEL<=B&A;

PROCESS (X, SEL)IS

BEGIN

IF(SEL="00") THEN

Y<=X(0);

ELSIF (SEL="01") THEN

Y<=X(1);

ELSIF (SEL="10")THEN

Y<=X(2);

ELSE

Y<=X(3);

END IF;

END PROCESS ;

END ART;

2、用VHDL语言编程设计四舍五入判别电路，输入为BCD码，输入大于等于五时，输出为1，否则为0，并在MAX+PLUSⅡ上进行仿真验证。讲过。

LIBRARY IEEE;

USE _LOGIC_;

ENTITY SHE IS

PORT(

A,B,C,D : IN STD_LOGIC;

y : OUT STD_LOGIC);

END SHE;

ARCHITECTURE A OF SHE IS

BEGIN

Y<=D OR (C AND A)OR(C AND B);

END A;

3、用VHDL语言编程设计八位双向总线缓冲器，EN=0时缓冲器工作，DIR=0时，由A向B传送数据，DIR=1时，由B向A传送数据，并在MAX+PLUSⅡ上进行仿真验证。200页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY BIDIR IS

PORT(

EN,DIR

A,B

: IN STD_LOGIC;

: INOUT STD_LOGIC_VECTOR(7 downto 0));

END BIDIR;

ARCHITECTURE a OF BIDIR IS

SIGNAL AOUT,BOUT: STD_LOGIC_VECTOR(7 DOWNTO 0);

BEGIN

PROCESS (A,EN,DIR) IS

BEGIN

IF (EN='0')AND(DIR='1') THEN BOUT<=A;

ELSE BOUT <="ZZZZZZZZ";

END IF;

B<=BOUT;

END PROCESS ;

PROCESS(B,EN,DIR) IS

BEGIN

IF (EN='0'AND DIR='1') THEN AOUT <=B;

ELSE AOUT<="ZZZZZZZZ";

END IF;

A<=AOUT;

END PROCESS;

END a;

4、用VHDL语言编程设计带使能端的8-3线优先编码器，并在MAX+PLUSⅡ上进行仿真验证。196页

LIBRARY IEEE;

USE _LOGIC_;

USE _LOGIC_;

ENTITY ENCODER1 IS

PORT(

A,B,C,D,E,F,G,H : IN STD_LOGIC;

Y0,Y1,Y2 : OUT STD_LOGIC);

END ENCODER1;

ARCHITECTURE ART OF ENCODER1 IS

SIGNAL SY: STD_LOGIC_VECTOR(2 DOWNTO 0);

BEGIN

PROCESS (H,G,F,E,D,C,B,A)IS

BEGIN

IF H='1' THEN SY<="111";

ELSIF G='1' THEN SY<="110";

ELSIF F='1' THEN SY<="101";

ELSIF E='1' THEN SY<="100";

ELSIF D='1' THEN SY<="011";

ELSIF C='1' THEN SY<="010";

ELSIF B='1' THEN SY<="001";

ELSIF A='1' THEN SY<="000";

ELSE SY<="XXX";

END IF;

END PROCESS;

Y0<=SY(0);

Y1<=SY(1);

Y2<=SY(2);

END ART;

5、用VHDL语言编程设计带使能端的JK触发器，并在MAX+PLUSⅡ上进行仿真验证。202页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY JKCFQ IS

PORT(

J,K,CLK : IN STD_LOGIC;

Q,QB : OUT STD_LOGIC);

END JKCFQ;

ARCHITECTURE ART OF JKCFQ IS

SIGNAL Q_S,QB_S: STD_LOGIC;

BEGIN

PROCESS (J,K,CLK)IS

BEGIN

IF (CLK'EVENT AND CLK='1') THEN

IF (J='1'AND K='0') THEN

Q_S<='1';QB_S<='0';

ELSIF (J='0'AND K='1') THEN

Q_S<='0';QB_S<='1';

ELSIF (J='1'AND K='1') THEN

Q_S<=NOT Q_S;QB_S<=NOT QB_S;

END IF;

END IF;

Q<=Q_S;

QB<=QB_S;

END PROCESS;

END ART;

6、用VHDL语言编程设计一位全加器，并在MAX+PLUSⅡ上进行仿真验证192页

--or

LIBRARY IEEE;

USE _LOGIC_;

ENTITY OR2A IS

PORT(

A, B : IN STD_LOGIC;

C : OUT STD_LOGIC);

END OR2A;

ARCHITECTURE a OF OR2A IS

BEGIN

C<=A OR B;

END a;

--h_adder

LIBRARY IEEE;

USE _LOGIC_;

ENTITY H_ADDER IS

PORT(

A, B : IN

SO, CO

STD_LOGIC;

: OUT STD_LOGIC);

END H_ADDER;

ARCHITECTURE a OF H_ADDER IS

BEGIN

SO<=(A OR B)AND(A NAND B);

CO<=NOT(A NAND B);

END a;

F_adder

LIBRARY IEEE;

USE _LOGIC_;

ENTITY F_ADDER IS

PORT(

AIN,BIN,CIN

SUM,CO

: IN STD_LOGIC;

: OUT STD_LOGIC);

END F_ADDER;

ARCHITECTURE a OF F_ADDER IS

COMPONENT H_ADDER

PORT(

A, B : IN STD_LOGIC;

SO, CO : OUT STD_LOGIC);

END COMPONENT;

COMPONENT OR2A

PORT(

A, B : IN STD_LOGIC;

C : OUT STD_LOGIC);

END COMPONENT;

SIGNAL S1,S2,S3 : STD_LOGIC;

BEGIN

U1: H_ADDER PORT MAP (AIN,BIN,CO=>S1,SO=>S2);

U2: H_ADDER PORT MAP (S2,CIN,S3,SUM);

U3: OR2A PORT MAP (A=>S1,B=>S3,C=>CO);

END a;

7、用VHDL语言编程设计一个8位的单向总线缓冲器，并在MAX+PLUSⅡ上进行仿真验证。200页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY TRI_BUFS IS

PORT(

EN: IN STD_LOGIC;

DIN

DOUT

: IN STD_LOGIC_VECTOR(7 downto 0);

: OUT STD_LOGIC_VECTOR(7 downto 0));

END ENTITY TRI_BUFS;

ARCHITECTURE ART OF TRI_BUFS IS

BEGIN

PROCESS (EN, DIN) IS

BEGIN

IF (EN='1') THEN

DOUT<=DIN;

ELSE

DOUT<="ZZZZZZZZ";

END IF;

END PROCESS ;

END ART;

7、用VHDL语言编程设计一个16位的单向总线缓冲器，并在MAX+PLUSⅡ上进行仿真验证。原理同上

LIBRARY IEEE;

USE _LOGIC_;

ENTITY TRI_BUFS1 IS

PORT(

EN: IN STD_LOGIC;

DIN

DOUT

: IN STD_LOGIC_VECTOR(15 downto 0);

: OUT STD_LOGIC_VECTOR(15 downto 0));

END ENTITY TRI_BUFS1;

ARCHITECTURE ART OF TRI_BUFS1 IS

BEGIN

PROCESS (EN, DIN) IS

BEGIN

IF (EN='1') THEN

DOUT<=DIN;

ELSE

DOUT<="ZZZZZZZZZZZZZZZZ";

END IF;

END PROCESS ;

END ART;

8、用VHDL语言编程设计设计同步复位的T触发器，并在MAX+PLUSⅡ上进行仿真验证。

LIBRARY IEEE;

USE _LOGIC_;

ENTITY TBTPCFQ IS

PORT(

CLK, CLR

Q , QB

: IN

STD_LOGIC;

: BUFFER STD_LOGIC);

END TBTPCFQ;

ARCHITECTURE a OF TBTPCFQ IS

BEGIN

PROCESS (CLK,CLR)

BEGIN

IF (CLK='1' AND CLK'EVENT) THEN

IF (CLR='1') THEN

Q <= '0';

QB <= '1';

ELSE

Q <= NOT Q;

QB <= NOT QB;

END IF;

END IF;

END PROCESS ;

END a;

9、用VHDL语言编程设计同步复位的T触发器，并在MAX+PLUSⅡ上进行仿真验证。

LIBRARY IEEE;

USE _LOGIC_;

ENTITY TBTCFQ IS

PORT(

CLK, CLR, T : IN STD_LOGIC;

Q , QB : BUFFER STD_LOGIC);

END TBTCFQ;

ARCHITECTURE a OF TBTCFQ IS

BEGIN

PROCESS (CLK,CLR,T)

BEGIN

IF (CLK='1' AND CLK'EVENT) THEN

IF (CLR='1') THEN

Q <= '0';

QB <= '1';

ELSIF(T='0') THEN

Q <= Q;

QB <= QB;

ELSE

Q <= NOT Q;

QB <= NOT QB;

END IF;

END IF;

END PROCESS ;

END a;

9、用VHDL语言编程设计带使能端的T触发器，并在Ⅱ上进行仿真验证。

LIBRARY IEEE;

USE _LOGIC_;

ENTITY SNTCFQ IS

PORT(

CLK, EN, T : IN STD_LOGIC;

Q , QB : BUFFER STD_LOGIC);

END SNTCFQ;

ARCHITECTURE a OF SNTCFQ IS

BEGIN

PROCESS (CLK,EN,T)

BEGIN

MAX+PLUS

IF EN='0' THEN

NULL;

ELSIF (CLK='1' AND CLK'EVENT) THEN

IF(T='0') THEN

Q <= Q;

QB <= QB;

ELSE

Q <= NOT Q;

QB <= NOT QB;

END IF;

END IF;

END PROCESS ;

END a;

10、用VHDL语言编程设计8位寄存器，并在MAX+PLUSⅡ上进行仿真验证。203页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY REG IS

PORT(

CLK : IN STD_LOGIC;

D : IN STD_LOGIC_VECTOR(8 downto 0);

Q : OUT STD_LOGIC_VECTOR(8 downto 0));

END ENTITY REG;

ARCHITECTURE ART OF REG IS

BEGIN

PROCESS (CLK, D) IS

BEGIN

IF (CLK'EVENT AND CLK='1') THEN

Q<=D;

END IF;

END PROCESS ;

END ART;

11、用VHDL语言编程设计一个8位的移位寄存器，具有左移一位或右移一位、并行输入和同步复位的功能，并在MAX+PLUSⅡ上进行仿真验证。204页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY SFTREG1 IS

PORT(

CLK ,RESET : IN STD_LOGIC;

LSFT,RSFT : IN STD_LOGIC;

DATA : IN STD_LOGIC_VECTOR(7 downto 0);

MODE : IN STD_LOGIC_VECTOR(1 downto 0);

QOUT : BUFFER STD_LOGIC_VECTOR(7 downto

0));

END ENTITY SFTREG1;

ARCHITECTURE ART OF SFTREG1 IS

BEGIN

PROCESS IS

BEGIN

WAIT UNTIL(RISING_EDGE(CLK));

IF (RESET='1') THEN

QOUT<="00000000";

ELSE

CASE MODE IS

WHEN "01" =>

QOUT<=RSFT&QOUT(7 DOWNTO 1);

WHEN "10"=>

QOUT<=QOUT(7 DOWNTO 1)&LSFT;

WHEN "11"=>

QOUT<=DATA;

WHEN OTHERS =>

NULL;

END CASE;

END IF;

END PROCESS;

END ARCHITECTURE ART;

12、用VHDL语言编程设计带使能端的RS触发器，并在MAX+PLUSⅡ上进行仿真验证。

LIBRARY IEEE;

USE _LOGIC_;

ENTITY SNRSCFQ IS

PORT(

CLK, R, S, EN

Q , QB

: IN STD_LOGIC;

: BUFFER STD_LOGIC);

END SNRSCFQ;

ARCHITECTURE a OF SNRSCFQ IS

BEGIN

PROCESS (CLK,R,S,EN)

BEGIN

IF(EN='0') THEN

NULL;

ELSIF (CLK='1' AND CLK'EVENT) THEN

IF (S='0' AND R='0') THEN

Q <= Q;

QB <= QB;

ELSIF(S='0' AND R='1') THEN

Q <= '0';

QB <= '1';

ELSIF(S='1' AND R='0') THEN

Q <= '1';

QB <= '0';

ELSE NULL;

END IF;

END IF;

END PROCESS ;

END a;

13、用VHDL语言编程设计带使能端、同步复位的RS触发器，并在MAX+PLUSⅡ上进行仿真验证。

LIBRARY IEEE;

USE _LOGIC_;

ENTITY SNTFRSCFQ IS

PORT(

CLK, R, S, EN, RES : IN

Q , QB

STD_LOGIC;

: BUFFER STD_LOGIC);

END SNTFRSCFQ;

ARCHITECTURE a OF SNTFRSCFQ IS

BEGIN

PROCESS (CLK,R,S,EN,RES)

BEGIN

IF(EN='0') THEN

NULL;

ELSIF (CLK='1' AND CLK'EVENT) THEN

IF(RES='1')THEN

Q <='0';

QB <='1';

ELSIF (S='0' AND R='0') THEN

Q <= Q;

QB <= QB;

ELSIF(S='0' AND R='1') THEN

Q <= '0';

QB <= '1';

ELSIF(S='1' AND R='0') THEN

Q <= '1';

QB <= '0';

ELSE NULL;

END IF;

END IF;

END PROCESS ;

END a;

14、用VHDL语言编程设计异步复位的D触发器，并在MAX+PLUSⅡ上进行仿真验证。201页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY ASYNDCFQ IS

PORT(

D,CLK,PRESET,CLR : IN STD_LOGIC;

Q : OUT STD_LOGIC

);

END ENTITY ASYNDCFQ;

ARCHITECTURE ART OF ASYNDCFQ IS

BEGIN

PROCESS(CLK,PRESET,CLR)IS

BEGIN

IF (PRESET='1') THEN

Q<='1';

ELSIF (CLR='1') THEN

Q<='0';

ELSIF (CLK'EVENT AND CLK='1')THEN

Q<=D;

END IF;

END PROCESS;

END ARCHITECTURE ART;

15、用VHDL语言编程设计带同步复位功能的D触发器，并在

MAX+PLUSⅡ上进行仿真验证。202页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY SYNDCFQ1 IS

PORT(

D,CLK,RESET : IN STD_LOGIC;

Q : OUT STD_LOGIC

);

END ENTITY SYNDCFQ1;

ARCHITECTURE ART OF SYNDCFQ1 IS

BEGIN

PROCESS(CLK)IS

BEGIN

IF (CLK'EVENT AND CLK ='1')THEN

IF (RESET='0') THEN

Q<='0';

ELSE

Q<=D;

END IF;

END IF;

END PROCESS;

END ARCHITECTURE ART;

16、用VHDL语言编程设计带使能引脚的D触发器，并在MAX+PLUSⅡ上进行仿真验证。201页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY DCFQ IS

PORT(

D,CLK : IN STD_LOGIC;

Q : OUT STD_LOGIC

);

END ENTITY DCFQ;

ARCHITECTURE ART OF DCFQ IS

BEGIN

PROCESS(CLK)IS

BEGIN

IF (CLK'EVENT AND CLK='1') THEN

Q<=D;

END IF;

END PROCESS;

END ARCHITECTURE ART;

16、用VHDL语言编程设计带使能端的D触发器，并在MAX+PLUSⅡ上进行仿真验证。201页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY DCFQ IS

PORT(

D,CLK : IN STD_LOGIC;

Q : OUT STD_LOGIC

);

END ENTITY DCFQ;

ARCHITECTURE ART OF DCFQ IS

BEGIN

PROCESS(CLK)IS

BEGIN

IF (CLK'EVENT AND CLK='1') THEN

Q<=D;

END IF;

END PROCESS;

END ARCHITECTURE ART;

17、用VHDL语言编程设计模为12的同步复位计数器，并在MAX+PLUSⅡ上进行仿真验证。205页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY CNT12 IS

PORT(

CLK : IN STD_LOGIC;

CLR : IN STD_LOGIC;

ENA : IN

CQ

STD_LOGIC;

: OUT INTEGER RANGE 0 TO 15;

STD_LOGIC); CO : OUT

END entity CNT12;

ARCHITECTURE ART OF CNT12 IS

SIGNAL CQI : INTEGER RANGE 0 TO 15;

BEGIN

PROCESS (CLK, CLR, ENA) IS

BEGIN

IF CLK'EVENT AND CLK='1' THEN

IF(CLR='1')THEN

CQI<=0;

ELSIF (ENA='1') THEN

IF(CQI=12)THEN

CQI<=0;

ELSE CQI<=CQI+1;

END IF;

END IF;

END IF;

END PROCESS;

PROCESS (CLK, CQI) IS

BEGIN

IF CLK'EVENT AND CLK='1' THEN

IF CQI=12 THEN CO<='1';

ELSE

CO<='0';END IF;

END IF;

END PROCESS ;

CQ<=CQI;

END ART;

18、用VHDL语言编程设计模6计数器，并在MAX+PLUSⅡ上进行仿真验证。205页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY CNT6 IS

PORT(

ENA : IN

CQ

STD_LOGIC;

: OUT INTEGER RANGE 0 TO 7;

STD_LOGIC); CO : OUT

END entity CNT6;

ARCHITECTURE ART OF CNT6 IS

SIGNAL CQI : INTEGER RANGE 0 TO 7;

BEGIN

PROCESS (ENA) IS

BEGIN

IF ENA='1' THEN

IF CQI=6 THEN CQI<=0;

ELSE CQI<=CQI+1; END IF;

END IF;

END PROCESS;

PROCESS (CQI) IS

BEGIN

IF CQI=6 THEN CO<='1';

ELSE

CO<='0';END IF;

END PROCESS ;

CQ<=CQI;

END ART;

18、用VHDL语言编程设计模8的计数器，并在MAX+PLUSⅡ上进行仿真验证。205页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY CNT8 IS

PORT(

ENA : IN

CQ

STD_LOGIC;

: OUT INTEGER RANGE 0 TO 15;

STD_LOGIC); CO : OUT

END entity CNT8;

ARCHITECTURE ART OF CNT8 IS

SIGNAL CQI : INTEGER RANGE 0 TO 15;

BEGIN

PROCESS (ENA) IS

BEGIN

IF ENA='1' THEN

IF CQI=8 THEN CQI<=0;

ELSE CQI<=CQI+1; END IF;

END IF;

END PROCESS;

PROCESS (CQI) IS

BEGIN

IF CQI=8 THEN CO<='1';

ELSE

CO<='0';END IF;

END PROCESS ;

CQ<=CQI;

END ART;

19、用VHDL语言编程设计带使能端、同步复位的模5计数器，并在MAX+PLUSⅡ上进行仿真验证。205页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY CNT5 IS

PORT(

CLK,EN : IN

CLR : IN

STD_LOGIC;

STD_LOGIC;

ENA : IN

CQ

STD_LOGIC;

: OUT INTEGER RANGE 0 TO 15;

STD_LOGIC); CO : OUT

END entity CNT5;

ARCHITECTURE ART OF CNT5 IS

SIGNAL CQI : INTEGER RANGE 0 TO 15;

BEGIN

PROCESS (CLK, CLR, ENA,EN) IS

BEGIN

IF EN='0' THEN

NULL;

ELSIF CLK'EVENT AND CLK='1' THEN

IF CLR='1' THEN CQI<=0;

ELSIF ENA='1' THEN

IF CQI=5 THEN CQI<=0;

ELSE CQI<=CQI+1; END IF;

END IF;

END IF;

END PROCESS ;

PROCESS (CLK, CQI) IS

BEGIN

IF CLK'EVENT AND CLK='1' THEN

IF CQI=5 THEN CO<='1';

ELSE

CO<='0';END IF;

END IF;

END PROCESS ;

CQ<=CQI;

END ART;

19、用VHDL语言编程设计带使能端、同步复位的模7计数器，并在MAX+PLUSⅡ上进行仿真验证。205页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY CNT7 IS

PORT(

CLK,EN : IN STD_LOGIC;

CLR : IN STD_LOGIC;

ENA : IN

CQ

STD_LOGIC;

: OUT INTEGER RANGE 0 TO 15;

STD_LOGIC); CO : OUT

END entity CNT7;

ARCHITECTURE ART OF CNT7 IS

SIGNAL CQI : INTEGER RANGE 0 TO 15;

BEGIN

PROCESS (CLK, CLR, ENA,EN) IS

BEGIN

IF EN='0' THEN

NULL;

ELSIF CLK'EVENT AND CLK='1' THEN

IF CLR='1' THEN

CQI<=0;

ELSIF ENA='1' THEN

IF CQI=7 THEN CQI<=0;

ELSE CQI<=CQI+1; END IF;

END IF;

END IF;

END PROCESS;

PROCESS (CLK, CQI) IS

BEGIN

IF CLK'EVENT AND CLK='1' THEN

IF CQI=7 THEN CO<='1';

ELSE

CO<='0';END IF;

END IF;

END PROCESS ;

CQ<=CQI;

END ART;

19、用VHDL语言编程设计带使能端、同步复位的模17计数器，并在MAX+PLUSⅡ上进行仿真验证。205页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY CNT17 IS

PORT(

CLK,EN : IN

CLR : IN

STD_LOGIC;

STD_LOGIC;

ENA : IN

CQ

STD_LOGIC;

: OUT INTEGER RANGE 0 TO 31;

STD_LOGIC); CO : OUT

END entity CNT17;

ARCHITECTURE ART OF CNT17 IS

SIGNAL CQI : INTEGER RANGE 0 TO 31;

BEGIN

PROCESS (CLK, CLR, ENA,EN) IS

BEGIN

IF(EN='0')THEN

NULL;

ELSIF CLK'EVENT AND CLK='1' THEN

IF(CLR='1')THEN

CQI<=0;

ELSIF (ENA='1') THEN

IF(CQI=17)THEN

CQI<=0;

ELSE CQI<=CQI+1;

END IF;

END IF;

END IF;

END PROCESS;

PROCESS (CLK, CQI) IS

BEGIN

IF CLK'EVENT AND CLK='1' THEN

IF CQI=17 THEN CO<='1';

ELSE

CO<='0';END IF;

END IF;

END PROCESS ;

CQ<=CQI;

END ART;

19、用VHDL语言编程设计带使能端、同步复位的模35计数器，并在MAX+PLUSⅡ上进行仿真验证。205页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY CNT35 IS

PORT(

CLK,EN : IN

CLR : IN

STD_LOGIC;

STD_LOGIC;

ENA : IN

CQ

STD_LOGIC;

: OUT INTEGER RANGE 0 TO 63;

STD_LOGIC); CO : OUT

END entity CNT35;

ARCHITECTURE ART OF CNT35 IS

SIGNAL CQI : INTEGER RANGE 0 TO 63;

BEGIN

PROCESS (CLK, CLR, ENA,EN) IS

BEGIN

IF EN='0' THEN

NULL;

ELSIF CLK'EVENT AND CLK='1' THEN

IF CLR='1' THEN

CQI<=0;

ELSIF ENA='1' THEN

IF CQI=35 THEN CQI<=0;

ELSE CQI<=CQI+1; END IF;

END IF;

END IF;

END PROCESS;

PROCESS (CLK, CQI) IS

BEGIN

IF CLK'EVENT AND CLK='1' THEN

IF CQI=35 THEN CO<='1';

ELSE

CO<='0';END IF;

END IF;

END PROCESS ;

CQ<=CQI;

END ART;

19、用VHDL语言编程设计带使能端、同步复位的模59计数器，并

在MAX+PLUSⅡ上进行仿真验证。205页

LIBRARY IEEE;

USE _LOGIC_;

ENTITY CNT59 IS

PORT(

CLK,EN : IN

CLR : IN

STD_LOGIC;

STD_LOGIC;

ENA : IN

CQ

STD_LOGIC;

: OUT INTEGER RANGE 0 TO 59;

STD_LOGIC); CO : OUT

END entity CNT59;

ARCHITECTURE ART OF CNT59 IS

SIGNAL CQI : INTEGER RANGE 0 TO 63;

BEGIN

PROCESS (CLK, CLR, ENA,EN) IS

BEGIN

IF EN='0' THEN

NULL;

ELSIF CLK'EVENT AND CLK='1' THEN

IF CLR='1' THEN

CQI<=0;

ELSIF ENA='1' THEN

IF CQI=59 THEN CQI<=0;

ELSE CQI<=CQI+1; END IF;

END IF;

END IF;

END PROCESS;

PROCESS (CLK, CQI) IS

BEGIN

IF CLK'EVENT AND CLK='1' THEN

IF CQI=59 THEN CO<='1';

ELSE

CO<='0';END IF;

END IF;

END PROCESS ;

CQ<=CQI;

END ART;

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