2024年3月15日发(作者：缑昆峰)
SIII52001-2.1
Electrical Characteristics
Operating Conditions
When Stratix
®
III devices are implemented in a system, they are rated according to a
set of defined parameters. To maintain the highest possible performance and
reliability of StratixIII devices, system designers must consider the operating
requirements discussed in this chapter. StratixIII devices are offered in both
commercial and industrial grades. Commercial devices are offered in –2 (fastest), –3,
–4 and –4L speed grades. Industrial devices are offered only in –3, –4, and –4L speed
grades.
1In this chapter, a prefix associated with the operating temperature range is attached to
the speed grades; commercial with “C” prefix and industrial with “I” prefix.
Commercial devices are therefore indicated as C2, C3, C4, and C4L per respective
speed grades. Industrial devices are indicated as I3, I4, and I4L.
Absolute Maximum Ratings
Absolute maximum ratings define the maximum operating conditions for StratixIII
devices. The values are based on experiments conducted with the device and
theoretical modeling of breakdown and damage mechanisms. The functional
operation of the device is not implied at these conditions. Conditions beyond those
listed in Table1–1 may cause permanent damage to the device. Additionally, device
operation at the absolute maximum ratings for extended periods may have adverse
effects on the device.
Table1–xIII Device Absolute Maximum Ratings (Note1)(Part 1 of 2)
Symbol
V
CCL
V
CC
V
CCD_PLL
V
CCA_PLL
V
CCPT
V
CCPGM
V
CCPD
V
CCIO
V
CC_CLKIN
V
CCBAT
V
I
Parameter
Selectable core voltage power supply
I/O registers power supply
PLL digital power supply
PLL analog power supply
Programmable power technology power supply
Configuration pins power supply
I/O pre-driver power supply
I/O power supply
Differential clock input power supply (top and bottom I/O
banks only)
Battery back-up power supply for design security volatile
key register
DC Input voltage
Minimum
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
Maximum
1.65
1.65
1.65
3.75
3.75
3.9
3.9
3.9
3.75
3.75
4.0
Unit
V
V
V
V
V
V
V
V
V
V
V
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
Switching Characteristics
Table1–xIII TriMatrix Memory Block Performance Specifications (Note1)(Part 3 of 3)
Memory
Block
Type
M144K
(3), (5)
Mode
Simple dual-port 2K × 64 (with ECC)
Min Pulse Width (Clock High Time)
Min Pulse Width (Clock Low Time )
TriMatrix
ALUTs
Memory
0
—
—
1
—
—
C2 (6)
V
CCL
=
1.1V
255
800
500
C3C4C4LI3
V
CCL
=
1.1V
195
1000
625
I4
V
CCL
=
1.1V
180
1100
690
I4L
V
CCL
=
0.9V
120
1800
1100
V
CCL
= V
CCL
= V
CCL
= V
CCL
=
1.1V1.1V1.1V0.9V
210
1000
625
180
1100
690
180
1100
690
130
1800
1100
Unit
MHz
ps
ps
Notes to Table1–22:
(1)Use a memory block clock that comes through global clock routing from an on-chip PLL set to 50% output duty cycle to achieve the maximum memory block
performance. Use Quartus II software to report timing for this and other memory block clocking schemes.
(2)The F
max
shown for M9K degrades 2 % when you use Error Detection CRC feature on the device, except for C4L speed grade with V
CCL
=0.9 V. For C4L speed
grade with V
CCL
=0.9V, there is no degradation in Fmax when Error Detection CRC feature is used.
(3)The F
max
shown for M144K degrades 10 MHz when you use byte-enable support on M144K.
(4)The F
max
is applicable when the COMPTABILITY option is turned ON.
(5)The F
max
is applicable when the COMPTABILITY option is turned OFF. This option is turned ON by default in QuartusII software.
(6)The F
max
for EP3SL200, EP3SE260, and EP3SL340 at C2 Speed Grade is 7% slower than the C2 values shown in the table.
Configuration and JTAG Specifications
Table1–23 lists the StratixIII Configuration Mode Specifications.
Table1–xIII Configuration Mode Specifications (Note1)
Programming Mode
Passive Serial
Fast Passive Parallel (2)
Fast Active Serial (3)
Notes to Table1–23:
(1)DCLK F
max
is restricted when Remote Update is enabled. For more information, refer to Remote Update Circuitry
(ALTREMOTE_UPDATE) Megafunction User Guide.
(2)Data rate must be 4× slower than the clock when decompression and/or encryption are used.
(3)For more information about the minimum and typical DCLK F
max
value in Fast Active Serial configuration, refer to
the Serial Configuration Devices Data Sheet chapter in Cyclone Device Handbook.
DCLK F
max
100
100
40
Unit
MHz
MHz
MHz
Table1–24 shows the JTAG timing parameters and values for StratixIII devices. Refer
to figure for “HIGH-SPEED I/O Block” in “Glossary” for JTAG timing requirements.
Table1–xIII JTAG Timing Parameters and Values
Symbol
t
JCP
t
JCH
t
JCL
t
JPSU
(TDI)
t
JPSU
(TMS)
t
JPH
t
JPCO
t
JPZX
t
JPXZ
Parameter
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time for TDI
JTAG port setup time for TMS
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Min
30
14
14
1
3
5
—
—
—
Max
—
—
—
—
—
—
11
14
14
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
Switching Characteristics
Periphery Performance
This section describes periphery performance, including high-speed I/O and external
memory interface.
I/O performance supports several system interfacing, such as the LVDS high-speed
I/O interface, external memory interface, and the PCI/PCI-X bus interface. For
example, StratixIII devices I/O configured with voltage referenced I/O standards can
achieve up to the stated system interfacing speed as indicated in “External Memory
Interface Specifications” on page1–25. General-purpose I/O standards such as 3.3,
3.0, 2.5, 1.8, or 1.5 LVTTL/LVCMOS are capable of typical 167 MHz and 1.2LVCMOS
at 100MHz interfacing frequency with 10pF load.
1Actual achievable frequency depends on design- and system-specific factors. You
should perform HSPICE/IBIS simulations based on your specific design and system
setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specifications
Refer to the “Glossary” for definitions of high-speed timing specifications.
Table1–25 shows the high-speed I/O timing for StratixIII devices.
Table1– & Emulated LVDS Specifications(Note1), (2)(Part 1 of 3)
Symbol
f
HSCLK_in
(input clock
frequency)
f
HSCLK_out
(output clock
frequency)
Transmitter
M
a
x
M
a
x
M
a
x
Clock boost
factor W = 1 to 40
(3)
—800—717—717—717
M
a
x
M
i
n
M
i
n
M
i
n
M
i
n
T
y
p
T
y
p
T
y
p
T
y
p
Conditions
MHz
—5—800 (7)5—717 (7)5—717 (7)5—717 (7)MHz
SERDES factor
J = 3 to 10 (8)
f
HSDR
(data rate)
(4)
(4)
—
—
1600
(4)
(4)
(4)
—
—
1250
(4)
(4)
(4)
—
—
1250
(4)
(4)
(4)
—
—
1250
(4)
Mbps
Mbps
SERDES factor
J = 2, Uses
DDR Register
SERDES factor
J = 1, Uses SDR
Register
(4)
(4)
(4)
—
—
—
(4)
1100
311
(4)
(4)
(4)
—
—
—
(4)
1100
200
(4)
(4)
(4)
—
—
—
(4)
800
200
(4)
(4)
(4)
—
—
—
(4)
800
200
Mbps
Mbps
Mbps
LVDS_E_3R -
f
HSDR
(data rate)
LVDS_E_1R -
f
HSDR
(data rate)
SERDES factor
J = 4 to 10
SERDES factor
J = 4 to 10
Stratix III Device Handbook, Volume 2
U
n
i
t
C2C3, I3C4, I4C4L, I4L
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table1– Timing Measurement Methodology for Output Pins(Part 3 of 3)
I/O Standard
R
S
MINI-LVDS_E_1R
MINI-LVDS_E_3R
RSDS_E_1R
RSDS_E_3R
Notes to Table1–39:
(1)Hyper transport is not supported by StratixIII.
(2)LVPECL outputs are not supported by StratixIII.
(3)Quartus timing conditions can be changed using the Advanced I/O Timing feature.
(4)V
CC
is nominally 1.1 V less 50 mV (1.05 V).
(5)Terminated I/O standards require an additional 30 mV IR drop on V
CC
(1.02 V).
(6)Terminated I/O standards required an additional 50 mV IR drop on V
CCIO
and V
CCPD
.
Loading and Terminations
R
D
100
100
100
100
R
T
—
—
—
—
R
P
120
170
120
170
V
CCIO
2.325
2.325
2.325
2.325
V
CCPD
2.325
2.325
2.325
2.325
V
CC
1.02
1.02
1.02
1.02
V
TT
—
—
—
—
C
L
(pF)
0
0
0
0
Measurement
Point
V
MEAS
(v)
1.1625
1.1625
1.1625
1.1625
—
120
—
120
I/O Default Capacitive Loading
See Table1–40 for default capacitive loading of different I/O standards.
Table1–t Loading of Different I/O Standards for StratixIII (Part 1 of 2)
I/O Standard
3.3-V LVTTL
3.3-V LVCMOS
3.0-V LVTTL
3.0-V LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVTTL/LVCMOS
3.0-V PCI
3.0-V PCI-X
SSTL-2 CLASSI
SSTL-2 CLASSII
SSTL-18 CLASSI
SSTL-18 CLASSII
1.5-V HSTL CLASSI
1.5-V HSTL CLASSII
1.8-V HSTL CLASSI
1.8-V HSTL CLASSII
1.2-V HSTL
Differential SSTL-2 CLASSI
Differential SSTL-2 CLASSII
Differential SSTL-18 CLASSI
Capacitive
Load
0
0
0
0
0
0
0
10
10
0
0
0
0
0
0
0
0
0
0
0
0
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
I/O Timing
Stratix III Device Handbook, Volume 2
2024年3月15日发(作者：缑昆峰)
SIII52001-2.1
Electrical Characteristics
Operating Conditions
When Stratix
®
III devices are implemented in a system, they are rated according to a
set of defined parameters. To maintain the highest possible performance and
reliability of StratixIII devices, system designers must consider the operating
requirements discussed in this chapter. StratixIII devices are offered in both
commercial and industrial grades. Commercial devices are offered in –2 (fastest), –3,
–4 and –4L speed grades. Industrial devices are offered only in –3, –4, and –4L speed
grades.
1In this chapter, a prefix associated with the operating temperature range is attached to
the speed grades; commercial with “C” prefix and industrial with “I” prefix.
Commercial devices are therefore indicated as C2, C3, C4, and C4L per respective
speed grades. Industrial devices are indicated as I3, I4, and I4L.
Absolute Maximum Ratings
Absolute maximum ratings define the maximum operating conditions for StratixIII
devices. The values are based on experiments conducted with the device and
theoretical modeling of breakdown and damage mechanisms. The functional
operation of the device is not implied at these conditions. Conditions beyond those
listed in Table1–1 may cause permanent damage to the device. Additionally, device
operation at the absolute maximum ratings for extended periods may have adverse
effects on the device.
Table1–xIII Device Absolute Maximum Ratings (Note1)(Part 1 of 2)
Symbol
V
CCL
V
CC
V
CCD_PLL
V
CCA_PLL
V
CCPT
V
CCPGM
V
CCPD
V
CCIO
V
CC_CLKIN
V
CCBAT
V
I
Parameter
Selectable core voltage power supply
I/O registers power supply
PLL digital power supply
PLL analog power supply
Programmable power technology power supply
Configuration pins power supply
I/O pre-driver power supply
I/O power supply
Differential clock input power supply (top and bottom I/O
banks only)
Battery back-up power supply for design security volatile
key register
DC Input voltage
Minimum
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
Maximum
1.65
1.65
1.65
3.75
3.75
3.9
3.9
3.9
3.75
3.75
4.0
Unit
V
V
V
V
V
V
V
V
V
V
V
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
Switching Characteristics
Table1–xIII TriMatrix Memory Block Performance Specifications (Note1)(Part 3 of 3)
Memory
Block
Type
M144K
(3), (5)
Mode
Simple dual-port 2K × 64 (with ECC)
Min Pulse Width (Clock High Time)
Min Pulse Width (Clock Low Time )
TriMatrix
ALUTs
Memory
0
—
—
1
—
—
C2 (6)
V
CCL
=
1.1V
255
800
500
C3C4C4LI3
V
CCL
=
1.1V
195
1000
625
I4
V
CCL
=
1.1V
180
1100
690
I4L
V
CCL
=
0.9V
120
1800
1100
V
CCL
= V
CCL
= V
CCL
= V
CCL
=
1.1V1.1V1.1V0.9V
210
1000
625
180
1100
690
180
1100
690
130
1800
1100
Unit
MHz
ps
ps
Notes to Table1–22:
(1)Use a memory block clock that comes through global clock routing from an on-chip PLL set to 50% output duty cycle to achieve the maximum memory block
performance. Use Quartus II software to report timing for this and other memory block clocking schemes.
(2)The F
max
shown for M9K degrades 2 % when you use Error Detection CRC feature on the device, except for C4L speed grade with V
CCL
=0.9 V. For C4L speed
grade with V
CCL
=0.9V, there is no degradation in Fmax when Error Detection CRC feature is used.
(3)The F
max
shown for M144K degrades 10 MHz when you use byte-enable support on M144K.
(4)The F
max
is applicable when the COMPTABILITY option is turned ON.
(5)The F
max
is applicable when the COMPTABILITY option is turned OFF. This option is turned ON by default in QuartusII software.
(6)The F
max
for EP3SL200, EP3SE260, and EP3SL340 at C2 Speed Grade is 7% slower than the C2 values shown in the table.
Configuration and JTAG Specifications
Table1–23 lists the StratixIII Configuration Mode Specifications.
Table1–xIII Configuration Mode Specifications (Note1)
Programming Mode
Passive Serial
Fast Passive Parallel (2)
Fast Active Serial (3)
Notes to Table1–23:
(1)DCLK F
max
is restricted when Remote Update is enabled. For more information, refer to Remote Update Circuitry
(ALTREMOTE_UPDATE) Megafunction User Guide.
(2)Data rate must be 4× slower than the clock when decompression and/or encryption are used.
(3)For more information about the minimum and typical DCLK F
max
value in Fast Active Serial configuration, refer to
the Serial Configuration Devices Data Sheet chapter in Cyclone Device Handbook.
DCLK F
max
100
100
40
Unit
MHz
MHz
MHz
Table1–24 shows the JTAG timing parameters and values for StratixIII devices. Refer
to figure for “HIGH-SPEED I/O Block” in “Glossary” for JTAG timing requirements.
Table1–xIII JTAG Timing Parameters and Values
Symbol
t
JCP
t
JCH
t
JCL
t
JPSU
(TDI)
t
JPSU
(TMS)
t
JPH
t
JPCO
t
JPZX
t
JPXZ
Parameter
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time for TDI
JTAG port setup time for TMS
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Min
30
14
14
1
3
5
—
—
—
Max
—
—
—
—
—
—
11
14
14
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
Switching Characteristics
Periphery Performance
This section describes periphery performance, including high-speed I/O and external
memory interface.
I/O performance supports several system interfacing, such as the LVDS high-speed
I/O interface, external memory interface, and the PCI/PCI-X bus interface. For
example, StratixIII devices I/O configured with voltage referenced I/O standards can
achieve up to the stated system interfacing speed as indicated in “External Memory
Interface Specifications” on page1–25. General-purpose I/O standards such as 3.3,
3.0, 2.5, 1.8, or 1.5 LVTTL/LVCMOS are capable of typical 167 MHz and 1.2LVCMOS
at 100MHz interfacing frequency with 10pF load.
1Actual achievable frequency depends on design- and system-specific factors. You
should perform HSPICE/IBIS simulations based on your specific design and system
setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specifications
Refer to the “Glossary” for definitions of high-speed timing specifications.
Table1–25 shows the high-speed I/O timing for StratixIII devices.
Table1– & Emulated LVDS Specifications(Note1), (2)(Part 1 of 3)
Symbol
f
HSCLK_in
(input clock
frequency)
f
HSCLK_out
(output clock
frequency)
Transmitter
M
a
x
M
a
x
M
a
x
Clock boost
factor W = 1 to 40
(3)
—800—717—717—717
M
a
x
M
i
n
M
i
n
M
i
n
M
i
n
T
y
p
T
y
p
T
y
p
T
y
p
Conditions
MHz
—5—800 (7)5—717 (7)5—717 (7)5—717 (7)MHz
SERDES factor
J = 3 to 10 (8)
f
HSDR
(data rate)
(4)
(4)
—
—
1600
(4)
(4)
(4)
—
—
1250
(4)
(4)
(4)
—
—
1250
(4)
(4)
(4)
—
—
1250
(4)
Mbps
Mbps
SERDES factor
J = 2, Uses
DDR Register
SERDES factor
J = 1, Uses SDR
Register
(4)
(4)
(4)
—
—
—
(4)
1100
311
(4)
(4)
(4)
—
—
—
(4)
1100
200
(4)
(4)
(4)
—
—
—
(4)
800
200
(4)
(4)
(4)
—
—
—
(4)
800
200
Mbps
Mbps
Mbps
LVDS_E_3R -
f
HSDR
(data rate)
LVDS_E_1R -
f
HSDR
(data rate)
SERDES factor
J = 4 to 10
SERDES factor
J = 4 to 10
Stratix III Device Handbook, Volume 2
U
n
i
t
C2C3, I3C4, I4C4L, I4L
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
I/O Timing
Table1– Timing Measurement Methodology for Output Pins(Part 3 of 3)
I/O Standard
R
S
MINI-LVDS_E_1R
MINI-LVDS_E_3R
RSDS_E_1R
RSDS_E_3R
Notes to Table1–39:
(1)Hyper transport is not supported by StratixIII.
(2)LVPECL outputs are not supported by StratixIII.
(3)Quartus timing conditions can be changed using the Advanced I/O Timing feature.
(4)V
CC
is nominally 1.1 V less 50 mV (1.05 V).
(5)Terminated I/O standards require an additional 30 mV IR drop on V
CC
(1.02 V).
(6)Terminated I/O standards required an additional 50 mV IR drop on V
CCIO
and V
CCPD
.
Loading and Terminations
R
D
100
100
100
100
R
T
—
—
—
—
R
P
120
170
120
170
V
CCIO
2.325
2.325
2.325
2.325
V
CCPD
2.325
2.325
2.325
2.325
V
CC
1.02
1.02
1.02
1.02
V
TT
—
—
—
—
C
L
(pF)
0
0
0
0
Measurement
Point
V
MEAS
(v)
1.1625
1.1625
1.1625
1.1625
—
120
—
120
I/O Default Capacitive Loading
See Table1–40 for default capacitive loading of different I/O standards.
Table1–t Loading of Different I/O Standards for StratixIII (Part 1 of 2)
I/O Standard
3.3-V LVTTL
3.3-V LVCMOS
3.0-V LVTTL
3.0-V LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVTTL/LVCMOS
3.0-V PCI
3.0-V PCI-X
SSTL-2 CLASSI
SSTL-2 CLASSII
SSTL-18 CLASSI
SSTL-18 CLASSII
1.5-V HSTL CLASSI
1.5-V HSTL CLASSII
1.8-V HSTL CLASSI
1.8-V HSTL CLASSII
1.2-V HSTL
Differential SSTL-2 CLASSI
Differential SSTL-2 CLASSII
Differential SSTL-18 CLASSI
Capacitive
Load
0
0
0
0
0
0
0
10
10
0
0
0
0
0
0
0
0
0
0
0
0
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Stratix III Device Handbook, Volume 2
Chapter 1:StratixIII Device Data Sheet: DC and Switching Characteristics
I/O Timing
Stratix III Device Handbook, Volume 2