2024年3月16日发(作者：出博赡)

Chapter 5:Tile Features

Examples

Configuring the Shared PMA PLL for XAUI Operation

The three methods to configure the shared PMA PLL for XAUI are described below:

the RocketIO GTX Transceiver Wizard.

The wizard includes a protocol file for XAUI that allows it to automatically configure

the GTX_DUAL primitive for use in a XAUI design.

the settings from Table5-3.

Table5-3 includes the settings for common configurations of popular protocols. XAUI

settings are included in Table5-3, along with other protocols that use 8B/10B

encoding.

Equation5-1 as described in the following steps:

a.

b.

Determine the required line rates.

For XAUI operation, both TX and RX use a line rate of 3.125Gb/s.

Determine the internal datapath width.

Because XAUI is an 8B/10B-encoded standard, an internal datapath width of

20bits is required. See “Configurable 8B/10B Encoder,” page 129 and

“Configurable 8B/10B Decoder,” page 200 for more information about encoding

and internal datapath width requirements.

ine the desired reference clock rate.

This example uses a reference clock running at 156.25MHz, a common rate for

XAUI.

ate the required PLL clock rate.

Because the SIPO block utilizes a Double Date Rate (DDR) architecture where both

edges of the clock are used to deserialize data, it must be fed a clock from the PLL

that is one-half the magnitude of the desired line rate. In this XAUI example, the

calculation is 3.125Gb/s line rate divided by 2 equaling 1.5625GHz. Because this

RX rate of 1.5625GHz is within the nominal PLL operation range, the external

divider (PLL_RXDIVSEL_OUT) must be one to allow the PLL to run at

1.5625GHz. The PLL clock rate is thus 1.5625x1 = 1.5625GHz.

ate the required DIV value.

Because the internal datapath width must be 20 bits and INTDATAWIDTH is

High, DIV=5.

ate the required PLL divider ratio.

Using the values f

CLKIN

, DIV, and f

PLL_CLOCK

determined above, rearrange

Equation5-1 to calculate the divider ratio as shown in Equation5-2. The result is a

ratio of two.

f

PLL_Clock

1.5625 GHz

PLL_DIVSEL_FB

-

=

------------------------------------------

=2

----------------------------------------------------

=

-----------------------------------

f

CLKIN

×DIV156.25 MHz×5

PLL_DIVSEL_REF

the PLL divider values.

Select the smallest divider values that result in the required PLL divider ratio. In

this case, using PLL_DIVSEL_FB

=2 and PLL_DIVSEL_REF=1 results in a ratio

of 2.

Equation5-2

RocketIO GTX Transceiver User Guide

UG198 (v3.0) October 30, 2009

Shared PMA PLL

Configuring the Shared PMA PLL for OC-48 Operation

This example shows how to set the shared PMA PLL divider settings for OC-48 using

Equation5-1. The RocketIO GTX Transceiver Wizard and Table5-3 are simpler

alternatives. This example is provided only to illustrate the process with Equation5-1.

Use Equation5-1 as described in the following steps:

1.

2.

Determine the required line rates.

For OC-48, both TX and RX use a line rate of 2.488Gb/s.

Determine the internal datapath width.

Because OC-48 uses no encoding and a datapath that is a multiple of 8bits, an internal

datapath width of 16 bits is required.

3.

4.

Determine the desired reference clock rate.

This example uses a reference clock running at 155.5MHz.

Calculate the required PLL clock rate.

The SIPO block utilizes a DDR architecture where both edges of the clock are used to

deserialize data. The SIPO block must be fed a clock from the PLL that is one-half the

magnitude of the desired line rate. In this OC-48 example, a 2.488Gb/s line rate is

divided by 2, or 1.244GHz. Because this RX rate of 1.244GHz is below the nominal

PLL operation range, the external divider (PLL_RXDIVSEL_OUT) must be two to

allow the PLL to run two times as fast (2.488GHz). The PLL clock rate is thus

1.244x2= 2.488GHz.

ate the required DIV value.

Because the internal datapath width must be 16 bits and INTDATAWIDTH is Low,

DIV=4.

ate the required PLL divider ratio.

Using the values f

CLKIN

, DIV, and f

PLL_CLOCK

determined above, rearrange

Equation5-1 to calculate the divider ratio as shown in Equation5-3. The result is a

ratio of 2.

f

PLL_Clock

2.488GHz

PLL_DIVSEL_FB

-

=

---------------------------------------

=2

----------------------------------------------------

=

-----------------------------------

f

CLKIN

×DIV155.5 MHz×4

PLL_DIVSEL_REF

the PLL divider values.

Select the smallest divider values that result in the required PLL divider ratio. In this

case, using PLL_DIVSEL_FB=2 and PLL_DIVSEL_REF=1 results in a ratio of 2.

Equation

5-3

RocketIO GTX Transceiver User Guide

UG198 (v3.0) October 30, 2009

2024年3月16日发(作者：出博赡)

Chapter 5:Tile Features

Examples

Configuring the Shared PMA PLL for XAUI Operation

The three methods to configure the shared PMA PLL for XAUI are described below:

the RocketIO GTX Transceiver Wizard.

The wizard includes a protocol file for XAUI that allows it to automatically configure

the GTX_DUAL primitive for use in a XAUI design.

the settings from Table5-3.

Table5-3 includes the settings for common configurations of popular protocols. XAUI

settings are included in Table5-3, along with other protocols that use 8B/10B

encoding.

Equation5-1 as described in the following steps:

a.

b.

Determine the required line rates.

For XAUI operation, both TX and RX use a line rate of 3.125Gb/s.

Determine the internal datapath width.

Because XAUI is an 8B/10B-encoded standard, an internal datapath width of

20bits is required. See “Configurable 8B/10B Encoder,” page 129 and

“Configurable 8B/10B Decoder,” page 200 for more information about encoding

and internal datapath width requirements.

ine the desired reference clock rate.

This example uses a reference clock running at 156.25MHz, a common rate for

XAUI.

ate the required PLL clock rate.

Because the SIPO block utilizes a Double Date Rate (DDR) architecture where both

edges of the clock are used to deserialize data, it must be fed a clock from the PLL

that is one-half the magnitude of the desired line rate. In this XAUI example, the

calculation is 3.125Gb/s line rate divided by 2 equaling 1.5625GHz. Because this

RX rate of 1.5625GHz is within the nominal PLL operation range, the external

divider (PLL_RXDIVSEL_OUT) must be one to allow the PLL to run at

1.5625GHz. The PLL clock rate is thus 1.5625x1 = 1.5625GHz.

ate the required DIV value.

Because the internal datapath width must be 20 bits and INTDATAWIDTH is

High, DIV=5.

ate the required PLL divider ratio.

Using the values f

CLKIN

, DIV, and f

PLL_CLOCK

determined above, rearrange

Equation5-1 to calculate the divider ratio as shown in Equation5-2. The result is a

ratio of two.

f

PLL_Clock

1.5625 GHz

PLL_DIVSEL_FB

-

=

------------------------------------------

=2

----------------------------------------------------

=

-----------------------------------

f

CLKIN

×DIV156.25 MHz×5

PLL_DIVSEL_REF

the PLL divider values.

Select the smallest divider values that result in the required PLL divider ratio. In

this case, using PLL_DIVSEL_FB

=2 and PLL_DIVSEL_REF=1 results in a ratio

of 2.

Equation5-2

RocketIO GTX Transceiver User Guide

UG198 (v3.0) October 30, 2009

Shared PMA PLL

Configuring the Shared PMA PLL for OC-48 Operation

This example shows how to set the shared PMA PLL divider settings for OC-48 using

Equation5-1. The RocketIO GTX Transceiver Wizard and Table5-3 are simpler

alternatives. This example is provided only to illustrate the process with Equation5-1.

Use Equation5-1 as described in the following steps:

1.

2.

Determine the required line rates.

For OC-48, both TX and RX use a line rate of 2.488Gb/s.

Determine the internal datapath width.

Because OC-48 uses no encoding and a datapath that is a multiple of 8bits, an internal

datapath width of 16 bits is required.

3.

4.

Determine the desired reference clock rate.

This example uses a reference clock running at 155.5MHz.

Calculate the required PLL clock rate.

The SIPO block utilizes a DDR architecture where both edges of the clock are used to

deserialize data. The SIPO block must be fed a clock from the PLL that is one-half the

magnitude of the desired line rate. In this OC-48 example, a 2.488Gb/s line rate is

divided by 2, or 1.244GHz. Because this RX rate of 1.244GHz is below the nominal

PLL operation range, the external divider (PLL_RXDIVSEL_OUT) must be two to

allow the PLL to run two times as fast (2.488GHz). The PLL clock rate is thus

1.244x2= 2.488GHz.

ate the required DIV value.

Because the internal datapath width must be 16 bits and INTDATAWIDTH is Low,

DIV=4.

ate the required PLL divider ratio.

Using the values f

CLKIN

, DIV, and f

PLL_CLOCK

determined above, rearrange

Equation5-1 to calculate the divider ratio as shown in Equation5-3. The result is a

ratio of 2.

f

PLL_Clock

2.488GHz

PLL_DIVSEL_FB

-

=

---------------------------------------

=2

----------------------------------------------------

=

-----------------------------------

f

CLKIN

×DIV155.5 MHz×4

PLL_DIVSEL_REF

the PLL divider values.

Select the smallest divider values that result in the required PLL divider ratio. In this

case, using PLL_DIVSEL_FB=2 and PLL_DIVSEL_REF=1 results in a ratio of 2.

Equation

5-3

RocketIO GTX Transceiver User Guide

UG198 (v3.0) October 30, 2009