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2024年3月22日发(作者：闾丘丽泽)

Boundary-Scan for Virtex-5 Devices Using IEEE Standard 1149.1

The Virtex-5 family is fully compliant with the IEEE Standard 1149.1 Test Access Port and

Boundary-Scan Architecture. The architecture includes all mandatory elements defined in

the IEEE 1149.1 Standard. These elements include the Test Access Port (TAP), the TAP

controller, the Instruction register, the instruction decoder, the Boundary-Scan register, and

the BYPASS register. The Virtex-5 family also supports a 32-bit Identification register and a

Configuration register in full compliance with the standard. Outlined in the following

sections are the details of the JTAG architecture for Virtex-5 devices.

If Boundary-Scan is used as part of the product verification in the LXT or SXT, the analog

supply voltage pin MGTAVCC of all GTP_DUAL tiles must be powered. The analog

supply voltage pin MGTAVCC of all unused GTP_DUAL tiles must be connected to the

same supply that supplies V

CCINT

, which is the power supply pin for the internal core

logic.

Test Access Port (TAP)

The Virtex-5 TAP contains four mandatory dedicated pins as specified by the protocol

given in Table3-1 and illustrated in Figure3-1, a typical JTAG architecture. Three input

pins and one output pin control the 1149.1 Boundary-Scan TAP controller. Optional control

pins, such as TRST (Test Reset) and enable pins might be found on devices from other

manufacturers. It is important to be aware of these optional signals when interfacing Xilinx

devices with parts from different vendors because they might need to be driven.

The TAP controller is a state machine (16 states) shown in Figure3-2. The four mandatory

TAP pins are outlined in Table3-1.

Virtex-5 FPGA Configuration Guide

UG191 (v3.13) July 28, 2020

Chapter 3:Boundary-Scan and JTAG Configuration

Capture-DR:

In this controller state, the data is parallel-loaded into the data registers selected by the

current instruction on the rising edge of TCK.

Shift-Dr, Exit1-DR, Pause-DR, Exit2-DR, and Update-DR:

These controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR, and Update-

IR states in the Instruction path.

TEST-LOGIC-RESET

RUN-TEST/IDLE

SELECT-DR-SCAN

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

EXIT2-DR

UPDATE-DR

SELECT-IR-SCAN

CAPTURE-IR

SHIFT-IR

EXIT1-IR

PAUSE-IR

EXIT2-IR

UPDATE-IR

NOTE: The value shown adjacent to each state transition in this figure

represents the signal present at TMS at the time of a rising edge at TCK.

UG191_c3_02_050406

Figure 3-2:Boundary-Scan TAP Controller

Virtex-5 devices support the mandatory IEEE 1149.1 commands, as well as several Xilinx

vendor-specific commands. The EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS,

IDCODE, USERCODE, and HIGHZ instructions are all included. The TAP also supports

internal user-defined registers (USER1, USER2, USER3, and USER4) and

configuration/readback of the device.

The Virtex-5 Boundary-Scan operations are independent of mode selection. The

Boundary-Scan mode in Virtex-5 devices overrides other mode selections. For this reason,

Boundary-Scan instructions using the Boundary-Scan register (SAMPLE/PRELOAD,

INTEST, and EXTEST) must not be performed during configuration. All instructions

except the user-defined instructions are available before a Virtex-5 device is configured.

After configuration, all instructions are available.

JSTART and JSHUTDOWN are instructions specific to the Virtex-5 architecture and

configuration flow. In Virtex-5 devices, the TAP controller is not reset by the PROGRAM_B

pin and can only be reset by bringing the controller to the TLR state. The TAP controller is

reset on power up.

For details on the standard Boundary-Scan instructions EXTEST, INTEST, and BYPASS,

refer to the IEEE Standard.