2024年3月22日发(作者：锁雅韵)
元器件交易网
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14553B
3-Digit BCD Counter
The MC14553B 3–digit BCD counter consists of 3 negative edge triggered
BCD counters that are cascaded synchronously. A quad latch at the output
of each counter permits storage of any given count. The information is then
time division multiplexed, providing one BCD number or digit at a time. Digit
select outputs provide display control. All outputs are TTL compatible.
An on–chip oscillator provides the low–frequency scanning clock which
drives the multiplexer output selector.
This device is used in instrumentation counters, clock displays, digital
panel meters, and as a building block for general logic applications.
•
•
•
•
•
•
•
TTL Compatible Outputs
On–Chip Oscillator
Cascadable
Clock Disable Input
Pulse Shaping Permits Very Slow Rise Times on Input Clock
Output Latches
Master Reset
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
T
A
= – 55° to 125°C for all packages.
MAXIMUM RATINGS*
(Voltages Referenced to V
SS
)
Symbol
V
DD
V
in
, V
out
I
in
I
out
P
D
T
stg
T
L
Parameter
DC Supply Voltage
Input or Output Voltage (DC or Transient)
Input Current (DC or Transient), per Pin
Output Current (DC or Transient), per Pin
Power Dissipation, per Package†
Storage Temperature
Lead Temperature (8–Second Soldering)
Value
– 0.5 to + 18.0
– 0.5 to V
DD
+ 0.5
± 10
+ 20
500
– 65 to + 150
260
Unit
V
V
mA
mA
mW
_C
_C
CIA
12
10
11
13
CLOCK
LE
DIS
MR
CIB
Q0
Q1
Q2
Q3
O.F.
DS1
DS2
DS3
V
DD
= PIN 16
V
SS
= PIN 8
9
7
6
5
14
2
1
15
BLOCK DIAGRAM
43
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
TRUTH TABLE
Inputs
Master
Reset
0
0
0
0
0
0
0
0
1
X = Don’t Care
ClockDisable
0
0
1
LE
0
0
X
0
0
X
1
0
Outputs
No Change
Advance
No Change
Advance
No Change
No Change
Latched
Latched
Q0 = Q1 = Q2 = Q3 = 0
X
1
1
0
X
X
X
X
X
X
X
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, V
in
and V
out
should be constrained
to the range V
SS
v (V
in
or V
out
) v V
DD
.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either V
SS
or V
DD
). Unused outputs must be left open.
REV 3
1/94
©
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
MC14553B
1
元器件交易网
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
Characteristic
Output Voltage
V
in
= V
DD
or 0
“0” Level
Symbol
V
OL
V
DD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
I
OL
5.0
10
15
5.0
10
15
I
in
C
in
I
DD
15
—
5.0
10
15
5.0
10
15
Min
—
—
—
4.95
9.95
14.95
—
—
—
3.5
7.0
11
– 0.25
– 0.62
– 1.8
– 0.64
– 1.6
– 4.2
0.5
1.1
1.8
3.0
6.0
18
—
—
—
—
—
– 55_C
Max
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
±0.1
—
5.0
10
20
Min
—
—
—
4.95
9.95
14.95
—
—
—
3.5
7.0
11
– 0.2
– 0.5
– 1.5
– 0.51
– 1.3
– 3.4
0.4
0.9
1.5
2.5
5.0
15
—
—
—
—
—
25_C
Typ #
0
0
0
5.0
10
15
2.25
4.50
6.75
2.75
5.50
8.25
– 0.36
– 0.9
– 3.5
– 0.88
– 2.25
– 8.8
0.88
2.25
8.8
4.0
8.0
20
±0.00001
5.0
0.010
0.020
0.030
Max
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
±0.1
7.5
5.0
10
20
125_C
Min
—
—
—
4.95
9.95
14.95
—
—
—
3.5
7.0
11
0.14
0.35
1.1
– 0.36
– 0.9
– 2.4
0.28
0.65
1.20
1.6
3.5
10
—
—
—
—
—
Max
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
Vdc
—
—
—
mAdc
—
—
—
—
—
—
—
—
—
—
—
—
±1.0
—
150
300
600
mAdc
Unit
Vdc
“1” Level
V
in
= 0 or V
DD
Input Voltage“0” Level
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
“1” Level
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
Output Drive Current
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc)
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
(V
OL
= 0.4 Vdc)
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance
(V
in
= 0)
Quiescent Current
(Per Package)
MR = V
DD
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
Source —
Pin 3
Source —
Other
Outputs
Sink —
Pin 3
Sink — Other
Outputs
V
OH
Vdc
V
IL
Vdc
V
IH
I
OH
mAdc
mAdc
µAdc
pF
µAdc
I
T
I
T
= (0.35 µA/kHz) f + I
DD
I
T
= (0.85 µA/kHz) f + I
DD
I
T
= (1.50 µA/kHz) f + I
DD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
– 50) Vfk
where: I
T
is in µA (per package), C
L
in pF, V = (V
DD
– V
SS
) in volts, f in kHz is input frequency, and k = 0.004.
MC14553B
2
MOTOROLA CMOS LOGIC DATA
2024年3月22日发(作者：锁雅韵)
元器件交易网
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14553B
3-Digit BCD Counter
The MC14553B 3–digit BCD counter consists of 3 negative edge triggered
BCD counters that are cascaded synchronously. A quad latch at the output
of each counter permits storage of any given count. The information is then
time division multiplexed, providing one BCD number or digit at a time. Digit
select outputs provide display control. All outputs are TTL compatible.
An on–chip oscillator provides the low–frequency scanning clock which
drives the multiplexer output selector.
This device is used in instrumentation counters, clock displays, digital
panel meters, and as a building block for general logic applications.
•
•
•
•
•
•
•
TTL Compatible Outputs
On–Chip Oscillator
Cascadable
Clock Disable Input
Pulse Shaping Permits Very Slow Rise Times on Input Clock
Output Latches
Master Reset
L SUFFIX
CERAMIC
CASE 620
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
Plastic
Ceramic
SOIC
T
A
= – 55° to 125°C for all packages.
MAXIMUM RATINGS*
(Voltages Referenced to V
SS
)
Symbol
V
DD
V
in
, V
out
I
in
I
out
P
D
T
stg
T
L
Parameter
DC Supply Voltage
Input or Output Voltage (DC or Transient)
Input Current (DC or Transient), per Pin
Output Current (DC or Transient), per Pin
Power Dissipation, per Package†
Storage Temperature
Lead Temperature (8–Second Soldering)
Value
– 0.5 to + 18.0
– 0.5 to V
DD
+ 0.5
± 10
+ 20
500
– 65 to + 150
260
Unit
V
V
mA
mA
mW
_C
_C
CIA
12
10
11
13
CLOCK
LE
DIS
MR
CIB
Q0
Q1
Q2
Q3
O.F.
DS1
DS2
DS3
V
DD
= PIN 16
V
SS
= PIN 8
9
7
6
5
14
2
1
15
BLOCK DIAGRAM
43
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C
TRUTH TABLE
Inputs
Master
Reset
0
0
0
0
0
0
0
0
1
X = Don’t Care
ClockDisable
0
0
1
LE
0
0
X
0
0
X
1
0
Outputs
No Change
Advance
No Change
Advance
No Change
No Change
Latched
Latched
Q0 = Q1 = Q2 = Q3 = 0
X
1
1
0
X
X
X
X
X
X
X
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, V
in
and V
out
should be constrained
to the range V
SS
v (V
in
or V
out
) v V
DD
.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either V
SS
or V
DD
). Unused outputs must be left open.
REV 3
1/94
©
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
MC14553B
1
元器件交易网
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
Characteristic
Output Voltage
V
in
= V
DD
or 0
“0” Level
Symbol
V
OL
V
DD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
I
OL
5.0
10
15
5.0
10
15
I
in
C
in
I
DD
15
—
5.0
10
15
5.0
10
15
Min
—
—
—
4.95
9.95
14.95
—
—
—
3.5
7.0
11
– 0.25
– 0.62
– 1.8
– 0.64
– 1.6
– 4.2
0.5
1.1
1.8
3.0
6.0
18
—
—
—
—
—
– 55_C
Max
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
±0.1
—
5.0
10
20
Min
—
—
—
4.95
9.95
14.95
—
—
—
3.5
7.0
11
– 0.2
– 0.5
– 1.5
– 0.51
– 1.3
– 3.4
0.4
0.9
1.5
2.5
5.0
15
—
—
—
—
—
25_C
Typ #
0
0
0
5.0
10
15
2.25
4.50
6.75
2.75
5.50
8.25
– 0.36
– 0.9
– 3.5
– 0.88
– 2.25
– 8.8
0.88
2.25
8.8
4.0
8.0
20
±0.00001
5.0
0.010
0.020
0.030
Max
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
±0.1
7.5
5.0
10
20
125_C
Min
—
—
—
4.95
9.95
14.95
—
—
—
3.5
7.0
11
0.14
0.35
1.1
– 0.36
– 0.9
– 2.4
0.28
0.65
1.20
1.6
3.5
10
—
—
—
—
—
Max
0.05
0.05
0.05
—
—
—
1.5
3.0
4.0
Vdc
—
—
—
mAdc
—
—
—
—
—
—
—
—
—
—
—
—
±1.0
—
150
300
600
mAdc
Unit
Vdc
“1” Level
V
in
= 0 or V
DD
Input Voltage“0” Level
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
“1” Level
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
Output Drive Current
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc)
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
(V
OL
= 0.4 Vdc)
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance
(V
in
= 0)
Quiescent Current
(Per Package)
MR = V
DD
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
Source —
Pin 3
Source —
Other
Outputs
Sink —
Pin 3
Sink — Other
Outputs
V
OH
Vdc
V
IL
Vdc
V
IH
I
OH
mAdc
mAdc
µAdc
pF
µAdc
I
T
I
T
= (0.35 µA/kHz) f + I
DD
I
T
= (0.85 µA/kHz) f + I
DD
I
T
= (1.50 µA/kHz) f + I
DD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
– 50) Vfk
where: I
T
is in µA (per package), C
L
in pF, V = (V
DD
– V
SS
) in volts, f in kHz is input frequency, and k = 0.004.
MC14553B
2
MOTOROLA CMOS LOGIC DATA