2024年3月22日发(作者：蒯飞雪)
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Symbol
Sequential Delays
T
REG
T
REG_MUX
T
REG_M31
Description
Speed Grade
-2I
1.43
1.55
1.15
-1I
1.73
1.87
1.38
-1M
1.73
1.87
1.38
Units
Clock to A–D outputs
Clock to AMUX–DMUX output
Clock to DMUX output via M31 output
ns, Max
ns, Max
ns, Max
Setup and Hold Times Before/After Clock CLK
T
WS
/T
WH
T
CECK
/T
CKCE
T
DS
/T
DH
Clock CLK
T
MPW
Notes:
1.A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
WE input
CE input to CLK
A–D inputs to CLK
0.24
–0.04
0.27
–0.07
0.66
0.09
0.70
0.29
–0.02
0.33
–0.06
0.78
0.11
0.85
0.29
–0.02
0.33
–0.06
0.78
0.11
0.85
ns, Min
ns, Min
ns, Min
Minimum pulse widthns, Min
DS714 (v2.2) January 17, 2011
Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 68:Block RAM and FIFO Switching Characteristics (Cont’d)
Symbol
Maximum Frequency
F
MAX
F
MAX_CASCADE
F
MAX_FIFO
F
MAX_ECC
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
TRACE will report all of these parameters as T
RCKO_DO
.
T
RCKO_DOR
includes T
RCKO_DOW
, T
RCKO_DOPR
, and T
RCKO_DOPW
as well as the B port equivalent timing parameters.
These parameters also apply to synchronous FIFO with DO_REG=0.
T
RCKO_DO
includes T
RCKO_DOP
as well as the B port equivalent timing parameters.
These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG=1.
T
RCKO_FLAGS
includes the following parameters: T
RCKO_AEMPTY
, T
RCKO_AFULL
, T
RCKO_EMPTY
, T
RCKO_FULL
, T
RCKO_RDERR
, T
RCKO_WRERR
.
T
RCKO_POINTERS
includes both T
RCKO_RDCOUNT
and T
RCKO_WRCOUNT
.
The ADDR setup and hold must be met when EN is asserted even though WE is deasserted. Otherwise, block RAM data corruption is possible.
T
RCKO_DI
includes both A and B inputs as well as the parity inputs of A and B.
These parameters also apply to RDEN.
T
RCO_FLAGS
includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
Description
Speed Grade
-2I
500
450
500
375
-1I
450
400
450
325
-1M
450
400
450
325
Units
Block RAM in all modes
Block RAM in cascade configuration
FIFO in all modes
Block RAM and FIFO in ECC configuration
MHz
MHz
MHz
MHz
DSP48E Switching Characteristics
Table 69:DSP48E Switching Characteristics
SymbolDescription
Speed Grade
-2I
0.21
0.23
0.16
0.31
-1I
0.26
0.30
0.20
0.37
-1M
0.26
0.30
0.20
0.50
Units
Setup and Hold Times of Data/Control Pins to the Input Register Clock
TDSPDCK_{AA, BB, ACINA, BCINB}/
TDSPCKD_{AA, BB, ACINA, BCINB}
TDSPDCK_CC/TDSPCKD_CC
{A, B, ACIN, BCIN} input to {A, B} register CLK
C input to Cregister CLK
ns
ns
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_{AM, BM, ACINM, BCINM}/
TDSPCKD_{AM, BM, ACINM, BCINM}
{A, B, ACIN, BCIN} input to Mregister CLK 1.44
0.19
1.71
0.19
1.71
0.19
ns
Setup and Hold Times of Data/Control Pins to the Output Register Clock
TDSPDCK_{AP, BP, ACINP, BCINP}_M/
TDSPCKD_{AP, BP, ACINP, BCINP}_M
TDSPDCK_{AP, BP, ACINP, BCINP}_NM/
TDSPCKD_{AP, BP, ACINP, BCINP}_NM
TDSPDCK_CP/TDSPCKD_CP
TDSPDCK_{PCINP, CRYCINP,
MULTSIGNINP}/
TDSPCKD_{PCINP, CRYCINP,
MULTSIGNINP}
{A, B, ACIN, BCIN} input to Pregister CLK
using multiplier
{A, B, ACIN, BCIN} input to Pregister CLK not
using multiplier
C input to Pregister CLK
{PCIN, CARRYCASCIN, MULTSIGNIN} input
to Pregister CLK
2.74
–0.30
1.54
–0.10
1.42
–0.13
1.17
0.11
3.25
–0.30
1.83
–0.10
1.70
–0.13
1.31
0.11
3.25
–0.30
1.83
–0.10
1.70
–0.13
1.31
0.11
ns
ns
ns
ns
Setup and Hold Times of the CE Pins
{CEA1, CEA2A, CEB1B, CEB2B} input to
TDSPCCK_{CEA1A, CEA2A, CEB1B,
{A,B} register CLK
CEB2B}/
TDSPCKC_{CEA1A, CEA2A, CEB1A, CEB2B}
TDSPCCK_CECC/TDSPCKC_CECC
TDSPCCK_CEMM/TDSPCKC_CEMM
CEC input to Cregister CLK
CEM input to Mregister CLK
0.28
0.25
0.21
0.21
0.29
0.21
0.33
0.31
0.26
0.28
0.36
0.26
0.33
0.31
0.26
0.28
0.36
0.26
ns
ns
ns
DS714 (v2.2) January 17, 2011
Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
DS714 (v2.2) January 17, 2011
Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
PLL Switching Characteristics
Table 74:PLL Specification
Symbol
F
INMAX
F
INMIN
F
INJITTER
F
INDUTY
Description
Maximum Input Clock Frequency
Minimum Input Clock Frequency
Maximum Input Clock Period Jitter
Allowable Input Duty Cycle: 19—49MHz
Allowable Input Duty Cycle: 50—199MHz
Allowable Input Duty Cycle: 200—399MHz
Allowable Input Duty Cycle: 400—499MHz
Allowable Input Duty Cycle: >500MHz
Speed Grade
-2I
710
19
-1I
645
19
25/75
30/70
35/65
40/60
45/55
-1M
645
19
Units
MHz
MHz
%
%
%
%
%
<20% of clock input period or 1ns Max
F
VCOMIN
F
VCOMAX
F
BANDWIDTH
T
STAPHAOFFSET
T
OUTJITTER
T
OUTDUTY
T
LOCKMAX
F
OUTMAX
Minimum PLL VCO Frequency
Maximum PLL VCO Frequency
Low PLL Bandwidth at Typical
(1)
High PLL Bandwidth at Typical
(1)
Static Phase Offset of the PLL Outputs
PLL Output Jitter
(2)
PLL Output Clock Duty Cycle Precision
(3)
PLL Maximum Lock Time
(4)
PLL Maximum Output Frequency for LX30T, LX85, LX110,
LX110T, SX50T, and FX70T(I) devices
PLL Maximum Output Frequency for LX155T, FX70T(M), and
FX100T devices
PLL Maximum Output Frequency for FX130T devices
PLL Maximum Output Frequency for LX220T, LX330T, SX95T,
SX240T, and FX200T devices
400
1200
1
4
120
±200
100
667
600
500
500
3.125
5
500
19
400
1000
1
4
120
Note 1
±200
100
600
550
450
450
3.125
5
450
19
400
1000
1
4
120
±200
100
N/A
550
N/A
N/A
3.125
5
450
19
MHz
MHz
MHz
MHz
ps
ps
µs
MHz
MHz
MHz
MHz
MHz
ns
MHz
MHz
F
OUTMIN
T
EXTFDVAR
RST
MINPULSE
F
PFDMAX
F
PFDMIN
T
FBDELAY
Notes:
1.
2.
3.
4.
5.
PLL Minimum Output Frequency
(5)
External Clock Feedback Variation
Minimum Reset Pulse Width
Maximum Frequency at the Phase Frequency Detector
Minimum Frequency at the Phase Frequency Detector
Maximum Delay in the Feedback Path
<20% of clock input period or 1ns Max
3ns Max or one CLKIN cycle
The PLL does not filter typical spread spectrum input clocks because they are usually far below the bandwidth filter frequencies.
Values for this parameter are available in the Architecture Wizard.
Includes global clock buffer.
The LOCK signal must be sampled after T
LOCKMAX
. The LOCK signal is invalid after configuration or reset until the T
LOCKMAX
time has
expired.
Calculated as F
VCO
/128 assuming output duty cycle is 50%.
DS714 (v2.2) January 17, 2011
Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
DS714 (v2.2) January 17, 2011
Product Specification
2024年3月22日发(作者：蒯飞雪)
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Symbol
Sequential Delays
T
REG
T
REG_MUX
T
REG_M31
Description
Speed Grade
-2I
1.43
1.55
1.15
-1I
1.73
1.87
1.38
-1M
1.73
1.87
1.38
Units
Clock to A–D outputs
Clock to AMUX–DMUX output
Clock to DMUX output via M31 output
ns, Max
ns, Max
ns, Max
Setup and Hold Times Before/After Clock CLK
T
WS
/T
WH
T
CECK
/T
CKCE
T
DS
/T
DH
Clock CLK
T
MPW
Notes:
1.A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
WE input
CE input to CLK
A–D inputs to CLK
0.24
–0.04
0.27
–0.07
0.66
0.09
0.70
0.29
–0.02
0.33
–0.06
0.78
0.11
0.85
0.29
–0.02
0.33
–0.06
0.78
0.11
0.85
ns, Min
ns, Min
ns, Min
Minimum pulse widthns, Min
DS714 (v2.2) January 17, 2011
Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 68:Block RAM and FIFO Switching Characteristics (Cont’d)
Symbol
Maximum Frequency
F
MAX
F
MAX_CASCADE
F
MAX_FIFO
F
MAX_ECC
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
TRACE will report all of these parameters as T
RCKO_DO
.
T
RCKO_DOR
includes T
RCKO_DOW
, T
RCKO_DOPR
, and T
RCKO_DOPW
as well as the B port equivalent timing parameters.
These parameters also apply to synchronous FIFO with DO_REG=0.
T
RCKO_DO
includes T
RCKO_DOP
as well as the B port equivalent timing parameters.
These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG=1.
T
RCKO_FLAGS
includes the following parameters: T
RCKO_AEMPTY
, T
RCKO_AFULL
, T
RCKO_EMPTY
, T
RCKO_FULL
, T
RCKO_RDERR
, T
RCKO_WRERR
.
T
RCKO_POINTERS
includes both T
RCKO_RDCOUNT
and T
RCKO_WRCOUNT
.
The ADDR setup and hold must be met when EN is asserted even though WE is deasserted. Otherwise, block RAM data corruption is possible.
T
RCKO_DI
includes both A and B inputs as well as the parity inputs of A and B.
These parameters also apply to RDEN.
T
RCO_FLAGS
includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
Description
Speed Grade
-2I
500
450
500
375
-1I
450
400
450
325
-1M
450
400
450
325
Units
Block RAM in all modes
Block RAM in cascade configuration
FIFO in all modes
Block RAM and FIFO in ECC configuration
MHz
MHz
MHz
MHz
DSP48E Switching Characteristics
Table 69:DSP48E Switching Characteristics
SymbolDescription
Speed Grade
-2I
0.21
0.23
0.16
0.31
-1I
0.26
0.30
0.20
0.37
-1M
0.26
0.30
0.20
0.50
Units
Setup and Hold Times of Data/Control Pins to the Input Register Clock
TDSPDCK_{AA, BB, ACINA, BCINB}/
TDSPCKD_{AA, BB, ACINA, BCINB}
TDSPDCK_CC/TDSPCKD_CC
{A, B, ACIN, BCIN} input to {A, B} register CLK
C input to Cregister CLK
ns
ns
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_{AM, BM, ACINM, BCINM}/
TDSPCKD_{AM, BM, ACINM, BCINM}
{A, B, ACIN, BCIN} input to Mregister CLK 1.44
0.19
1.71
0.19
1.71
0.19
ns
Setup and Hold Times of Data/Control Pins to the Output Register Clock
TDSPDCK_{AP, BP, ACINP, BCINP}_M/
TDSPCKD_{AP, BP, ACINP, BCINP}_M
TDSPDCK_{AP, BP, ACINP, BCINP}_NM/
TDSPCKD_{AP, BP, ACINP, BCINP}_NM
TDSPDCK_CP/TDSPCKD_CP
TDSPDCK_{PCINP, CRYCINP,
MULTSIGNINP}/
TDSPCKD_{PCINP, CRYCINP,
MULTSIGNINP}
{A, B, ACIN, BCIN} input to Pregister CLK
using multiplier
{A, B, ACIN, BCIN} input to Pregister CLK not
using multiplier
C input to Pregister CLK
{PCIN, CARRYCASCIN, MULTSIGNIN} input
to Pregister CLK
2.74
–0.30
1.54
–0.10
1.42
–0.13
1.17
0.11
3.25
–0.30
1.83
–0.10
1.70
–0.13
1.31
0.11
3.25
–0.30
1.83
–0.10
1.70
–0.13
1.31
0.11
ns
ns
ns
ns
Setup and Hold Times of the CE Pins
{CEA1, CEA2A, CEB1B, CEB2B} input to
TDSPCCK_{CEA1A, CEA2A, CEB1B,
{A,B} register CLK
CEB2B}/
TDSPCKC_{CEA1A, CEA2A, CEB1A, CEB2B}
TDSPCCK_CECC/TDSPCKC_CECC
TDSPCCK_CEMM/TDSPCKC_CEMM
CEC input to Cregister CLK
CEM input to Mregister CLK
0.28
0.25
0.21
0.21
0.29
0.21
0.33
0.31
0.26
0.28
0.36
0.26
0.33
0.31
0.26
0.28
0.36
0.26
ns
ns
ns
DS714 (v2.2) January 17, 2011
Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
DS714 (v2.2) January 17, 2011
Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
PLL Switching Characteristics
Table 74:PLL Specification
Symbol
F
INMAX
F
INMIN
F
INJITTER
F
INDUTY
Description
Maximum Input Clock Frequency
Minimum Input Clock Frequency
Maximum Input Clock Period Jitter
Allowable Input Duty Cycle: 19—49MHz
Allowable Input Duty Cycle: 50—199MHz
Allowable Input Duty Cycle: 200—399MHz
Allowable Input Duty Cycle: 400—499MHz
Allowable Input Duty Cycle: >500MHz
Speed Grade
-2I
710
19
-1I
645
19
25/75
30/70
35/65
40/60
45/55
-1M
645
19
Units
MHz
MHz
%
%
%
%
%
<20% of clock input period or 1ns Max
F
VCOMIN
F
VCOMAX
F
BANDWIDTH
T
STAPHAOFFSET
T
OUTJITTER
T
OUTDUTY
T
LOCKMAX
F
OUTMAX
Minimum PLL VCO Frequency
Maximum PLL VCO Frequency
Low PLL Bandwidth at Typical
(1)
High PLL Bandwidth at Typical
(1)
Static Phase Offset of the PLL Outputs
PLL Output Jitter
(2)
PLL Output Clock Duty Cycle Precision
(3)
PLL Maximum Lock Time
(4)
PLL Maximum Output Frequency for LX30T, LX85, LX110,
LX110T, SX50T, and FX70T(I) devices
PLL Maximum Output Frequency for LX155T, FX70T(M), and
FX100T devices
PLL Maximum Output Frequency for FX130T devices
PLL Maximum Output Frequency for LX220T, LX330T, SX95T,
SX240T, and FX200T devices
400
1200
1
4
120
±200
100
667
600
500
500
3.125
5
500
19
400
1000
1
4
120
Note 1
±200
100
600
550
450
450
3.125
5
450
19
400
1000
1
4
120
±200
100
N/A
550
N/A
N/A
3.125
5
450
19
MHz
MHz
MHz
MHz
ps
ps
µs
MHz
MHz
MHz
MHz
MHz
ns
MHz
MHz
F
OUTMIN
T
EXTFDVAR
RST
MINPULSE
F
PFDMAX
F
PFDMIN
T
FBDELAY
Notes:
1.
2.
3.
4.
5.
PLL Minimum Output Frequency
(5)
External Clock Feedback Variation
Minimum Reset Pulse Width
Maximum Frequency at the Phase Frequency Detector
Minimum Frequency at the Phase Frequency Detector
Maximum Delay in the Feedback Path
<20% of clock input period or 1ns Max
3ns Max or one CLKIN cycle
The PLL does not filter typical spread spectrum input clocks because they are usually far below the bandwidth filter frequencies.
Values for this parameter are available in the Architecture Wizard.
Includes global clock buffer.
The LOCK signal must be sampled after T
LOCKMAX
. The LOCK signal is invalid after configuration or reset until the T
LOCKMAX
time has
expired.
Calculated as F
VCO
/128 assuming output duty cycle is 50%.
DS714 (v2.2) January 17, 2011
Product Specification
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
DS714 (v2.2) January 17, 2011
Product Specification