2024年11月3日发(作者：风材)
元器件交易网
19-1641; Rev 2; 11/04
Low-Cost, Low-Power, 8-Bit DACs with
2-Wire Serial Interface in SOT23
General DescriptionFeatures
The MAX5380/MAX5381/MAX5382 are low-cost, 8-bit
digital-to-analog converters (DACs) in miniature 5-pin
♦8-Bit Accuracy in a Miniature 5-Pin SOT23
SOT23 packages, with a simple 2-wire serial interface
♦Wide +2.7V to +5.5V Supply Range (MAX5382)
that allows communication with multiple devices. The
MAX5380 has an internal +2V reference and operates
♦Low 230µA max Supply Current
from a +2.7V to +3.6V supply. The MAX5381 has an
♦1µA Shutdown Mode
internal +4V reference and operates from a +4.5V to
+5.5V supply. The MAX5382 operates over the full
♦Buffered Output Drives Resistive Loads
+2.7V to +5.5V supply range and has an internal refer-
♦Low-Glitch Power-On Reset to Zero DAC Output
ence equal to 0.9 x V
DD
.
2
The fast-mode I
2
C*-compatible serial interface allows
♦Fast I
C-Compatible Serial Interface
communication at data rates up to 400kbps, minimizing
♦<±5% Full-Scale Error (MAX5382)
board space and reducing interconnect complexity
in many applications. Each device is available with
♦<±1LSB max INL/DNL
one of four factory-preset addresses (see Selector
Guide).
Ordering Information
These DACs also include an output buffer, a low-power
shutdown mode, and a power-on reset that ensures the
PARTTEMP RANGEPIN-PACKAGE
DAC outputs are at zero when power is initially applied.
MAX5380_EUK-T
-40°C to +85°C5 SOT23
In shutdown mode, supply current is reduced to less
MAX5381_EUK-T
-40°C to +85°C5 SOT23
than 1µA and the output is pulled down to GND with a
MAX5382_EUK-T
-40°C to +85°C5 SOT23
10kΩresistor.
Applications
Selector Guide
Automatic Tuning (VCO)
REFERENCETOP
Power-Amplifier Bias Control
PARTADDRESS
(V)MARK
Programmable Threshold Levels
MAX5380LEUK
0x60+2.0ADMN
Automatic Gain Control
MAX5380MEUK0x62+2.0ADMZ
MAX5380NEUK0x64+2.0ADNF
Automatic Offset Adjustment
MAX5380PEUK0x66+2.0ADMP
MAX5381LEUK
0x60+4.0ADMV
Typical Operating Circuit
MAX5381MEUK0x62+4.0ADNB
MAX5381NEUK0x64+4.0ADNH
+2.7V TO +5.5V
MAX5381PEUK0x66+4.0
ADMR
MAX5382LEUK
0x600.9 x V
DD
ADMX
V
DD
MAX5382MEUK0x620.9 x V
DD
ADND
µC
MAX5382NEUK0x640.9 x V
DD
ADNJ
V
DD
MAX5382PEUK0x660.9 x V
DD
ADMT
PX.0/SDA
SDA
PX.1/SCL
SCL
MAX5382
OUT
Pin Configuration
GND
GND
TOP VIEW
OUT 15SCL
Purchase of I
2
C components from Maxim Integrated Products,
GND
2
MAX5380
Inc., or one of its sublicensed Associate Companies, conveys a
MAX5381
MAX5382
license under the Philips I
2
C Patent Rights to use these compo-
V
DD
34SDA
nents in an I
2
C system, provided that the system conforms to the
I
2
C Standard Specification defined by Philips.
SOT23-5
________________________________________________________________Maxim Integrated Products1
For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at
1-888-629-4642, or visit Maxim’s website at .
MAX5380/MAX5381/MAX5382
元器件交易网
Low-Cost, Low-Power, 8-Bit DACs with
2-Wire Serial Interface in SOT23
M
A
X
5
3
8
0
/
M
A
X
5
3
8
1
/
M
A
X
5
3
8
2
ABSOLUTE MAXIMUM RATINGS
V
DD
-0.3V to +6V
OUT, SCL, SDA -0.3V to +6V
Maximum Current into .50mA
Continuous Power Dissipation (T
A
= +70°C)
5-Pin SOT23 (derate 7.1mW/°C above +70°C).............571mW
Operating Temperature Ranges
MAX538_ _-40°C to +85°C
Storage -65°C to +150°C
Maximum .+150°C
Lead Temperature (soldering, 10s).................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= +2.7V to +3.6V (MAX5380), V
DD
= +4.5V to +5.5V (MAX5381), V
DD
= +2.7V to +5.5V (MAX5382); R
L
= 10kΩ; C
L
= 50pF,
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are T
A
= +25°C.)
PARAMETER
STATIC ACCURACY
Resolution
Integral Linearity Error
Differential Linearity Error
Offset Error
Offset Error Supply Rejection
Offset Error Temperature
Coefficient
Full-Scale Error
Full-Scale Error Supply Rejection
Full-Scale Error Temperature
Coefficient
DAC OUTPUT
MAX5380
Internal Reference (Note 5)REF
MAX5381
MAX5382
Output Load Regulation
Output Resistance
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
Output Settling Time
Digital Feedthrough
Digital-Analog Glitch Impulse
Wake-Up Time
Positive and negative
To 1/2 LSB, 50kΩand 50pF load (Note 6)
Code = 0, all digital inputs from 0 to V
DD
Code 127 to 128
From software shutdown
0.4
20
2
40
50
V/µs
µs
nVs
nVs
µs
Code = 255, 0 to 100µA
Code = 0, 0 to 100µA
V
OUT
= 0 to V
DD
, power-down mode
1.8
3.6
0.85 x
V
DD
2
4
0.9x
V
DD
0.5
0.5
10
2.2
4.4
0.95x
V
DD
V
INL
DNL
(Note 1)
Guaranteed monotonic
(Note 2)
MAX5382 (Notes 2, 3)
(Note 2)
Code = 255
MAX5380/MAX5381
MAX5382
MAX5380/MAX5381
MAX5382
MAX5380/MAX5381
MAX5382
±40
±10
60
3
1
10
5
50
±1
8
±1
±1
±25
Bits
LSB
LSB
mV
dB
ppm/°C
% of
ideal FS
dB
ppm/°C
SYMBOLCONDITIONSMINTYPMAXUNITS
Code = 255, MAX5380/MAX5281 (Note 4)
Code = 255
LSB
kΩ
2_______________________________________________________________________________________
元器件交易网
Low-Cost, Low-Power, 8-Bit DACs with
2-Wire Serial Interface in SOT23
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +2.7V to +3.6V (MAX5380), V
DD
= +4.5V to +5.5V (MAX5381), V
DD
= +2.7V to +5.5V (MAX5382); R
L
= 10kΩ; C
L
= 50pF,
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are T
A
= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER REQUIREMENTS
MAX53802.73.6
Supply VoltageV
DD
MAX53814.55.5
V
MAX53822.75.5
Supply CurrentI
No load, all digital inputs at 0 or V, code = 255150230
DD
DD
Shutdown mode1
µA
DIGITAL INPUTS (SCL, SDA)
Input Low VoltageV
IL
0.3 x V
DD
V
Input High VoltageV
IH
0.7 x V
DD
V
Input HysteresisV
HYS
0.05 x V
DD
V
Input CapacitanceC
IN
(Note 7)10pF
Input Leakage CurrentI
IN
±10µA
Pulse Width of Spike Suppressedt
SP
050ns
DIGITAL OUTPUT (SDA, open drain)
Output Low Voltage V
I0.4
OL
SINK
= 3mA
I
SINK
= 6mA0.6
V
V
IH(MIN)
to V
IL(MAX)
,
Output Fall Time t
OF
bus capacitance =
I
SINK
= 3mA250
ns
10pF to 400pF
I
SINK
= 6mA250
TIMING CHARACTERISTICS
(Figure 3; V
DD
= +2.7V to +3.6V (MAX5380), V
DD
= +4.5V to +5.5V (MAX5381), V
DD
= +2.7V to +5.5V (MAX5382); R
L
= 10kΩ;
C
L
= 50pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are T
A
= +25°C.) (Note 7)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SCL Clock Frequencyf
SCL
0400
kHz
Bus Free Time Between a
STOP and a START Condition
t
BUF
1.3µs
Hold Time Repeated for a
START Condition
t
HD:STA
0.6µs
Low Period of the SCL Clockt
LOW
1.3µs
High Period of the SCL Clockt
HIGH
0.6µs
Setup Time for a Repeated
START Condition
t
SU:STA
0.6µs
Data Hold Timet
HD:DAT
00.9µs
Data Setup Timet
SU:DAT
100ns
_______________________________________________________________________________________3
MAX5380/MAX5381/MAX5382
元器件交易网
Low-Cost, Low-Power, 8-Bit DACs with
2-Wire Serial Interface in SOT23
M
A
X
5
3
8
0
/
M
A
X
5
3
8
1
/
M
A
X
5
3
8
2
TIMING CHARACTERISTICS (continued)
(Figure 3; V
DD
= +2.7V to +3.6V (MAX5380), V
DD
= +4.5V to +5.5V (MAX5381), V
DD
= +2.7V to +5.5V (MAX5382); R
L
= 10kΩ;
C
L
= 50pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are T
A
= +25°C.) (Note 7)
PARAMETER
Rise Time of Both SDA and
SCL Signals
Fall Time of Both SDA and
SCL Signals
Setup Time for STOP Condition
Capacitive Load for Each
Bus Line
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
SYMBOL
t
r
t
f
t
SU:STO
C
b
0.6
400
CONDITIONSMINTYPMAX
300
300
UNITS
ns
ns
µs
pF
Guaranteed from code 5 to code 255.
The offset value extrapolated from the range over which the INL is guaranteed.
MAX5382 tested at V
DD
= +5V ±10%.
MAX5380 tested at V
DD
= +3V ±10%, MAX5381 tested at V
DD
= 5V ±10%.
Actual output voltages at full scale are 255/256 x V
REF
.
Output settling time is measured by taking the code from code 5 to 255, and from code 255 to 5.
Guaranteed by design.
Typical Operating Characteristics
(V
DD
= +3.0V (MAX5380), V
DD
= +5.0V (MAX5381/MAX5382); R
L
= 10kΩ, T
A
= +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. CODE
M
A
X
5
3
8
0
/
1
/
2
-
0
1
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
M
A
X
5
3
8
0
/
1
/
2
-
0
2
INTEGRAL NONLINEARITY
vs. TEMPERATURE
M
A
X
5
3
8
0
/
1
/
2
-
0
3
0.075
0.050
0.025
00
-0.05
I
N
L
(
L
S
B
)
-0.05
I
N
L
(
L
S
B
)
I
N
L
(
L
S
B
)
0
-0.025
-0.050
-0.075
-0.100
050100150
CODE
200250300
-0.10
-0.10
-0.15
-0.15
-0.20
2.53.03.54.04.55.05.5
SUPPLY VOLTAGE (V)
-0.20
-40-20
TEMPERATURE (°C)
4_______________________________________________________________________________________
元器件交易网
Low-Cost, Low-Power, 8-Bit DACs with
2-Wire Serial Interface in SOT23
Typical Operating Characteristics (continued)
(V
DD
= +3.0V (MAX5380), V
DD
= +5.0V (MAX5381/MAX5382); R
L
= 10kΩ, T
A
= +25°C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY
DIFFERENTIAL NONLINEARITY
DIFFERENTIAL NONLINEARITY vs. CODE
vs. SUPPLY VOLTAGE
vs. TEMPERATURE
4
0
5
0
0
-
0
6
0
2
-
2
-
0.04
2
/
/
/
1
1
1
/
/
/
0
0
0
8
8
8
3
3
3
5
5
5
X
A
X
0.02
M
-0.02
A
-0.02
X
M
A
M
)
B
0
)
-0.04
-0.04
S
B
)
L
S
B
(
L
S
(
L
L
(
N
-0.02
L
D
N
L
D
-0.06
N
D
-0.06
-0.04
-0.06
-0.08
-0.08
-0.08
-0.10
-0.10
250300
2.53.03.54.04.55.05.5
-40-20
CODE
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TOTAL UNADJUSTED ERROR vs. CODE
OFFSET ERROR vs. SUPPLY VOLTAGE
OFFSET ERROR vs. TEMPERATURE
0.45
7
0
0
8
-
0
0
9
0
2
--
/
22
1
//
/
11
0
//
8
00
0.30
3
88
5
33
X
55
A
XX
M
AA
MM
0.15
-0.5
-0.5
)
V
m
(
)
B
S
0
)
V
R
L
m
O
R
(
(
-1.0
R
E
S
E
-1.0
U
-0.15
O
T
T
V
E
S
F
F
-0.30
O
-1.5
-1.5
-0.45
-0.60
-2.0
-2.0
250300
2.53.03.54.04.55.05.5
-40-20
CODE
SUPPLY VOLTAGE (V)TEMPERATURE (°C)
FULL-SCALE ERROR vs. SUPPLY VOLTAGE
FULL-SCALE ERROR vs. TEMPERATURE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
3
MAX5380/1/2-10
1.2
3
MAX5380/1/2-11
1.2
200
2
1
MAX5381
-
2
/
180
1
/
0
8
3
2
0.8
2
0.8
5
X
160
MAX5381
A
MAX5380
M
)
)
B
MAX5380
)
)
)
S
B
L
0.4
%
S
MAX5380
(
(
L
1
0.4
%
A
(
µ
140
R
MAX5382
R
(
1
MAX5381
R
(
O
O
R
O
T
R
R
O
R
N
120
R
R
R
R
E
MAX5382
E
0
E
R
E
0
E
E
0
E
L
L
E
A
A
L
MAX5382
0
R
E
R
L
U
100
A
C
C
C
A
C
Y
S
S
C
L
80
-0.4
-
S
-
L
-1
L
S
-
-1
-0.4
-
L
P
L
L
L
L
P
U
U
L
U
U
60
F
F
U
F
F
S
-2
-0.8
-2
-0.8
40
NO LOAD
20
-3
-1.2
-3
-1.2
0
2.53.03.54.04.55.05.5
-40-20
2.53.03.54.04.55.05.5
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________5
MAX5380/MAX5381/MAX5382
元器件交易网
Low-Cost, Low-Power, 8-Bit DACs with
2-Wire Serial Interface in SOT23
8
2
Typical Operating Characteristics (continued)
(V
DD
= +3.0V (MAX5380), V
DD
= +5.0V (MAX5381/MAX5382); R
L
= 10kΩ, T
A
= +25°C, unless otherwise noted.)
3
5
X
A
M
/
1
8
3
5
X
A
M
/
0
8
3
5
X
A
M
6
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. CODE
160
3
160
4
1
1
NO LOAD
-
-
2
2
/
/
1
1
/
/
0
0
8
8
3
3
155
5
155
5
X
X
A
A
M
MAX5381
MAX5381, V
M
DD
= +5.0V
)
)
A
A
µ
µ
(
150
(
150
T
T
N
N
MAX5382, V
DD
= +5.0V
E
MAX5382
E
R
R
R
R
U
145
U
145
C
C
MAX5380, V
DD
= +5.0V
Y
Y
L
MAX5380
L
P
P
140
P
P
140
MAX5380, V
U
U
DD
= +3.0V
S
S
135
135
NO LOAD
130
130
-40-20
TEMPERATURE (°C)
CODE
SHUTDOWN SUPPLY CURRENT
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
vs. TEMPERATURE
1.0
5
1.0
6
1
1
-
2
-
2
/
/
1
1
/
/
0
0
8
8
3
3
5
5
0.8
X
A
0.8
X
M
A
M
)
A
)
µ
A
(
µ
(
T
N
E
0.6
T
N
0.6
R
E
R
R
U
R
V
DD
= +5.0V
C
U
Y
L
0.4
C
Y
P
L
0.4
P
P
U
P
V
S
U
DD
= +3.0V
S
0.2
0.2
0
0
2.53.03.54.04.55.05.5
-40-20
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
OUTPUT LOAD REGULATION
OUTPUT VOLTAGE ON POWER-UP
4.5
MAX5380/1/2-17
8
1
A
-
2
/
1
/
0
)
4.0
8
V
3
5
(
X
E
A
L
M
A
3.5
C
S
OUT
L
3.0
L
50mV/div
U
F
T
2.5
U
O
V
2.0
B
)
1.5
C
0.2
V
(
V
DD
D
E
D
2V/div
O
E
C
0.1
O
R
E
Z
T
0
U
O
V
4µs/div
LOAD CURRENT (mA)
A: MAX5361/MAX5362, V
DD
= 4.5V FULL-SCALE OR SOURCING
B: MAX5360, FULL-SCALE, V
DD
= 2.7V SINKING, V
DD
= 5.0V SOURCING
C: MAX5360, FULL-SCALE, V
DD
= 2.7V SOURCING
D: ZERO CODE, V
DD
= 2.7V SINKING
E: ZERO CODE, V
DD
= 5.5V SINKING
_______________________________________________________________________________________
元器件交易网
Low-Cost, Low-Power, 8-Bit DACs with
2-Wire Serial Interface in SOT23
Typical Operating Characteristics (continued)
(V
DD
= +3.0V (MAX5380), V
DD
= +5.0V (MAX5381/MAX5382); R
L
= 10kΩ, T
A
= +25°C, unless otherwise noted.)
OUTPUT SETTLING
OUTPUT VOLTAGE EXITING SHUTDOWN
OUTPUT VOLTAGE ENTERING SHUTDOWN
FROM 1/4 FS TO 3/4 FS
9
1
1
0
2
-
2
-
2
-
2
/
2
/
1
/
1
/
1
/
0
/
0
8
0
8
3
8
3
5
3
5
X
5
X
A
X
A
M
A
M
M
OUT
OUT
OUT
500mV/div
500mV/div
0.5V/div
SDA
SDA
SDA
3V/div
3V/div
3V/div
10µs/div
1µs/div
1µs/div
MAX5380, SHDN TO 0x80
MAX5380, 0x80 TO SHDN
MAX5380
OUTPUT SETTLING
OUTPUT SETTLING
OUTPUT SETTLING
FROM 3/4 FS TO 1/4 FS
1LSB STEP UP
1LSB STEP DOWN
2
3
4
2
2
2
-
-
2
2
-
2
/
/
/
1
1
1
/
/
/
0
0
0
8
8
8
3
3
3
5
5
5
X
X
A
A
X
M
M
A
M
OUT
OUT
OUT
0.5V/div
20mV/div
20mV/div
AC-COUPLED
AC-COUPLED
SDA
SDA
SDA
3V/div
3V/div
3V/div
1µs/div
2µs/div
2µs/div
MAX5380
MAX5380, 0x7F TO 0x80
MAX5380, 0x80 TO 0x7F
Pin Description
PIN
NAME
FUNCTION
1OUTDAC Voltage Output
2GNDGround
3V
DD
Power-Supply Input
4SDASerial Data Input
5SCLSerial Clock Input
_______________________________________________________________________________________7
MAX5380/MAX5381/MAX5382
元器件交易网
Low-Cost, Low-Power, 8-Bit DACs with
2-Wire Serial Interface in SOT23
M
A
X
5
3
8
0
/
M
A
X
5
3
8
1
/
M
A
X
5
3
8
2
V
DD
V
REF
REF
CURRENT-
STEERING
DAC
255
CONTROL
LOGIC
DATA LATCH
8
SERIAL INPUT
REGISTER
MAX5380
MAX5381
MAX5382
OUT
SW1SW2SW255
SDA
SCL
10k
OUT
GND
Figure 1. Functional DiagramFigure 2. Current-Steering Topology
Table 1. Unipolar Code Output Voltage
DAC CODE
1111 1111
1000 0000
0000 0001
0000 0000
OUTPUT VOLTAGE
MAX5380
2V x (255 / 256)
+1V
7.8mV
0
MAX5381
4V x (255 / 256)
+2V
15.6mV
0
MAX5382
0.9 x V
DD
x (255 / 256)
0.9 x V
DD
/ 2
0.9 x V
DD
/ 256
0
Detailed Description
The MAX5380/MAX5381/MAX5382 voltage-output, 8-bit
digital-to-analog converters (DACs) offer full 8-bit perfor-
mance with less than 1LSB integral nonlinearity error
and less than 1LSB differential nonlinearity error, ensur-
ing monotonic performance. The devices use a simple
2-wire, fast-mode I
2
C-compatible serial interface that
operates at up to 400kHz. The MAX5380/MAX5381/
MAX5382 include an internal reference, an output
buffer, and a low-current shutdown mode, which make
these devices ideal for low-power, highly integrated
applications (See Figure 1. Functional Diagram).
currents is steered to the DAC output. The current is
then converted to a voltage across a resistor, and this
voltage is buffered by the output buffer amplifier.
Output Voltage
Table 1 shows the relationship between the DAC code
and the analog output voltage. The 8-bit DAC code is
binary unipolar with 1LSB = V
REF
/ 256. The MAX5380/
MAX5381 have a full-scale output voltage of (+2V -
1LSB) and (+4V - 1LSB), respectively, set by the internal
references. The MAX5382 has a full-scale output volt-
age of (0.9
x
V
DD
- 1LSB).
Output Buffer
The DAC voltage output is an internally buffered unity-
gain follower that typically slews at ±0.4V/µs. The out-
put can swing from 0 to full scale. With a 1/4 FS to 3/4
FS output transition, the amplifier outputs typically settle
to 1/2LSB in less than 5µs when loaded with 10kΩin
parallel with 50pF. The buffer amplifiers are stable with
any combination of resistive loads >10kΩand capaci-
tive loads <50pF.
Analog Section
The MAX5380/MAX5381/MAX5382 employ a current-
steering DAC topology as shown in Figure 2. At the core
of the DAC is a reference voltage-to-current converter
(V/I) that generates a reference current. This current is
mirrored to 255 equally weighted current sources. DAC
switches control the outputs of these current mirrors so
that only the desired fraction of the total current-mirror
8_______________________________________________________________________________________
元器件交易网
Low-Cost, Low-Power, 8-Bit DACs with
2-Wire Serial Interface in SOT23
SDA
t
SU:
DAT
t
SU:
STA
t
BUF
t
HD:
STA
t
LOW
t
HD:
DAT
t
SU:
STO
SCL
t
t
HIGH
HD:
STA
t
R
t
F
START CONDITIONREPEATED START CONDITIONSTOP CONDITIONSTART CONDITION
Figure 3. 2-Wire Serial Interface Timing Diagram
V
after a loss of power. The output glitch at startup is typi-
DD
cally less than 50mV.
µC
SDASCL
Shutdown Mode
The MAX5380/MAX5381/MAX5382 include a software-
SCLV
DD
controlled shutdown mode that reduces the supply cur-
R
S
*
MAX5380M
rent to <1µA. All internal circuitry is disabled, and an
2V REFERENCE
internal 10kΩresistor is placed from OUT to GND to
SDA
OUT
OFFSET ADJUSTMENT
ensure 0V at OUT while in shutdown. The device enters
shutdown in less than 5µs and exits shutdown in less
than 50µs.
SCLV
DD
Digital Section
MAX5381N
Serial Interface
4V REFERENCE
SDA
OUT
THRESHOLD ADJUSTMENT
The MAX5380/MAX5381/MAX5382 use a simple 2-wire
serial interface requiring only two I/O lines (2-wire bus)
of a standard microprocessor (µP) port. Figure 3 shows
the timing diagram for signals on the 2-wire bus.
SCLV
DD
The two bus lines (SDA and SCL) must be high when
MAX5382P
the bus is not in use. The MAX5380/MAX5381/
V
DD
REFERENCE
MAX5382 are receive-only devices (slaves) and must
SDA
OUT
GAIN ADJUSTMENT
be controlled by a bus master device. Figure 4 shows a
typical application where up to four devices can be
*R
S
IS OPTIONAL.
connected to the bus, provided they have different
address settings. External pull-up resistors are not nec-
Figure 4. Typical Application Circuit
essary on these lines (when driven by push-pull dri-
vers), though these DACs can be used in applications
Power-On Reset
where pull-up resistors are required (such as in I
2
C
The MAX5380/MAX5381/MAX5382 have a power-on
systems) to maintain compatibility with existing circuit-
reset circuit to set the DAC’s output to 0 when V
ry. The serial interface operates at SCL rates up to
DD
is
first applied or when V
400kHz. The SDA state is allowed to change only while
DD
dips below 1.7V (typ). This
ensures that unwanted DAC output voltages will not
SCL is low, with the exception of START and STOP con-
occur immediately following a system startup, such as
ditions as shown in Figure 5. Each transmission con-
sists of a START condition sent by the bus master
_______________________________________________________________________________________9
MAX5380/MAX5381/MAX5382
元器件交易网
Low-Cost, Low-Power, 8-Bit DACs with
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M
A
X
5
3
8
0
/
M
A
X
5
3
8
1
/
M
A
X
5
3
8
2
SDA
SCL
START CONDITION
STOP CONDITION
define a write or read protocol, sets the device’s power
mode (SHDN). The device is powered-down when
SHDN is set to one. During a device search routine, the
MAX5380/MAX5381/MAX5382 acknowledge both
options (SHDN = 0 or SHDN = 1), but do not change
their power state if a stop condition (or restart) is issued
immediately. The second byte (DAC data) must be
sent/received for the device to update both power
mode and DAC output.
DAC Data
The 8-bit DAC data is decoded as straight binary MSB
first with 1LSB = V
REF
/ 256 and converted into the cor-
responding analog voltage as shown in Table 1. After
receiving the data byte, the devices acknowledge its
receipt and expect a STOP condition, at which point
the DAC output is updated.
The MAX5380/MAX5381/MAX5382 update the output
and the power mode only if the second byte is clocked
in (SHDN = 0) or out (SHDN = 1) of the device. When
SHDN = 1, the master will read all ones when clocking
out a data byte. The MAX5380/MAX5381/MAX5382 do
not drive SDA except for the acknowledge bit.
I
2
C Compatibility
The MAX5380/MAX5381/MAX5382 are compatible with
existing I
2
C systems. SCL and SDA are high-imped-
ance inputs; SDA has an open drain that pulls the data
line low during the 9th clock pulse. Figure 7 shows a
typical I
2
C application. The communication protocol
supports standard I
2
C 8-bit communications. The gen-
eral call address is ignored, and CBUS formats are not
supported. The devices’ address is compatible with the
7-bit I
2
C addressing protocol only. No 10-bit formats
Figure 5. START and STOP Conditions
device, followed by the MAX5380/MAX5381/MAX5382s’
preset slave address, a power-mode bit, the DAC data,
and finally, a STOP condition (Figure 6). The bus is then
free for another transmission.
SDA’s state is sampled and therefore must remain sta-
ble while SCL is high. Data is transmitted in 8-bit bytes.
Nine clock cycles are required to transfer each byte to
the MAX5380/MAX5381/MAX5382. Release SDA during
the 9th clock cycle since the selected device acknowl-
edges receipt of the byte by pulling SDA low during
this time. A series resistor on the SDA line may be
needed if the master’s output is forced high while the
selected device acknowledges (Figure 4).
Slave Address
The MAX5380/MAX5381/MAX5382 are available with
one of four preset slave addresses. Each address
option is identified by the suffix L, M, N, or P added to
the part number. The address is defined as the 7MSBs
sent by the master after a START condition. The
address options are 0x60, 0x62, 0x64, 0x66 (left justi-
fied with LSB set to 0). The 8th bit, typically used to
SLAVE ADDRESS BYTE
SDA
0
MSB
1
START
CONDITION
*
L
M
N
P
A
1
A
2
0
0
0
1
1
1
0
1
*SEE ORDERING INFORMATION.
11
0
0A
1
A
2
LSB
89
SHDNACK
D7
MSB
10
D6D5
DAC CODE
D4
D3D2
D1
D0
LSB
1718
STOP
CONDITION
ACK
Figure 6. A Complete Serial Transmission
10______________________________________________________________________________________
元器件交易网
Low-Cost, Low-Power, 8-Bit DACs with
2-Wire Serial Interface in SOT23
V
DD
Applications Information
µC
Digital Inputs and Interface Logic
SDASCL
The serial 2-wire interface has logic levels defined as
V
IL
= 0.3
x
V
DD
and V
IH
= 0.7
x
V
DD
. All inputs include
Schmitt trigger buffers to accept slow-transition inter-
faces. This means that optocouplers can interface
SCLV
DD
directly to the MAX5380/MAX5381/MAX5382 without
MAX5380L
additional external logic. The digital inputs are compati-
2V REFERENCE
ble with CMOS logic levels and must not be driven with
SDAOUT
OFFSET ADJUSTMENT
voltages higher than V
DD
.
Power-Supply Bypassing and Layout
SCLV
Careful printed circuit board layout is important for best
DD
system performance. To reduce crosstalk and noise
MAX5381M
injection, keep analog and digital signals separate.
4V REFERENCE
Ensure that the ground return from GND to the supply
SDA
OUT
THRESHOLD ADJUSTMENT
ground is short and low impedance; a ground plane is
recommended. Bypass V
DD
with a 0.1µF capacitor to
ground as close as possible to the device. If the supply
SCLV
DD
is excessively noisy, connect a 10Ωresistor in series
with the supply and V
DD
and add additional capaci-
MAX5382N
V
tance.
DD
REFERENCE
SDA
OUT
GAIN ADJUSTMENT
Chip Information
TRANSISTOR COUNT: 2910
Figure 7. Typical I
2
C Application
are supported. RESTART protocol is supported, but an
immediate STOP condition is necessary to update the
DAC. The 8th bit of the address byte, typically used to
indicate a read or write protocol, is used in the MAX5380/
MAX5381/MAX5382 to enter or exit shutdown mode.
When MAX5380/MAX5381/MAX5382 are addressed in
I
2
C read mode, they enter shutdown mode.
______________________________________________________________________________________11
MAX5380/MAX5381/MAX5382
元器件交易网
Low-Cost, Low-Power, 8-Bit DACs with
2-Wire Serial Interface in SOT23
M
A
X
5
3
8
0
/
M
A
X
5
3
8
1
/
M
A
X
5
3
8
2
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to /packages.)
S
O
T
-
2
3
5
L
.
E
P
S
PACKAGE OUTLINE, SOT-23, 5L
21-0057
E
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
©2004 Maxim Integrated Products Printed USAis a registered trademark of Maxim Integrated Products.
2024年11月3日发(作者：风材)
元器件交易网
19-1641; Rev 2; 11/04
Low-Cost, Low-Power, 8-Bit DACs with
2-Wire Serial Interface in SOT23
General DescriptionFeatures
The MAX5380/MAX5381/MAX5382 are low-cost, 8-bit
digital-to-analog converters (DACs) in miniature 5-pin
♦8-Bit Accuracy in a Miniature 5-Pin SOT23
SOT23 packages, with a simple 2-wire serial interface
♦Wide +2.7V to +5.5V Supply Range (MAX5382)
that allows communication with multiple devices. The
MAX5380 has an internal +2V reference and operates
♦Low 230µA max Supply Current
from a +2.7V to +3.6V supply. The MAX5381 has an
♦1µA Shutdown Mode
internal +4V reference and operates from a +4.5V to
+5.5V supply. The MAX5382 operates over the full
♦Buffered Output Drives Resistive Loads
+2.7V to +5.5V supply range and has an internal refer-
♦Low-Glitch Power-On Reset to Zero DAC Output
ence equal to 0.9 x V
DD
.
2
The fast-mode I
2
C*-compatible serial interface allows
♦Fast I
C-Compatible Serial Interface
communication at data rates up to 400kbps, minimizing
♦<±5% Full-Scale Error (MAX5382)
board space and reducing interconnect complexity
in many applications. Each device is available with
♦<±1LSB max INL/DNL
one of four factory-preset addresses (see Selector
Guide).
Ordering Information
These DACs also include an output buffer, a low-power
shutdown mode, and a power-on reset that ensures the
PARTTEMP RANGEPIN-PACKAGE
DAC outputs are at zero when power is initially applied.
MAX5380_EUK-T
-40°C to +85°C5 SOT23
In shutdown mode, supply current is reduced to less
MAX5381_EUK-T
-40°C to +85°C5 SOT23
than 1µA and the output is pulled down to GND with a
MAX5382_EUK-T
-40°C to +85°C5 SOT23
10kΩresistor.
Applications
Selector Guide
Automatic Tuning (VCO)
REFERENCETOP
Power-Amplifier Bias Control
PARTADDRESS
(V)MARK
Programmable Threshold Levels
MAX5380LEUK
0x60+2.0ADMN
Automatic Gain Control
MAX5380MEUK0x62+2.0ADMZ
MAX5380NEUK0x64+2.0ADNF
Automatic Offset Adjustment
MAX5380PEUK0x66+2.0ADMP
MAX5381LEUK
0x60+4.0ADMV
Typical Operating Circuit
MAX5381MEUK0x62+4.0ADNB
MAX5381NEUK0x64+4.0ADNH
+2.7V TO +5.5V
MAX5381PEUK0x66+4.0
ADMR
MAX5382LEUK
0x600.9 x V
DD
ADMX
V
DD
MAX5382MEUK0x620.9 x V
DD
ADND
µC
MAX5382NEUK0x640.9 x V
DD
ADNJ
V
DD
MAX5382PEUK0x660.9 x V
DD
ADMT
PX.0/SDA
SDA
PX.1/SCL
SCL
MAX5382
OUT
Pin Configuration
GND
GND
TOP VIEW
OUT 15SCL
Purchase of I
2
C components from Maxim Integrated Products,
GND
2
MAX5380
Inc., or one of its sublicensed Associate Companies, conveys a
MAX5381
MAX5382
license under the Philips I
2
C Patent Rights to use these compo-
V
DD
34SDA
nents in an I
2
C system, provided that the system conforms to the
I
2
C Standard Specification defined by Philips.
SOT23-5
________________________________________________________________Maxim Integrated Products1
For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at
1-888-629-4642, or visit Maxim’s website at .
MAX5380/MAX5381/MAX5382
元器件交易网
Low-Cost, Low-Power, 8-Bit DACs with
2-Wire Serial Interface in SOT23
M
A
X
5
3
8
0
/
M
A
X
5
3
8
1
/
M
A
X
5
3
8
2
ABSOLUTE MAXIMUM RATINGS
V
DD
-0.3V to +6V
OUT, SCL, SDA -0.3V to +6V
Maximum Current into .50mA
Continuous Power Dissipation (T
A
= +70°C)
5-Pin SOT23 (derate 7.1mW/°C above +70°C).............571mW
Operating Temperature Ranges
MAX538_ _-40°C to +85°C
Storage -65°C to +150°C
Maximum .+150°C
Lead Temperature (soldering, 10s).................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= +2.7V to +3.6V (MAX5380), V
DD
= +4.5V to +5.5V (MAX5381), V
DD
= +2.7V to +5.5V (MAX5382); R
L
= 10kΩ; C
L
= 50pF,
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are T
A
= +25°C.)
PARAMETER
STATIC ACCURACY
Resolution
Integral Linearity Error
Differential Linearity Error
Offset Error
Offset Error Supply Rejection
Offset Error Temperature
Coefficient
Full-Scale Error
Full-Scale Error Supply Rejection
Full-Scale Error Temperature
Coefficient
DAC OUTPUT
MAX5380
Internal Reference (Note 5)REF
MAX5381
MAX5382
Output Load Regulation
Output Resistance
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
Output Settling Time
Digital Feedthrough
Digital-Analog Glitch Impulse
Wake-Up Time
Positive and negative
To 1/2 LSB, 50kΩand 50pF load (Note 6)
Code = 0, all digital inputs from 0 to V
DD
Code 127 to 128
From software shutdown
0.4
20
2
40
50
V/µs
µs
nVs
nVs
µs
Code = 255, 0 to 100µA
Code = 0, 0 to 100µA
V
OUT
= 0 to V
DD
, power-down mode
1.8
3.6
0.85 x
V
DD
2
4
0.9x
V
DD
0.5
0.5
10
2.2
4.4
0.95x
V
DD
V
INL
DNL
(Note 1)
Guaranteed monotonic
(Note 2)
MAX5382 (Notes 2, 3)
(Note 2)
Code = 255
MAX5380/MAX5381
MAX5382
MAX5380/MAX5381
MAX5382
MAX5380/MAX5381
MAX5382
±40
±10
60
3
1
10
5
50
±1
8
±1
±1
±25
Bits
LSB
LSB
mV
dB
ppm/°C
% of
ideal FS
dB
ppm/°C
SYMBOLCONDITIONSMINTYPMAXUNITS
Code = 255, MAX5380/MAX5281 (Note 4)
Code = 255
LSB
kΩ
2_______________________________________________________________________________________
元器件交易网
Low-Cost, Low-Power, 8-Bit DACs with
2-Wire Serial Interface in SOT23
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +2.7V to +3.6V (MAX5380), V
DD
= +4.5V to +5.5V (MAX5381), V
DD
= +2.7V to +5.5V (MAX5382); R
L
= 10kΩ; C
L
= 50pF,
T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are T
A
= +25°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER REQUIREMENTS
MAX53802.73.6
Supply VoltageV
DD
MAX53814.55.5
V
MAX53822.75.5
Supply CurrentI
No load, all digital inputs at 0 or V, code = 255150230
DD
DD
Shutdown mode1
µA
DIGITAL INPUTS (SCL, SDA)
Input Low VoltageV
IL
0.3 x V
DD
V
Input High VoltageV
IH
0.7 x V
DD
V
Input HysteresisV
HYS
0.05 x V
DD
V
Input CapacitanceC
IN
(Note 7)10pF
Input Leakage CurrentI
IN
±10µA
Pulse Width of Spike Suppressedt
SP
050ns
DIGITAL OUTPUT (SDA, open drain)
Output Low Voltage V
I0.4
OL
SINK
= 3mA
I
SINK
= 6mA0.6
V
V
IH(MIN)
to V
IL(MAX)
,
Output Fall Time t
OF
bus capacitance =
I
SINK
= 3mA250
ns
10pF to 400pF
I
SINK
= 6mA250
TIMING CHARACTERISTICS
(Figure 3; V
DD
= +2.7V to +3.6V (MAX5380), V
DD
= +4.5V to +5.5V (MAX5381), V
DD
= +2.7V to +5.5V (MAX5382); R
L
= 10kΩ;
C
L
= 50pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are T
A
= +25°C.) (Note 7)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SCL Clock Frequencyf
SCL
0400
kHz
Bus Free Time Between a
STOP and a START Condition
t
BUF
1.3µs
Hold Time Repeated for a
START Condition
t
HD:STA
0.6µs
Low Period of the SCL Clockt
LOW
1.3µs
High Period of the SCL Clockt
HIGH
0.6µs
Setup Time for a Repeated
START Condition
t
SU:STA
0.6µs
Data Hold Timet
HD:DAT
00.9µs
Data Setup Timet
SU:DAT
100ns
_______________________________________________________________________________________3
MAX5380/MAX5381/MAX5382
元器件交易网
Low-Cost, Low-Power, 8-Bit DACs with
2-Wire Serial Interface in SOT23
M
A
X
5
3
8
0
/
M
A
X
5
3
8
1
/
M
A
X
5
3
8
2
TIMING CHARACTERISTICS (continued)
(Figure 3; V
DD
= +2.7V to +3.6V (MAX5380), V
DD
= +4.5V to +5.5V (MAX5381), V
DD
= +2.7V to +5.5V (MAX5382); R
L
= 10kΩ;
C
L
= 50pF, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are T
A
= +25°C.) (Note 7)
PARAMETER
Rise Time of Both SDA and
SCL Signals
Fall Time of Both SDA and
SCL Signals
Setup Time for STOP Condition
Capacitive Load for Each
Bus Line
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
SYMBOL
t
r
t
f
t
SU:STO
C
b
0.6
400
CONDITIONSMINTYPMAX
300
300
UNITS
ns
ns
µs
pF
Guaranteed from code 5 to code 255.
The offset value extrapolated from the range over which the INL is guaranteed.
MAX5382 tested at V
DD
= +5V ±10%.
MAX5380 tested at V
DD
= +3V ±10%, MAX5381 tested at V
DD
= 5V ±10%.
Actual output voltages at full scale are 255/256 x V
REF
.
Output settling time is measured by taking the code from code 5 to 255, and from code 255 to 5.
Guaranteed by design.
Typical Operating Characteristics
(V
DD
= +3.0V (MAX5380), V
DD
= +5.0V (MAX5381/MAX5382); R
L
= 10kΩ, T
A
= +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. CODE
M
A
X
5
3
8
0
/
1
/
2
-
0
1
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
M
A
X
5
3
8
0
/
1
/
2
-
0
2
INTEGRAL NONLINEARITY
vs. TEMPERATURE
M
A
X
5
3
8
0
/
1
/
2
-
0
3
0.075
0.050
0.025
00
-0.05
I
N
L
(
L
S
B
)
-0.05
I
N
L
(
L
S
B
)
I
N
L
(
L
S
B
)
0
-0.025
-0.050
-0.075
-0.100
050100150
CODE
200250300
-0.10
-0.10
-0.15
-0.15
-0.20
2.53.03.54.04.55.05.5
SUPPLY VOLTAGE (V)
-0.20
-40-20
TEMPERATURE (°C)
4_______________________________________________________________________________________
元器件交易网
Low-Cost, Low-Power, 8-Bit DACs with
2-Wire Serial Interface in SOT23
Typical Operating Characteristics (continued)
(V
DD
= +3.0V (MAX5380), V
DD
= +5.0V (MAX5381/MAX5382); R
L
= 10kΩ, T
A
= +25°C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY
DIFFERENTIAL NONLINEARITY
DIFFERENTIAL NONLINEARITY vs. CODE
vs. SUPPLY VOLTAGE
vs. TEMPERATURE
4
0
5
0
0
-
0
6
0
2
-
2
-
0.04
2
/
/
/
1
1
1
/
/
/
0
0
0
8
8
8
3
3
3
5
5
5
X
A
X
0.02
M
-0.02
A
-0.02
X
M
A
M
)
B
0
)
-0.04
-0.04
S
B
)
L
S
B
(
L
S
(
L
L
(
N
-0.02
L
D
N
L
D
-0.06
N
D
-0.06
-0.04
-0.06
-0.08
-0.08
-0.08
-0.10
-0.10
250300
2.53.03.54.04.55.05.5
-40-20
CODE
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TOTAL UNADJUSTED ERROR vs. CODE
OFFSET ERROR vs. SUPPLY VOLTAGE
OFFSET ERROR vs. TEMPERATURE
0.45
7
0
0
8
-
0
0
9
0
2
--
/
22
1
//
/
11
0
//
8
00
0.30
3
88
5
33
X
55
A
XX
M
AA
MM
0.15
-0.5
-0.5
)
V
m
(
)
B
S
0
)
V
R
L
m
O
R
(
(
-1.0
R
E
S
E
-1.0
U
-0.15
O
T
T
V
E
S
F
F
-0.30
O
-1.5
-1.5
-0.45
-0.60
-2.0
-2.0
250300
2.53.03.54.04.55.05.5
-40-20
CODE
SUPPLY VOLTAGE (V)TEMPERATURE (°C)
FULL-SCALE ERROR vs. SUPPLY VOLTAGE
FULL-SCALE ERROR vs. TEMPERATURE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
3
MAX5380/1/2-10
1.2
3
MAX5380/1/2-11
1.2
200
2
1
MAX5381
-
2
/
180
1
/
0
8
3
2
0.8
2
0.8
5
X
160
MAX5381
A
MAX5380
M
)
)
B
MAX5380
)
)
)
S
B
L
0.4
%
S
MAX5380
(
(
L
1
0.4
%
A
(
µ
140
R
MAX5382
R
(
1
MAX5381
R
(
O
O
R
O
T
R
R
O
R
N
120
R
R
R
R
E
MAX5382
E
0
E
R
E
0
E
E
0
E
L
L
E
A
A
L
MAX5382
0
R
E
R
L
U
100
A
C
C
C
A
C
Y
S
S
C
L
80
-0.4
-
S
-
L
-1
L
S
-
-1
-0.4
-
L
P
L
L
L
L
P
U
U
L
U
U
60
F
F
U
F
F
S
-2
-0.8
-2
-0.8
40
NO LOAD
20
-3
-1.2
-3
-1.2
0
2.53.03.54.04.55.05.5
-40-20
2.53.03.54.04.55.05.5
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________5
MAX5380/MAX5381/MAX5382
元器件交易网
Low-Cost, Low-Power, 8-Bit DACs with
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8
2
Typical Operating Characteristics (continued)
(V
DD
= +3.0V (MAX5380), V
DD
= +5.0V (MAX5381/MAX5382); R
L
= 10kΩ, T
A
= +25°C, unless otherwise noted.)
3
5
X
A
M
/
1
8
3
5
X
A
M
/
0
8
3
5
X
A
M
6
SUPPLY CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. CODE
160
3
160
4
1
1
NO LOAD
-
-
2
2
/
/
1
1
/
/
0
0
8
8
3
3
155
5
155
5
X
X
A
A
M
MAX5381
MAX5381, V
M
DD
= +5.0V
)
)
A
A
µ
µ
(
150
(
150
T
T
N
N
MAX5382, V
DD
= +5.0V
E
MAX5382
E
R
R
R
R
U
145
U
145
C
C
MAX5380, V
DD
= +5.0V
Y
Y
L
MAX5380
L
P
P
140
P
P
140
MAX5380, V
U
U
DD
= +3.0V
S
S
135
135
NO LOAD
130
130
-40-20
TEMPERATURE (°C)
CODE
SHUTDOWN SUPPLY CURRENT
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
vs. TEMPERATURE
1.0
5
1.0
6
1
1
-
2
-
2
/
/
1
1
/
/
0
0
8
8
3
3
5
5
0.8
X
A
0.8
X
M
A
M
)
A
)
µ
A
(
µ
(
T
N
E
0.6
T
N
0.6
R
E
R
R
U
R
V
DD
= +5.0V
C
U
Y
L
0.4
C
Y
P
L
0.4
P
P
U
P
V
S
U
DD
= +3.0V
S
0.2
0.2
0
0
2.53.03.54.04.55.05.5
-40-20
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
OUTPUT LOAD REGULATION
OUTPUT VOLTAGE ON POWER-UP
4.5
MAX5380/1/2-17
8
1
A
-
2
/
1
/
0
)
4.0
8
V
3
5
(
X
E
A
L
M
A
3.5
C
S
OUT
L
3.0
L
50mV/div
U
F
T
2.5
U
O
V
2.0
B
)
1.5
C
0.2
V
(
V
DD
D
E
D
2V/div
O
E
C
0.1
O
R
E
Z
T
0
U
O
V
4µs/div
LOAD CURRENT (mA)
A: MAX5361/MAX5362, V
DD
= 4.5V FULL-SCALE OR SOURCING
B: MAX5360, FULL-SCALE, V
DD
= 2.7V SINKING, V
DD
= 5.0V SOURCING
C: MAX5360, FULL-SCALE, V
DD
= 2.7V SOURCING
D: ZERO CODE, V
DD
= 2.7V SINKING
E: ZERO CODE, V
DD
= 5.5V SINKING
_______________________________________________________________________________________
元器件交易网
Low-Cost, Low-Power, 8-Bit DACs with
2-Wire Serial Interface in SOT23
Typical Operating Characteristics (continued)
(V
DD
= +3.0V (MAX5380), V
DD
= +5.0V (MAX5381/MAX5382); R
L
= 10kΩ, T
A
= +25°C, unless otherwise noted.)
OUTPUT SETTLING
OUTPUT VOLTAGE EXITING SHUTDOWN
OUTPUT VOLTAGE ENTERING SHUTDOWN
FROM 1/4 FS TO 3/4 FS
9
1
1
0
2
-
2
-
2
-
2
/
2
/
1
/
1
/
1
/
0
/
0
8
0
8
3
8
3
5
3
5
X
5
X
A
X
A
M
A
M
M
OUT
OUT
OUT
500mV/div
500mV/div
0.5V/div
SDA
SDA
SDA
3V/div
3V/div
3V/div
10µs/div
1µs/div
1µs/div
MAX5380, SHDN TO 0x80
MAX5380, 0x80 TO SHDN
MAX5380
OUTPUT SETTLING
OUTPUT SETTLING
OUTPUT SETTLING
FROM 3/4 FS TO 1/4 FS
1LSB STEP UP
1LSB STEP DOWN
2
3
4
2
2
2
-
-
2
2
-
2
/
/
/
1
1
1
/
/
/
0
0
0
8
8
8
3
3
3
5
5
5
X
X
A
A
X
M
M
A
M
OUT
OUT
OUT
0.5V/div
20mV/div
20mV/div
AC-COUPLED
AC-COUPLED
SDA
SDA
SDA
3V/div
3V/div
3V/div
1µs/div
2µs/div
2µs/div
MAX5380
MAX5380, 0x7F TO 0x80
MAX5380, 0x80 TO 0x7F
Pin Description
PIN
NAME
FUNCTION
1OUTDAC Voltage Output
2GNDGround
3V
DD
Power-Supply Input
4SDASerial Data Input
5SCLSerial Clock Input
_______________________________________________________________________________________7
MAX5380/MAX5381/MAX5382
元器件交易网
Low-Cost, Low-Power, 8-Bit DACs with
2-Wire Serial Interface in SOT23
M
A
X
5
3
8
0
/
M
A
X
5
3
8
1
/
M
A
X
5
3
8
2
V
DD
V
REF
REF
CURRENT-
STEERING
DAC
255
CONTROL
LOGIC
DATA LATCH
8
SERIAL INPUT
REGISTER
MAX5380
MAX5381
MAX5382
OUT
SW1SW2SW255
SDA
SCL
10k
OUT
GND
Figure 1. Functional DiagramFigure 2. Current-Steering Topology
Table 1. Unipolar Code Output Voltage
DAC CODE
1111 1111
1000 0000
0000 0001
0000 0000
OUTPUT VOLTAGE
MAX5380
2V x (255 / 256)
+1V
7.8mV
0
MAX5381
4V x (255 / 256)
+2V
15.6mV
0
MAX5382
0.9 x V
DD
x (255 / 256)
0.9 x V
DD
/ 2
0.9 x V
DD
/ 256
0
Detailed Description
The MAX5380/MAX5381/MAX5382 voltage-output, 8-bit
digital-to-analog converters (DACs) offer full 8-bit perfor-
mance with less than 1LSB integral nonlinearity error
and less than 1LSB differential nonlinearity error, ensur-
ing monotonic performance. The devices use a simple
2-wire, fast-mode I
2
C-compatible serial interface that
operates at up to 400kHz. The MAX5380/MAX5381/
MAX5382 include an internal reference, an output
buffer, and a low-current shutdown mode, which make
these devices ideal for low-power, highly integrated
applications (See Figure 1. Functional Diagram).
currents is steered to the DAC output. The current is
then converted to a voltage across a resistor, and this
voltage is buffered by the output buffer amplifier.
Output Voltage
Table 1 shows the relationship between the DAC code
and the analog output voltage. The 8-bit DAC code is
binary unipolar with 1LSB = V
REF
/ 256. The MAX5380/
MAX5381 have a full-scale output voltage of (+2V -
1LSB) and (+4V - 1LSB), respectively, set by the internal
references. The MAX5382 has a full-scale output volt-
age of (0.9
x
V
DD
- 1LSB).
Output Buffer
The DAC voltage output is an internally buffered unity-
gain follower that typically slews at ±0.4V/µs. The out-
put can swing from 0 to full scale. With a 1/4 FS to 3/4
FS output transition, the amplifier outputs typically settle
to 1/2LSB in less than 5µs when loaded with 10kΩin
parallel with 50pF. The buffer amplifiers are stable with
any combination of resistive loads >10kΩand capaci-
tive loads <50pF.
Analog Section
The MAX5380/MAX5381/MAX5382 employ a current-
steering DAC topology as shown in Figure 2. At the core
of the DAC is a reference voltage-to-current converter
(V/I) that generates a reference current. This current is
mirrored to 255 equally weighted current sources. DAC
switches control the outputs of these current mirrors so
that only the desired fraction of the total current-mirror
8_______________________________________________________________________________________
元器件交易网
Low-Cost, Low-Power, 8-Bit DACs with
2-Wire Serial Interface in SOT23
SDA
t
SU:
DAT
t
SU:
STA
t
BUF
t
HD:
STA
t
LOW
t
HD:
DAT
t
SU:
STO
SCL
t
t
HIGH
HD:
STA
t
R
t
F
START CONDITIONREPEATED START CONDITIONSTOP CONDITIONSTART CONDITION
Figure 3. 2-Wire Serial Interface Timing Diagram
V
after a loss of power. The output glitch at startup is typi-
DD
cally less than 50mV.
µC
SDASCL
Shutdown Mode
The MAX5380/MAX5381/MAX5382 include a software-
SCLV
DD
controlled shutdown mode that reduces the supply cur-
R
S
*
MAX5380M
rent to <1µA. All internal circuitry is disabled, and an
2V REFERENCE
internal 10kΩresistor is placed from OUT to GND to
SDA
OUT
OFFSET ADJUSTMENT
ensure 0V at OUT while in shutdown. The device enters
shutdown in less than 5µs and exits shutdown in less
than 50µs.
SCLV
DD
Digital Section
MAX5381N
Serial Interface
4V REFERENCE
SDA
OUT
THRESHOLD ADJUSTMENT
The MAX5380/MAX5381/MAX5382 use a simple 2-wire
serial interface requiring only two I/O lines (2-wire bus)
of a standard microprocessor (µP) port. Figure 3 shows
the timing diagram for signals on the 2-wire bus.
SCLV
DD
The two bus lines (SDA and SCL) must be high when
MAX5382P
the bus is not in use. The MAX5380/MAX5381/
V
DD
REFERENCE
MAX5382 are receive-only devices (slaves) and must
SDA
OUT
GAIN ADJUSTMENT
be controlled by a bus master device. Figure 4 shows a
typical application where up to four devices can be
*R
S
IS OPTIONAL.
connected to the bus, provided they have different
address settings. External pull-up resistors are not nec-
Figure 4. Typical Application Circuit
essary on these lines (when driven by push-pull dri-
vers), though these DACs can be used in applications
Power-On Reset
where pull-up resistors are required (such as in I
2
C
The MAX5380/MAX5381/MAX5382 have a power-on
systems) to maintain compatibility with existing circuit-
reset circuit to set the DAC’s output to 0 when V
ry. The serial interface operates at SCL rates up to
DD
is
first applied or when V
400kHz. The SDA state is allowed to change only while
DD
dips below 1.7V (typ). This
ensures that unwanted DAC output voltages will not
SCL is low, with the exception of START and STOP con-
occur immediately following a system startup, such as
ditions as shown in Figure 5. Each transmission con-
sists of a START condition sent by the bus master
_______________________________________________________________________________________9
MAX5380/MAX5381/MAX5382
元器件交易网
Low-Cost, Low-Power, 8-Bit DACs with
2-Wire Serial Interface in SOT23
M
A
X
5
3
8
0
/
M
A
X
5
3
8
1
/
M
A
X
5
3
8
2
SDA
SCL
START CONDITION
STOP CONDITION
define a write or read protocol, sets the device’s power
mode (SHDN). The device is powered-down when
SHDN is set to one. During a device search routine, the
MAX5380/MAX5381/MAX5382 acknowledge both
options (SHDN = 0 or SHDN = 1), but do not change
their power state if a stop condition (or restart) is issued
immediately. The second byte (DAC data) must be
sent/received for the device to update both power
mode and DAC output.
DAC Data
The 8-bit DAC data is decoded as straight binary MSB
first with 1LSB = V
REF
/ 256 and converted into the cor-
responding analog voltage as shown in Table 1. After
receiving the data byte, the devices acknowledge its
receipt and expect a STOP condition, at which point
the DAC output is updated.
The MAX5380/MAX5381/MAX5382 update the output
and the power mode only if the second byte is clocked
in (SHDN = 0) or out (SHDN = 1) of the device. When
SHDN = 1, the master will read all ones when clocking
out a data byte. The MAX5380/MAX5381/MAX5382 do
not drive SDA except for the acknowledge bit.
I
2
C Compatibility
The MAX5380/MAX5381/MAX5382 are compatible with
existing I
2
C systems. SCL and SDA are high-imped-
ance inputs; SDA has an open drain that pulls the data
line low during the 9th clock pulse. Figure 7 shows a
typical I
2
C application. The communication protocol
supports standard I
2
C 8-bit communications. The gen-
eral call address is ignored, and CBUS formats are not
supported. The devices’ address is compatible with the
7-bit I
2
C addressing protocol only. No 10-bit formats
Figure 5. START and STOP Conditions
device, followed by the MAX5380/MAX5381/MAX5382s’
preset slave address, a power-mode bit, the DAC data,
and finally, a STOP condition (Figure 6). The bus is then
free for another transmission.
SDA’s state is sampled and therefore must remain sta-
ble while SCL is high. Data is transmitted in 8-bit bytes.
Nine clock cycles are required to transfer each byte to
the MAX5380/MAX5381/MAX5382. Release SDA during
the 9th clock cycle since the selected device acknowl-
edges receipt of the byte by pulling SDA low during
this time. A series resistor on the SDA line may be
needed if the master’s output is forced high while the
selected device acknowledges (Figure 4).
Slave Address
The MAX5380/MAX5381/MAX5382 are available with
one of four preset slave addresses. Each address
option is identified by the suffix L, M, N, or P added to
the part number. The address is defined as the 7MSBs
sent by the master after a START condition. The
address options are 0x60, 0x62, 0x64, 0x66 (left justi-
fied with LSB set to 0). The 8th bit, typically used to
SLAVE ADDRESS BYTE
SDA
0
MSB
1
START
CONDITION
*
L
M
N
P
A
1
A
2
0
0
0
1
1
1
0
1
*SEE ORDERING INFORMATION.
11
0
0A
1
A
2
LSB
89
SHDNACK
D7
MSB
10
D6D5
DAC CODE
D4
D3D2
D1
D0
LSB
1718
STOP
CONDITION
ACK
Figure 6. A Complete Serial Transmission
10______________________________________________________________________________________
元器件交易网
Low-Cost, Low-Power, 8-Bit DACs with
2-Wire Serial Interface in SOT23
V
DD
Applications Information
µC
Digital Inputs and Interface Logic
SDASCL
The serial 2-wire interface has logic levels defined as
V
IL
= 0.3
x
V
DD
and V
IH
= 0.7
x
V
DD
. All inputs include
Schmitt trigger buffers to accept slow-transition inter-
faces. This means that optocouplers can interface
SCLV
DD
directly to the MAX5380/MAX5381/MAX5382 without
MAX5380L
additional external logic. The digital inputs are compati-
2V REFERENCE
ble with CMOS logic levels and must not be driven with
SDAOUT
OFFSET ADJUSTMENT
voltages higher than V
DD
.
Power-Supply Bypassing and Layout
SCLV
Careful printed circuit board layout is important for best
DD
system performance. To reduce crosstalk and noise
MAX5381M
injection, keep analog and digital signals separate.
4V REFERENCE
Ensure that the ground return from GND to the supply
SDA
OUT
THRESHOLD ADJUSTMENT
ground is short and low impedance; a ground plane is
recommended. Bypass V
DD
with a 0.1µF capacitor to
ground as close as possible to the device. If the supply
SCLV
DD
is excessively noisy, connect a 10Ωresistor in series
with the supply and V
DD
and add additional capaci-
MAX5382N
V
tance.
DD
REFERENCE
SDA
OUT
GAIN ADJUSTMENT
Chip Information
TRANSISTOR COUNT: 2910
Figure 7. Typical I
2
C Application
are supported. RESTART protocol is supported, but an
immediate STOP condition is necessary to update the
DAC. The 8th bit of the address byte, typically used to
indicate a read or write protocol, is used in the MAX5380/
MAX5381/MAX5382 to enter or exit shutdown mode.
When MAX5380/MAX5381/MAX5382 are addressed in
I
2
C read mode, they enter shutdown mode.
______________________________________________________________________________________11
MAX5380/MAX5381/MAX5382
元器件交易网
Low-Cost, Low-Power, 8-Bit DACs with
2-Wire Serial Interface in SOT23
M
A
X
5
3
8
0
/
M
A
X
5
3
8
1
/
M
A
X
5
3
8
2
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to /packages.)
S
O
T
-
2
3
5
L
.
E
P
S
PACKAGE OUTLINE, SOT-23, 5L
21-0057
E
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
©2004 Maxim Integrated Products Printed USAis a registered trademark of Maxim Integrated Products.