2024年3月25日发(作者：汝雨)
7Series FPGAs Data Sheet: Overview
Spartan-7 FPGA Feature Summary
Table 2:Spartan-7 FPGA Feature Summary by Device
CLB
Device
Logic
Cells
6,000
12,800
23,360
52,160
76,800
102,400
Slices
(1)
938
2,000
3,650
8,150
12,000
16,000
Max
Distributed
RAM (Kb)
70
150
313
600
832
1,100
DSP
Slices
(2)
10
20
80
120
140
160
Block RAM Blocks
(3)
18Kb
10
20
90
150
180
240
36Kb
5
10
45
75
90
120
Max
(Kb)
180
360
1,620
2,700
3,240
4,320
CMTs
(4)
PCIeGT
XADC
Blocks
0
0
1
1
1
1
Total I/O
Banks
(5)
2
2
3
5
8
8
Max User
I/O
100
100
150
250
400
400
XC7S6
XC7S15
XC7S25
XC7S50
XC7S75
XC7S100
2
2
3
5
8
8
0
0
0
0
0
0
0
0
0
0
0
0
Notes:
1.
2.
3.
4.
5.
Each 7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.
Each DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an accumulator.
Block RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18Kb blocks.
Each CMT contains one MMCM and one PLL.
Does not include configuration Bank 0.
Table 3:Spartan-7 FPGA Device-Package Combinations and Maximum I/Os
Package
Size (mm)
BallPitch(mm)
Device
XC7S6
XC7S15
XC7S25
XC7S50
XC7S75
XC7S100
CPGA196
8 x 8
0.5
HR I/O
(1)
100
100
CSGA225
13 x 13
0.8
HR I/O
(1)
100
100
150150
210
CSGA324
15 x 15
0.8
HR I/O
(1)
FTGB196
15 x 15
1.0
HR I/O
(1)
100
100
100
100250
338
338
400
400
FGGA484
23 x 23
1.0
HR I/O
(1)
FGGA676
27 x 27
1.0
HR I/O
(1)
Notes:
= High-range I/O with support for I/O voltage from 1.2V to 3.3V.
DS180 (v2.6) February 27, 2018
Product Specification
7Series FPGAs Data Sheet: Overview
Encryption, Readback, and Partial Reconfiguration
In all 7series FPGAs (except XC7S6 and XC7S15), the FPGA bitstream, which contains sensitive customer IP, can be
protected with 256-bit AES encryption and HMAC/SHA-256 authentication to prevent unauthorized copying of the design.
The FPGA performs decryption on the fly during configuration using an internally stored 256-bit key. This key can reside in
battery-backed RAM or in nonvolatile eFUSE bits.
Most configuration data can be read back without affecting the system's operation. Typically, configuration is an
all-or-nothing operation, but Xilinx 7series FPGAs support partial reconfiguration. This is an extremely powerful and flexible
feature that allows the user to change portions of the FPGA while other portions remain static. Users can time-slice these
portions to fit more IP into smaller devices, saving cost and power. Where applicable in certain designs, partial
reconfiguration can greatly improve the versatility of the FPGA.
XADC (Analog-to-Digital Converter)
Highlights of the XADC architecture include:
•
•
•
•
•
Dual 12-bit 1MSPS analog-to-digital converters (ADCs)
Up to 17 flexible and user-configurable analog inputs
On-chip or external reference option
On-chip temperature (±4°C max error) and power supply (±1% max error) sensors
Continuous JTAG access to ADC measurements
All Xilinx 7 series FPGAs (except XC7S6 and XC7S15) integrate a new flexible analog interface called XADC. When
combined with the programmable logic capability of the 7 series FPGAs, the XADC can address a broad range of data
acquisition and monitoring requirements. For more information, go.
The XADC contains two 12-bit 1 MSPS ADCs with separate track and hold amplifiers, an on-chip analog multiplexer (up to
17 external analog input channels supported), and on-chip thermal and supply sensors. The two ADCs can be configured to
simultaneously sample two external-input analog channels. The track and hold amplifiers support a range of analog input
signal types, including unipolar, bipolar, and differential. The analog inputs can support signal bandwidths of at least
500 KHz at sample rates of 1MSPS. It is possible to support higher analog bandwidths using external analog multiplexer
mode with the dedicated analog input (see UG480
, 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual
12-Bit 1 MSPS Analog-to-Digital Converter User Guide).
The XADC optionally uses an on-chip reference circuit (±1%), thereby eliminating the need for any external active
components for basic on-chip monitoring of temperature and power supply rails. To achieve the full 12-bit performance of the
ADCs, an external 1.25V reference IC is recommended.
If the XADC is not instantiated in a design, then by default it digitizes the output of all on-chip sensors. The most recent
measurement results (together with maximum and minimum readings) are stored in dedicated registers for access at any
time via the JTAG interface. User-defined alarm thresholds can automatically indicate over-temperature events and
unacceptable power supply variation. A user-specified limit (for example, 100°C) can be used to initiate an automatic
powerdown.
EasyPath-7 FPGAs
EasyPath-7 FPGAs provide a fast, simple, and risk-free solution for cost reducing Kintex-7, Virtex-7 T, and Virtex-7 XT FPGA
designs. EasyPath-7 FPGAs support the same packages, speed grades, and match all Kintex-7 or Virtex-7 FPGA data
sheet specifications (in function and timing). With no re-engineering or re-qualification, EasyPath-7 FPGAs deliver the
lowest total product cost compared to any other FPGA cost-reduction solution.
DS180 (v2.6) February 27, 2018
Product Specification
7Series FPGAs Data Sheet: Overview
7Series FPGA Ordering Information
Table12 shows the speed and temperature grades available in the different device families. Some devices might not be available in every
speed and temperature grade.
Table 12:7 Series Speed Grade and Temperature Ranges
Device
Family
Speed Grade, Temperature Range, and Operating Voltage
Devices
Commercial (C)
0°C to +85°C
-2C (1.0V)
Spartan-7All-1C (1.0V)
Extended (E)
0°C to +100°C
Industrial (I)
–40°C to +100°C
-2I (1.0V)
-1I (1.0V)
-1LI (0.95V)
Expanded (Q)
–40°C to +125°C
-1Q (1.0V)
-3E (1.0V)
-2C (1.0V)
Artix-7All
-1C (1.0V)
-2LE (1.0V or 0.9V)
-1I (1.0V)
-1LI (0.95V)
-3E (1.0V)
XC7K70T
-2C (1.0V)
-2LE (1.0V or 0.9V)
-1C (1.0V)
XC7K160T
XC7K325T
XC7K355T
XC7K410T
XC7K420T
XC7K480T
-3E (1.0V)
-2C (1.0V)
-2LE (1.0V or 0.9V)
-1C (1.0V)
-3E (1.0V)
XC7V585T
-2C (1.0V)
-2LE (1.0V)
-1C (1.0V)
-2C (1.0V)
XC7V2000T
-1C (1.0V)
-3E (1.0V)
XC7VX330T
XC7VX415T
XC7VX485T
XC7VX550T
XC7VX690T
-2C (1.0V)
-2LE (1.0V)
-1C (1.0V)
-2C (1.0V)
XC7VX980T
-1C (1.0V)
-2C (1.0V)
XC7VX1140T
-1C (1.0V)
-2C (1.0V)
Virtex-7 HTAll
-1C (1.0V)
-2GE (1.0V)
-2LE (1.0V)
-2GE (1.0V)
-2LE (1.0V)
-1I (1.0V)
-2LE (1.0V)
-1I (1.0V)
-1I (1.0V)
-2I (1.0V)
-2GE (1.0V)
-2LE (1.0V)
-1I (1.0V)
-1I (1.0V)
-2I (1.0V)
-2I (1.0V)
-2LI (0.95V)
-1I (1.0V)
-1I (1.0V)
-2I (1.0V)
-2I (1.0V)
Kintex-7
Virtex-7 T
Virtex-7 XT
DS180 (v2.6) February 27, 2018
Product Specification
2024年3月25日发(作者：汝雨)
7Series FPGAs Data Sheet: Overview
Spartan-7 FPGA Feature Summary
Table 2:Spartan-7 FPGA Feature Summary by Device
CLB
Device
Logic
Cells
6,000
12,800
23,360
52,160
76,800
102,400
Slices
(1)
938
2,000
3,650
8,150
12,000
16,000
Max
Distributed
RAM (Kb)
70
150
313
600
832
1,100
DSP
Slices
(2)
10
20
80
120
140
160
Block RAM Blocks
(3)
18Kb
10
20
90
150
180
240
36Kb
5
10
45
75
90
120
Max
(Kb)
180
360
1,620
2,700
3,240
4,320
CMTs
(4)
PCIeGT
XADC
Blocks
0
0
1
1
1
1
Total I/O
Banks
(5)
2
2
3
5
8
8
Max User
I/O
100
100
150
250
400
400
XC7S6
XC7S15
XC7S25
XC7S50
XC7S75
XC7S100
2
2
3
5
8
8
0
0
0
0
0
0
0
0
0
0
0
0
Notes:
1.
2.
3.
4.
5.
Each 7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.
Each DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an accumulator.
Block RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18Kb blocks.
Each CMT contains one MMCM and one PLL.
Does not include configuration Bank 0.
Table 3:Spartan-7 FPGA Device-Package Combinations and Maximum I/Os
Package
Size (mm)
BallPitch(mm)
Device
XC7S6
XC7S15
XC7S25
XC7S50
XC7S75
XC7S100
CPGA196
8 x 8
0.5
HR I/O
(1)
100
100
CSGA225
13 x 13
0.8
HR I/O
(1)
100
100
150150
210
CSGA324
15 x 15
0.8
HR I/O
(1)
FTGB196
15 x 15
1.0
HR I/O
(1)
100
100
100
100250
338
338
400
400
FGGA484
23 x 23
1.0
HR I/O
(1)
FGGA676
27 x 27
1.0
HR I/O
(1)
Notes:
= High-range I/O with support for I/O voltage from 1.2V to 3.3V.
DS180 (v2.6) February 27, 2018
Product Specification
7Series FPGAs Data Sheet: Overview
Encryption, Readback, and Partial Reconfiguration
In all 7series FPGAs (except XC7S6 and XC7S15), the FPGA bitstream, which contains sensitive customer IP, can be
protected with 256-bit AES encryption and HMAC/SHA-256 authentication to prevent unauthorized copying of the design.
The FPGA performs decryption on the fly during configuration using an internally stored 256-bit key. This key can reside in
battery-backed RAM or in nonvolatile eFUSE bits.
Most configuration data can be read back without affecting the system's operation. Typically, configuration is an
all-or-nothing operation, but Xilinx 7series FPGAs support partial reconfiguration. This is an extremely powerful and flexible
feature that allows the user to change portions of the FPGA while other portions remain static. Users can time-slice these
portions to fit more IP into smaller devices, saving cost and power. Where applicable in certain designs, partial
reconfiguration can greatly improve the versatility of the FPGA.
XADC (Analog-to-Digital Converter)
Highlights of the XADC architecture include:
•
•
•
•
•
Dual 12-bit 1MSPS analog-to-digital converters (ADCs)
Up to 17 flexible and user-configurable analog inputs
On-chip or external reference option
On-chip temperature (±4°C max error) and power supply (±1% max error) sensors
Continuous JTAG access to ADC measurements
All Xilinx 7 series FPGAs (except XC7S6 and XC7S15) integrate a new flexible analog interface called XADC. When
combined with the programmable logic capability of the 7 series FPGAs, the XADC can address a broad range of data
acquisition and monitoring requirements. For more information, go.
The XADC contains two 12-bit 1 MSPS ADCs with separate track and hold amplifiers, an on-chip analog multiplexer (up to
17 external analog input channels supported), and on-chip thermal and supply sensors. The two ADCs can be configured to
simultaneously sample two external-input analog channels. The track and hold amplifiers support a range of analog input
signal types, including unipolar, bipolar, and differential. The analog inputs can support signal bandwidths of at least
500 KHz at sample rates of 1MSPS. It is possible to support higher analog bandwidths using external analog multiplexer
mode with the dedicated analog input (see UG480
, 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual
12-Bit 1 MSPS Analog-to-Digital Converter User Guide).
The XADC optionally uses an on-chip reference circuit (±1%), thereby eliminating the need for any external active
components for basic on-chip monitoring of temperature and power supply rails. To achieve the full 12-bit performance of the
ADCs, an external 1.25V reference IC is recommended.
If the XADC is not instantiated in a design, then by default it digitizes the output of all on-chip sensors. The most recent
measurement results (together with maximum and minimum readings) are stored in dedicated registers for access at any
time via the JTAG interface. User-defined alarm thresholds can automatically indicate over-temperature events and
unacceptable power supply variation. A user-specified limit (for example, 100°C) can be used to initiate an automatic
powerdown.
EasyPath-7 FPGAs
EasyPath-7 FPGAs provide a fast, simple, and risk-free solution for cost reducing Kintex-7, Virtex-7 T, and Virtex-7 XT FPGA
designs. EasyPath-7 FPGAs support the same packages, speed grades, and match all Kintex-7 or Virtex-7 FPGA data
sheet specifications (in function and timing). With no re-engineering or re-qualification, EasyPath-7 FPGAs deliver the
lowest total product cost compared to any other FPGA cost-reduction solution.
DS180 (v2.6) February 27, 2018
Product Specification
7Series FPGAs Data Sheet: Overview
7Series FPGA Ordering Information
Table12 shows the speed and temperature grades available in the different device families. Some devices might not be available in every
speed and temperature grade.
Table 12:7 Series Speed Grade and Temperature Ranges
Device
Family
Speed Grade, Temperature Range, and Operating Voltage
Devices
Commercial (C)
0°C to +85°C
-2C (1.0V)
Spartan-7All-1C (1.0V)
Extended (E)
0°C to +100°C
Industrial (I)
–40°C to +100°C
-2I (1.0V)
-1I (1.0V)
-1LI (0.95V)
Expanded (Q)
–40°C to +125°C
-1Q (1.0V)
-3E (1.0V)
-2C (1.0V)
Artix-7All
-1C (1.0V)
-2LE (1.0V or 0.9V)
-1I (1.0V)
-1LI (0.95V)
-3E (1.0V)
XC7K70T
-2C (1.0V)
-2LE (1.0V or 0.9V)
-1C (1.0V)
XC7K160T
XC7K325T
XC7K355T
XC7K410T
XC7K420T
XC7K480T
-3E (1.0V)
-2C (1.0V)
-2LE (1.0V or 0.9V)
-1C (1.0V)
-3E (1.0V)
XC7V585T
-2C (1.0V)
-2LE (1.0V)
-1C (1.0V)
-2C (1.0V)
XC7V2000T
-1C (1.0V)
-3E (1.0V)
XC7VX330T
XC7VX415T
XC7VX485T
XC7VX550T
XC7VX690T
-2C (1.0V)
-2LE (1.0V)
-1C (1.0V)
-2C (1.0V)
XC7VX980T
-1C (1.0V)
-2C (1.0V)
XC7VX1140T
-1C (1.0V)
-2C (1.0V)
Virtex-7 HTAll
-1C (1.0V)
-2GE (1.0V)
-2LE (1.0V)
-2GE (1.0V)
-2LE (1.0V)
-1I (1.0V)
-2LE (1.0V)
-1I (1.0V)
-1I (1.0V)
-2I (1.0V)
-2GE (1.0V)
-2LE (1.0V)
-1I (1.0V)
-1I (1.0V)
-2I (1.0V)
-2I (1.0V)
-2LI (0.95V)
-1I (1.0V)
-1I (1.0V)
-2I (1.0V)
-2I (1.0V)
Kintex-7
Virtex-7 T
Virtex-7 XT
DS180 (v2.6) February 27, 2018
Product Specification