2024年3月25日发(作者：才晴虹)
7Series FPGAs Data Sheet: Overview
DS180 (v2.6.1) September 8, 2020Product Specification
General Description
Xilinx® 7series FPGAs comprise four FPGA families that address the complete range of system requirements, ranging from low cost, small form factor,
cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding
high-performance applications. The 7series FPGAs include:
•Spartan®-7 Family: Optimized for low cost, lowest power, and high
I/O performance. Available in low-cost, very small form-factor
packaging for smallest PCB footprint.
Artix®-7 Family: Optimized for low power applications requiring serial
transceivers and high DSP and logic throughput. Provides the lowest
total bill of materials cost for high-throughput, cost-sensitive
applications.
•Kintex®-7 Family: Optimized for best price-performance with a 2X
improvement compared to previous generation, enabling a new class
of FPGAs.
Virtex®-7 Family: Optimized for highest system performance and
capacity with a 2X improvement in system performance. Highest
capability devices enabled by stacked silicon interconnect (SSI)
technology.
••
Built on a state-of-the-art, high-performance, low-power (HPL), 28nm, high-k metal gate (HKMG) process technology, 7series FPGAs enable an
unparalleled increase in system performance with 2.9Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3TMAC/s DSP, while consuming 50% less
power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs.
Summary of 7Series FPGA Features
•
•
•
•
•
•
Advanced high-performance FPGA logic based on real 6-input look-
up table (LUT) technology configurable as distributed memory.
36Kb dual-port block RAM with built-in FIFO logic for on-chip data
buffering.
High-performance SelectIO™ technology with support for DDR3
interfaces up to 1,866 Mb/s.
High-speed serial connectivity with built-in multi-gigabit transceivers
from 600
Mb/s to max. rates of 6.6Gb/s up to 28.05Gb/s, offering a
special low-power mode, optimized for chip-to-chip interfaces.
A user configurable analog interface (XADC), incorporating dual
12-bit 1MSPS analog-to-digital converters with on-chip thermal and
supply sensors.
DSP slices with 25x18 multiplier, 48-bit accumulator, and pre-adder
for high-performance filtering, including optimized symmetric
coefficient filtering.
•
•
•
•
•
Powerful clock management tiles (CMT), combining phase-locked
loop (PLL) and mixed-mode clock manager (MMCM) blocks for high
precision and low jitter.
Quickly deploy embedded processing with MicroBlaze™ processor.
Integrated block for PCIExpress® (PCIe), for up to x8 Gen3
Endpoint and Root Port designs.
Wide variety of configuration options, including support for
commodity memories, 256-bit AES encryption with HMAC/SHA-256
authentication, and built-in SEU detection and correction.
Low-cost, wire-bond, bare-die flip-chip, and high signal integrity flip-
chip packaging offering easy migration between family members in
the same package. All packages available in Pb-free and selected
packages in Pb option.
Designed for high performance and lowest power with 28nm,
HKMG, HPL process, 1.0V core voltage process technology and
0.9V core voltage option for even lower power.
•
Table 1:7Series Families Comparison
Max. Capability
Logic Cells
Block RAM
(1)
DSP Slices
DSP Performance
(2)
MicroBlaze CPU
(3)
Transceivers
Transceiver Speed
Serial Bandwidth
PCIe Interface
Memory Interface
I/O Pins
I/O Voltage
Package Options
Notes:
1.
2.
3.
Additional memory available in the form of distributed RAM.
Peak DSP performance numbers are based on symmetrical filter implementation.
Peak MicroBlaze CPU performance numbers based on microcontroller preset.
Spartan-7
102K
4.2Mb
160
176 GMAC/s
260 DMIPs
–
–
–
–
800Mb/s
400
1.2V–3.3V
Low-Cost, Wire-Bond
Artix-7
215K
13Mb
740
929GMAC/s
303 DMIPs
16
6.6Gb/s
211Gb/s
x4 Gen2
1,066Mb/s
500
1.2V–3.3V
Low-Cost, Wire-Bond,
Bare-Die Flip-Chip
Kintex-7
478K
34Mb
1,920
2,845GMAC/s
438 DMIPs
32
12.5Gb/s
800Gb/s
x8 Gen2
1,866Mb/s
500
1.2V–3.3V
Bare-Die Flip-Chip and High-
Performance Flip-Chip
Virtex-7
1,955K
68Mb
3,600
5,335GMAC/s
441 DMIPs
96
28.05Gb/s
2,784Gb/s
x8 Gen3
1,866Mb/s
1,200
1.2V–3.3V
Highest Performance
Flip-Chip
DS180 (v2.6.1) September 8, 2020
Product Specification
7Series FPGAs Data Sheet: Overview
Artix-7 FPGA Feature Summary
Table 4:Artix-7 FPGA Feature Summary by Device
Logic
Cells
Configurable Logic Blocks
(CLBs)
Slices
(1)
2,000
2,600
3,650
5,200
8,150
11,800
15,850
33,650
Max
Distributed
RAM (Kb)
171
200
313
400
600
892
1,188
2,888
Block RAM Blocks
(3)
DSP48E1
Slices
(2)
18Kb
40
50
90
100
150
210
270
730
36Kb
20
25
45
50
75
105
135
365
Max
(Kb)
720
900
1,620
1,800
2,700
3,780
4,860
13,140
CMTs
(4)
PCIe
(5)
GTPs
XADC
Blocks
Total I/O
Banks
(6)
Max User
I/O
(7)
Device
XC7A12T
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T
12,800
16,640
23,360
33,280
52,160
75,520
101,440
215,360
40
45
80
90
120
180
240
740
3
5
3
5
5
6
6
10
1
1
1
1
1
1
1
1
2
4
4
4
4
8
8
16
1
1
1
1
1
1
1
1
3
5
3
5
5
6
6
10
150
250
150
250
250
300
300
500
Notes:
7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.
DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an accumulator.
RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18Kb blocks.
CMT contains one MMCM and one PLL.
-7 FPGA Interface Blocks for PCI Express support up to x4 Gen 2.
not include configuration Bank 0.
number does not include GTP transceivers.
Table 5:Artix-7 FPGA Device-Package Combinations and Maximum I/Os
Package
(1)
Size (mm)
Ball Pitch
(mm)
Device
XC7A12T
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T
2
2
106
106
2106
2112
0
0
0
0
210
210
210
210
GTP
(4)
CPG236
10 x 10
0.5
I/O
HR
(5)
CPG238
10 x 10
0.5
GTP
(4)
CSG324
15 x 15
0.8
CSG325
15 x 15
0.8
FTG256
17 x 17
1.0
SBG484
19 x 19
0.8
FGG484
(2)
23 x 23
1.0
FBG484
(2)
23 x 23
1.0
FGG676
(3)
27 x 27
1.0
FBG676
(3)
27 x 27
1.0
FFG1156
35 x 35
1.0
I/O
HR
(5)
GTP
(4)
I/O
HR
(5)
GTP
(4)
I/O
HR
(5)
GTP
(4)
I/O
HR
(5)
GTP
I/O
HR
(5)
GTP
(4)
I/O
HR
(5)
GTP
I/O
HR
(5)
GTP
(4)
I/O
HR
(5)
GTP
I/O
HR
(5)
GTP
I/O
HR
(5)
2112
0210
2
4
4
4
4
150
150
150
150
150
0
0
0
0
170
170
170
170
4285
4
4
4
4
250
250
285
285
4285
8
8
300
300
840016500
01704250
Notes:
packages listed are Pb-free (SBG, FBG, FFG with exemption 15). Some packages are available in Pb option.
s in FGG484 and FBG484 are footprint compatible.
s in FGG676 and FBG676 are footprint compatible.
transceivers in CP, CS, FT, and FG packages support data rates up to 6.25Gb/s.
= High-range I/O with support for I/O voltage from 1.2V to 3.3V.
DS180 (v2.6.1) September 8, 2020
Product Specification
7Series FPGAs Data Sheet: Overview
Kintex-7 FPGA Feature Summary
Table 6:Kintex-7 FPGA Feature Summary by Device
Logic
Cells
Configurable Logic
Blocks (CLBs)
Slices
(1)
10,250
25,350
50,950
55,650
63,550
65,150
74,650
Max
Distributed
RAM (Kb)
838
2,188
4,000
5,088
5,663
5,938
6,788
FBG676
(2)
27 x 27
1.0
I/O
HR
(5)
HP
(6)
185
185
100
100
GTX
(4)
Block RAM Blocks
(3)
DSP
Slices
(2)
CMTs
(4)
18Kb
270
650
890
1,430
1,590
1,670
1,910
36Kb
135
325
445
715
795
835
955
Max (Kb)
4,860
11,700
16,020
25,740
28,620
30,060
34,380
6
8
10
6
10
8
8
FFG900
(3)
31 x 31
1.0
I/O
HR
(5)
HP
(6)
GTX
I/O
HR
(5)
HP
(6)
GTX
1
1
1
1
1
1
1
8
8
16
24
16
32
32
FFG901
31 x 31
1.0
I/O
HR
(5)
HP
(6)
GTX
PCIe
(5)
GTXs
XADC
Blocks
Total I/O
Banks
(6)
Device
Max
User
I/O
(7)
300
400
500
300
500
400
400
XC7K70T
XC7K160T
XC7K325T
XC7K355T
XC7K410T
XC7K420T
XC7K480T
Package
(1)
Size (mm)
Ball Pitch
(mm)
Device
XC7K70T
XC7K160T
XC7K325T
XC7K355T
XC7K410T
XC7K420T
XC7K480T
65,600
162,240
326,080
356,160
406,720
416,960
477,760
FBG484
23 x 23
1.0
GTX
(4)
240
600
840
1,440
1,540
1,680
1,920
1
1
1
1
1
1
1
6
8
10
6
10
8
8
FFG676
(2)
27 x 27
1.0
FBG900
(3)
31 x 31
1.0
FFG1156
35 x 35
1.0
I/O
HR
(5)
HP
(6)
I/O
HR
(5)
HP
(6)
200
250
250
100
150
150
GTX
I/O
HR
(5)
HP
(6)
GTX
(4)
4
4
8
8
8
8
8
250
250
150
1550150
243000
825635
28
28
380
380
0
0
32
32
400
400
0
0
DS180 (v2.6.1) September 8, 2020
Product Specification
7Series FPGAs Data Sheet: Overview
Configurable Logic
Blocks (CLBs)
Slices
(1)
91,050
305,400
51,000
64,400
75,900
86,600
108,300
153,000
178,000
90,700
136,900
Max
Distributed
RAM (Kb)
6,938
21,550
4,388
6,525
8,175
8,725
10,888
13,838
17,700
8,850
13,275
Block RAM Blocks
(3)
DSP
Slices
(2)
CMTs
18Kb36Kb
Max
(Kb)
(4)
Device
Logic
Cells
PCIe
(5)
GTXGTHGTZ
XADC Total I/O
BlocksBanks
(6)
Max
User
I/O
(7)
850
1,200
700
600
700
600
1,000
900
1,100
600
300
SLRs
(8)
XC7V585T
XC7V2000T
XC7VX330T
XC7VX415T
XC7VX485T
XC7VX550T
XC7VX690T
XC7VX980T
XC7VX1140T
XC7VH580T
XC7VH870T
582,720
1,954,560
326,400
412,160
485,760
554,240
693,120
979,200
1,139,200
580,480
876,160
1,260 1,590
2,160 2,584
1,120
2,160
2,800
2,880
3,600
3,600
3,360
1,680
2,520
1,500
1,760
2,060
2,360
2,940
3,000
3,760
1,880
2,820
795 28,620
1,292
750
880
1,030
1,180
1,470
1,500
1,880
940
1,410
46,512
27,000
31,680
37,080
42,480
52,920
54,000
67,680
33,840
50,760
18
24
14
12
14
20
20
18
24
12
18
3
4
2
2
4
2
3
3
4
2
3
36
36
0
0
56
0
0
0
0
0
0
0
0
28
48
0
80
80
72
96
48
72
0
0
0
0
0
0
0
0
0
8
16
1
1
1
1
1
1
1
1
1
1
1
17
24
14
12
14
16
20
18
22
12
6
N/A
4
N/A
N/A
N/A
N/A
N/A
N/A
4
2
3
DS180 (v2.6.1) September 8, 2020
Product Specification
7Series FPGAs Data Sheet: Overview
Package
(1)
Size (mm)
Ball Pitch
Device
XC7V585T
XC7V2000T
XC7VX330T
XC7VX415T
XC7VX485T
XC7VX550T
XC7VX690T
XC7VX980T
XC7VX1140T
0
48
0
0
48
0
48
48
350
350
350
3500
0
64
64
720
720
064720
0
56
0
0
48
0
80
80
600
600
600
600
072480
096480
0
0
24
24
1,000
900
0241,100
240700
FFG1158
35 x 35
1.0
I/O
GTXGTH
HP
(5)
FFG1926
(2)
45 x 45
1.0
I/O
GTXGTH
HP
(5)
FLG1926
(2)
45 x 45
1.0
I/O
GTXGTH
HP
(5)
FFG1927
45 x 45
1.0
I/O
GTXGTH
HP
(5)
FFG1928
(3)
45 x 45
1.0
I/O
GTXGTH
HP
(5)
FLG1928
(3)
45 x 45
1.0
I/O
GTXGTH
HP
(5)
FFG1930
(4)
45 x 45
1.0
I/O
GTXGTH
HP
(5)
FLG1930
(4)
45 x 45
1.0
I/O
GTXGTH
HP
(5)
DS180 (v2.6.1) September 8, 2020
Product Specification
2024年3月25日发(作者：才晴虹)
7Series FPGAs Data Sheet: Overview
DS180 (v2.6.1) September 8, 2020Product Specification
General Description
Xilinx® 7series FPGAs comprise four FPGA families that address the complete range of system requirements, ranging from low cost, small form factor,
cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding
high-performance applications. The 7series FPGAs include:
•Spartan®-7 Family: Optimized for low cost, lowest power, and high
I/O performance. Available in low-cost, very small form-factor
packaging for smallest PCB footprint.
Artix®-7 Family: Optimized for low power applications requiring serial
transceivers and high DSP and logic throughput. Provides the lowest
total bill of materials cost for high-throughput, cost-sensitive
applications.
•Kintex®-7 Family: Optimized for best price-performance with a 2X
improvement compared to previous generation, enabling a new class
of FPGAs.
Virtex®-7 Family: Optimized for highest system performance and
capacity with a 2X improvement in system performance. Highest
capability devices enabled by stacked silicon interconnect (SSI)
technology.
••
Built on a state-of-the-art, high-performance, low-power (HPL), 28nm, high-k metal gate (HKMG) process technology, 7series FPGAs enable an
unparalleled increase in system performance with 2.9Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3TMAC/s DSP, while consuming 50% less
power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs.
Summary of 7Series FPGA Features
•
•
•
•
•
•
Advanced high-performance FPGA logic based on real 6-input look-
up table (LUT) technology configurable as distributed memory.
36Kb dual-port block RAM with built-in FIFO logic for on-chip data
buffering.
High-performance SelectIO™ technology with support for DDR3
interfaces up to 1,866 Mb/s.
High-speed serial connectivity with built-in multi-gigabit transceivers
from 600
Mb/s to max. rates of 6.6Gb/s up to 28.05Gb/s, offering a
special low-power mode, optimized for chip-to-chip interfaces.
A user configurable analog interface (XADC), incorporating dual
12-bit 1MSPS analog-to-digital converters with on-chip thermal and
supply sensors.
DSP slices with 25x18 multiplier, 48-bit accumulator, and pre-adder
for high-performance filtering, including optimized symmetric
coefficient filtering.
•
•
•
•
•
Powerful clock management tiles (CMT), combining phase-locked
loop (PLL) and mixed-mode clock manager (MMCM) blocks for high
precision and low jitter.
Quickly deploy embedded processing with MicroBlaze™ processor.
Integrated block for PCIExpress® (PCIe), for up to x8 Gen3
Endpoint and Root Port designs.
Wide variety of configuration options, including support for
commodity memories, 256-bit AES encryption with HMAC/SHA-256
authentication, and built-in SEU detection and correction.
Low-cost, wire-bond, bare-die flip-chip, and high signal integrity flip-
chip packaging offering easy migration between family members in
the same package. All packages available in Pb-free and selected
packages in Pb option.
Designed for high performance and lowest power with 28nm,
HKMG, HPL process, 1.0V core voltage process technology and
0.9V core voltage option for even lower power.
•
Table 1:7Series Families Comparison
Max. Capability
Logic Cells
Block RAM
(1)
DSP Slices
DSP Performance
(2)
MicroBlaze CPU
(3)
Transceivers
Transceiver Speed
Serial Bandwidth
PCIe Interface
Memory Interface
I/O Pins
I/O Voltage
Package Options
Notes:
1.
2.
3.
Additional memory available in the form of distributed RAM.
Peak DSP performance numbers are based on symmetrical filter implementation.
Peak MicroBlaze CPU performance numbers based on microcontroller preset.
Spartan-7
102K
4.2Mb
160
176 GMAC/s
260 DMIPs
–
–
–
–
800Mb/s
400
1.2V–3.3V
Low-Cost, Wire-Bond
Artix-7
215K
13Mb
740
929GMAC/s
303 DMIPs
16
6.6Gb/s
211Gb/s
x4 Gen2
1,066Mb/s
500
1.2V–3.3V
Low-Cost, Wire-Bond,
Bare-Die Flip-Chip
Kintex-7
478K
34Mb
1,920
2,845GMAC/s
438 DMIPs
32
12.5Gb/s
800Gb/s
x8 Gen2
1,866Mb/s
500
1.2V–3.3V
Bare-Die Flip-Chip and High-
Performance Flip-Chip
Virtex-7
1,955K
68Mb
3,600
5,335GMAC/s
441 DMIPs
96
28.05Gb/s
2,784Gb/s
x8 Gen3
1,866Mb/s
1,200
1.2V–3.3V
Highest Performance
Flip-Chip
DS180 (v2.6.1) September 8, 2020
Product Specification
7Series FPGAs Data Sheet: Overview
Artix-7 FPGA Feature Summary
Table 4:Artix-7 FPGA Feature Summary by Device
Logic
Cells
Configurable Logic Blocks
(CLBs)
Slices
(1)
2,000
2,600
3,650
5,200
8,150
11,800
15,850
33,650
Max
Distributed
RAM (Kb)
171
200
313
400
600
892
1,188
2,888
Block RAM Blocks
(3)
DSP48E1
Slices
(2)
18Kb
40
50
90
100
150
210
270
730
36Kb
20
25
45
50
75
105
135
365
Max
(Kb)
720
900
1,620
1,800
2,700
3,780
4,860
13,140
CMTs
(4)
PCIe
(5)
GTPs
XADC
Blocks
Total I/O
Banks
(6)
Max User
I/O
(7)
Device
XC7A12T
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T
12,800
16,640
23,360
33,280
52,160
75,520
101,440
215,360
40
45
80
90
120
180
240
740
3
5
3
5
5
6
6
10
1
1
1
1
1
1
1
1
2
4
4
4
4
8
8
16
1
1
1
1
1
1
1
1
3
5
3
5
5
6
6
10
150
250
150
250
250
300
300
500
Notes:
7series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.
DSP slice contains a pre-adder, a 25x18 multiplier, an adder, and an accumulator.
RAMs are fundamentally 36Kb in size; each block can also be used as two independent 18Kb blocks.
CMT contains one MMCM and one PLL.
-7 FPGA Interface Blocks for PCI Express support up to x4 Gen 2.
not include configuration Bank 0.
number does not include GTP transceivers.
Table 5:Artix-7 FPGA Device-Package Combinations and Maximum I/Os
Package
(1)
Size (mm)
Ball Pitch
(mm)
Device
XC7A12T
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T
2
2
106
106
2106
2112
0
0
0
0
210
210
210
210
GTP
(4)
CPG236
10 x 10
0.5
I/O
HR
(5)
CPG238
10 x 10
0.5
GTP
(4)
CSG324
15 x 15
0.8
CSG325
15 x 15
0.8
FTG256
17 x 17
1.0
SBG484
19 x 19
0.8
FGG484
(2)
23 x 23
1.0
FBG484
(2)
23 x 23
1.0
FGG676
(3)
27 x 27
1.0
FBG676
(3)
27 x 27
1.0
FFG1156
35 x 35
1.0
I/O
HR
(5)
GTP
(4)
I/O
HR
(5)
GTP
(4)
I/O
HR
(5)
GTP
(4)
I/O
HR
(5)
GTP
I/O
HR
(5)
GTP
(4)
I/O
HR
(5)
GTP
I/O
HR
(5)
GTP
(4)
I/O
HR
(5)
GTP
I/O
HR
(5)
GTP
I/O
HR
(5)
2112
0210
2
4
4
4
4
150
150
150
150
150
0
0
0
0
170
170
170
170
4285
4
4
4
4
250
250
285
285
4285
8
8
300
300
840016500
01704250
Notes:
packages listed are Pb-free (SBG, FBG, FFG with exemption 15). Some packages are available in Pb option.
s in FGG484 and FBG484 are footprint compatible.
s in FGG676 and FBG676 are footprint compatible.
transceivers in CP, CS, FT, and FG packages support data rates up to 6.25Gb/s.
= High-range I/O with support for I/O voltage from 1.2V to 3.3V.
DS180 (v2.6.1) September 8, 2020
Product Specification
7Series FPGAs Data Sheet: Overview
Kintex-7 FPGA Feature Summary
Table 6:Kintex-7 FPGA Feature Summary by Device
Logic
Cells
Configurable Logic
Blocks (CLBs)
Slices
(1)
10,250
25,350
50,950
55,650
63,550
65,150
74,650
Max
Distributed
RAM (Kb)
838
2,188
4,000
5,088
5,663
5,938
6,788
FBG676
(2)
27 x 27
1.0
I/O
HR
(5)
HP
(6)
185
185
100
100
GTX
(4)
Block RAM Blocks
(3)
DSP
Slices
(2)
CMTs
(4)
18Kb
270
650
890
1,430
1,590
1,670
1,910
36Kb
135
325
445
715
795
835
955
Max (Kb)
4,860
11,700
16,020
25,740
28,620
30,060
34,380
6
8
10
6
10
8
8
FFG900
(3)
31 x 31
1.0
I/O
HR
(5)
HP
(6)
GTX
I/O
HR
(5)
HP
(6)
GTX
1
1
1
1
1
1
1
8
8
16
24
16
32
32
FFG901
31 x 31
1.0
I/O
HR
(5)
HP
(6)
GTX
PCIe
(5)
GTXs
XADC
Blocks
Total I/O
Banks
(6)
Device
Max
User
I/O
(7)
300
400
500
300
500
400
400
XC7K70T
XC7K160T
XC7K325T
XC7K355T
XC7K410T
XC7K420T
XC7K480T
Package
(1)
Size (mm)
Ball Pitch
(mm)
Device
XC7K70T
XC7K160T
XC7K325T
XC7K355T
XC7K410T
XC7K420T
XC7K480T
65,600
162,240
326,080
356,160
406,720
416,960
477,760
FBG484
23 x 23
1.0
GTX
(4)
240
600
840
1,440
1,540
1,680
1,920
1
1
1
1
1
1
1
6
8
10
6
10
8
8
FFG676
(2)
27 x 27
1.0
FBG900
(3)
31 x 31
1.0
FFG1156
35 x 35
1.0
I/O
HR
(5)
HP
(6)
I/O
HR
(5)
HP
(6)
200
250
250
100
150
150
GTX
I/O
HR
(5)
HP
(6)
GTX
(4)
4
4
8
8
8
8
8
250
250
150
1550150
243000
825635
28
28
380
380
0
0
32
32
400
400
0
0
DS180 (v2.6.1) September 8, 2020
Product Specification
7Series FPGAs Data Sheet: Overview
Configurable Logic
Blocks (CLBs)
Slices
(1)
91,050
305,400
51,000
64,400
75,900
86,600
108,300
153,000
178,000
90,700
136,900
Max
Distributed
RAM (Kb)
6,938
21,550
4,388
6,525
8,175
8,725
10,888
13,838
17,700
8,850
13,275
Block RAM Blocks
(3)
DSP
Slices
(2)
CMTs
18Kb36Kb
Max
(Kb)
(4)
Device
Logic
Cells
PCIe
(5)
GTXGTHGTZ
XADC Total I/O
BlocksBanks
(6)
Max
User
I/O
(7)
850
1,200
700
600
700
600
1,000
900
1,100
600
300
SLRs
(8)
XC7V585T
XC7V2000T
XC7VX330T
XC7VX415T
XC7VX485T
XC7VX550T
XC7VX690T
XC7VX980T
XC7VX1140T
XC7VH580T
XC7VH870T
582,720
1,954,560
326,400
412,160
485,760
554,240
693,120
979,200
1,139,200
580,480
876,160
1,260 1,590
2,160 2,584
1,120
2,160
2,800
2,880
3,600
3,600
3,360
1,680
2,520
1,500
1,760
2,060
2,360
2,940
3,000
3,760
1,880
2,820
795 28,620
1,292
750
880
1,030
1,180
1,470
1,500
1,880
940
1,410
46,512
27,000
31,680
37,080
42,480
52,920
54,000
67,680
33,840
50,760
18
24
14
12
14
20
20
18
24
12
18
3
4
2
2
4
2
3
3
4
2
3
36
36
0
0
56
0
0
0
0
0
0
0
0
28
48
0
80
80
72
96
48
72
0
0
0
0
0
0
0
0
0
8
16
1
1
1
1
1
1
1
1
1
1
1
17
24
14
12
14
16
20
18
22
12
6
N/A
4
N/A
N/A
N/A
N/A
N/A
N/A
4
2
3
DS180 (v2.6.1) September 8, 2020
Product Specification
7Series FPGAs Data Sheet: Overview
Package
(1)
Size (mm)
Ball Pitch
Device
XC7V585T
XC7V2000T
XC7VX330T
XC7VX415T
XC7VX485T
XC7VX550T
XC7VX690T
XC7VX980T
XC7VX1140T
0
48
0
0
48
0
48
48
350
350
350
3500
0
64
64
720
720
064720
0
56
0
0
48
0
80
80
600
600
600
600
072480
096480
0
0
24
24
1,000
900
0241,100
240700
FFG1158
35 x 35
1.0
I/O
GTXGTH
HP
(5)
FFG1926
(2)
45 x 45
1.0
I/O
GTXGTH
HP
(5)
FLG1926
(2)
45 x 45
1.0
I/O
GTXGTH
HP
(5)
FFG1927
45 x 45
1.0
I/O
GTXGTH
HP
(5)
FFG1928
(3)
45 x 45
1.0
I/O
GTXGTH
HP
(5)
FLG1928
(3)
45 x 45
1.0
I/O
GTXGTH
HP
(5)
FFG1930
(4)
45 x 45
1.0
I/O
GTXGTH
HP
(5)
FLG1930
(4)
45 x 45
1.0
I/O
GTXGTH
HP
(5)
DS180 (v2.6.1) September 8, 2020
Product Specification