FPGA可编程逻辑器件芯片XC2S15-5FG256C中文规格书-USB迷|专注于互联网分享

2024年4月6日发(作者：朋听荷)

Spartan-3 FPGA Family: Functional Description

The product of w and n yields the total block RAM capacity. Equation1 and Equation2 show that as the data bus width

increases, the number of address lines along with the number of addressable memory locations decreases. Using the

permissible DI/DO bus widths as inputs to these equations provides the bus width and memory capacity measures shown

in Table14.

Table 14:Port Aspect Ratios for Port A or B

DI/DO Bus Width

(w – p Bits)

DIP/DOP

Bus Width (p Bits)

Total Data Path

Width (w Bits)

ADDR Bus Width

(r Bits)

No. of Addressable Block RAM

Locations (n)Capacity (Bits)

16,384

8,192

4,096

2,048

1,024

512

16,384

18,432

Block RAM Data Operations

Writing data to and accessing data from the block RAM are synchronous operations that take place independently on each

of the two ports.

The waveforms for the write operation are shown in the top half of the Figure15, Figure16, and Figure17. When the WE

and EN signals enable the active edge of CLK, data at the DI input bus is written to the block RAM location addressed by the

ADDR lines.

There are a number of different conditions under which data can be accessed at the DO outputs. Basic data access always

occurs when the WE input is inactive. Under this condition, data stored in the memory location addressed by the ADDR lines

passes through a transparent output latch to the DO outputs. The timing for basic data access is shown in the portions of

Figure15, Figure16, and Figure17 during which WE is Low.

CLK

ADDR

XXXX11112222XXXX

aabbccdd

0000MEM(aa)11112222MEM(dd)

DISABLEDREAD

WRITE

MEM(bb)=1111

WRITE

MEM(cc)=2222

READ

DS099-2_14_091410

Figure 15:Waveforms of Block RAM Data Operations with WRITE_FIRST Selected

Data can also be accessed on the DO outputs when asserting the WE input. This is accomplished using two different

attributes:

Choosing the WRITE_FIRST attribute, data is written to the addressed memory location on an enabled active CLK edge and

is also passed to the DO outputs. WRITE_FIRST timing is shown in the portion of Figure15 during which WE is High.

Choosing the READ_FIRST attribute, data already stored in the addressed location pass to the DO outputs before that

location is overwritten with new data from the DI inputs on an enabled active CLK edge. READ_FIRST timing is shown in the

portion of Figure16 during which WE is High.

DS099 (v3.1) June 27, 2013

Product Specification

Spartan-3 FPGA Family: Functional Description

The DLL component has two clock inputs, CLKIN and CLKFB, as well as seven clock outputs, CLK0, CLK90, CLK180,

CLK270, CLK2X, CLK2X180, and CLKDV as described in Table16. The clock outputs drive simultaneously; however, the

High Frequency mode only supports a subset of the outputs available in the Low Frequency mode. See DLL Frequency

Modes, page35. Signals that initialize and report the state of the DLL are discussed in The Status Logic Component,

page41.

Table 16:DLL Signals

Mode Support

Signal

CLKIN

CLKFB

CLK0

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

Direction

Input

Output

Accepts original clock signal.

Description

Low

Frequency

Yes

High

Frequency

Yes

Accepts either CLK0 or CLK2X as feed back signal. (Set CLK_FEEDBACK

attribute accordingly).

Generates clock signal with same frequency and phase as CLKIN.

Generates clock signal with same frequency as CLKIN, only phase-shifted 90°.

Generates clock signal with same frequency as CLKIN, only phase-shifted 180°.

Generates clock signal with same frequency as CLKIN, only phase-shifted 270°.

Generates clock signal with same phase as CLKIN, only twice the frequency.

Generates clock signal with twice the frequency of CLKIN, phase-shifted 180°

with respect to CLKIN.

Divides the CLKIN frequency by CLKDV_DIVIDE value to generate lower

frequency clock signal that is phase-aligned to CLKIN.

The clock signal supplied to the CLKIN input serves as a reference waveform, with which the DLL seeks to align the

feedback signal at the CLKFB input. When eliminating clock skew, the common approach to using the DLL is as follows: The

CLK0 signal is passed through the clock distribution network to all the registers it synchronizes. These registers are either

internal or external to the FPGA. After passing through the clock distribution network, the clock signal returns to the DLL via

a feedback line called CLKFB. The control block inside the DLL measures the phase error between CLKFB and CLKIN. This

phase error is a measure of the clock skew that the clock distribution network introduces. The control block activates the

appropriate number of delay elements to cancel out the clock skew. Once the DLL has brought the CLK0 signal in phase with

the CLKIN signal, it asserts the LOCKED output, indicating a “lock” on to the CLKIN signal.

DLL Attributes and Related Functions

A number of different functional options can be set for the DLL component through the use of the attributes described in

Table17. Each attribute is described in detail in the sections that follow:

Table 17:DLL Attributes

Attribute

CLK_FEEDBACK

DLL_FREQUENCY_MODE

CLKIN_DIVIDE_BY_2

CLKDV_DIVIDE

Description

Chooses between High Frequency and Low Frequency modes

Halves the frequency of the CLKIN signal just as it enters the DCM

Selects constant used to divide the CLKIN input frequency to

generate the CLKDV output frequency

Enables 50% duty cycle correction for the CLK0, CLK90, CLK180,

and CLK270 outputs

Values

LOW, HIGH

TRUE, FALSE

1.5, 2, 2.5, 3, 3.5, 4, 4.5,

5, 5.5, 6.0, 6.5, 7.0, 7.5,

8, 9, 10, 11, 12, 13, 14,

15, and 16.

TRUE, FALSE

Chooses either the CLK0 or CLK2X output to drive the CLKFB inputNONE, 1X, 2X

DUTY_CYCLE_CORRECTION