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FPGA可编程逻辑器件芯片XC4VLX60-11FF668C中文规格书

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2024年4月6日发(作者:次云岚)

DS302 (v3.7) September 9, 2009

00

Product Specification

Virtex-4 FPGA Electrical Characteristics

Virtex®-4 FPGAs are available in -12, -11, and -10 speed

grades, with -12 having the highest performance.

Virtex-4 FPGA DC and AC characteristics are specified for

both commercial and industrial grades. Except the operat-

ing temperature range or unless otherwise noted, all the DC

and AC electrical parameters are the same for a particular

speed grade (that is, the timing characteristics of a -10

speed grade industrial device are the same as for a -10

speed grade commercial device). However, only selected

speed grades and/or devices might be available in the

industrial range.

All supply voltage and junction temperature specifications

are representative of worst-case conditions. The parame-

ters included are common to popular designs and typical

applications.

This Virtex-4 FPGA Data Sheet is part of an overall set of

documentation on the Virtex-4 family of FPGAs that is avail-

able on the Xilinx website:

Virtex-4 Family Overview, DS112

Virtex-4 FPGA User Guide, UG070

Virtex-4 FPGA Configuration Guide, UG071

XtremeDSP for Virtex-4 FPGAs User Guide, UG073

Virtex-4 FPGA Packaging and Pinout Specification,

UG075

Virtex-4 FPGA PCB Designer’s Guide, UG072

Virtex-4 RocketIO™ Multi-Gigabit Transceiver User

Guide, UG076

Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC

User Guide, UG074

PowerPC® 405 Processor Block Reference Guide,

UG018

All specifications are subject to change without notice.

Virtex-4 FPGA DC Characteristics

Table 1: Absolute Maximum Ratings

Symbol

V

CCINT

V

CCAUX

V

CCO

V

BATT

V

REF

Description

Internal supply voltage relative to GND

Auxiliary supply voltage relative to GND

Output drivers supply voltage relative to GND

Key memory battery backup supply

Input reference voltage

I/O input voltage relative to GND

(all user and dedicated I/Os)

–0.5 to 1.32

–0.5 to 3.0

–0.5 to 3.75

–0.5 to 4.05

–0.3 to 3.75

–0.75 to 4.05

–0.95 to 4.4

(Commercial Temperature)

Units

V

V

V

V

V

V

V

IN

I/O input voltage relative to GND

(restricted to maximum of 100 user I/Os)

(3,4)

2.5V or below I/O input voltage relative to GND

(user and dedicated I/Os)

–0.85 to 4.3

(Industrial Temperature)

V

–0.75 to V

CCO

+0.5

±100

±200

V

mA

mA

I

IN

Current applied to an I/O pin, powered or unpowered

Total current applied to all I/O pins, powered or unpowered

DS302 (v3.7) September 9, 2009

Product Specification

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Speed Grade

Description

Clock Synthesis Period Jitter

CLK0

CLK90

CLK180

CLK270

CLK2X, CLK2X180

CLKDV (integer division)

CLKDV (non-integer division)

CLKFX, CLKFX180

CLKOUT_PER_JITT_0

CLKOUT_PER_JITT_90

CLKOUT_PER_JITT_180

CLKOUT_PER_JITT_270

CLKOUT_PER_JITT_2X

CLKOUT_PER_JITT_DV1

CLKOUT_PER_JITT_DV2

CLKOUT_PER_JITT_FX

±100

±150

±150

±150

±200

±150

±300

Note (2)

±100

±150

±150

±150

±200

±150

±300

Note (2)

±100

±150

±150

±150

±200

±150

±300

Note (2)

ps

ps

ps

ps

ps

ps

ps

ps

SymbolConstraints-12-11-10Units

DS302 (v3.7) September 9, 2009

Product Specification

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Table 50: Miscellaneous Timing Parameters

Speed Grade

Symbol

Time Required to Achieve LOCK

T_LOCK_DLL_240

T_LOCK_DLL_120_240

T_LOCK_DLL_60_120

T_LOCK_DLL_50_60

T_LOCK_DLL_40_50

T_LOCK_DLL_30_40

T_LOCK_DLL_24_30

T_LOCK_DLL_30

T_LOCK_FX_MAX

T_LOCK_DLL_FINE_SHIFT

Fine Phase Shifting

FINE_SHIFT_RANGE_MS

FINE_SHIFT_RANGE_MR

Delay Lines

DCM_TAP_MS_MIN

DCM_TAP_MS_MAX

DCM_TAP_MR_MIN

DCM_TAP_MR_MAX

Input Signal Requirements

DCM_RESET

(4)

DCM_INPUT_CLOCK_STOP

Minimum duration that RST must be held asserted

Maximum duration that RST can be held asserted

(5)

Maximum duration that CLKIN and CLKFB can be

stopped

(6,7)

Tap delay resolution (Min) in maximum speed mode

Tap delay resolution (Max) in maximum speed mode

Tap delay resolution (Min) in maximum range mode

Tap delay resolution (Max) in maximum range mode

5

40

10

60

5

40

10

60

5

40

10

60

ps

ps

ps

ps

Absolute shifting range in maximum speed mode

Absolute shifting range in maximum range mode

7

10

7

10

7

10

ns

ns

DLL output – Frequency range > 240MHz

(2)

DLL output – Frequency range 120 - 240MHz

(1,2)

DLL output – Frequency range 60 - 120MHz

(1,2)

DLL output – Frequency range 50 - 60MHz

(1,2)

DLL output – Frequency range 40 - 50MHz

(1,2)

DLL output – Frequency range 30 - 40MHz

(1,2)

DLL output – Frequency range 24 - 30MHz

(1,2)

DLL output – Frequency range < 30MHz

(2)

DFS outputs

(3)

Multiplication factor for DLL lock time with Fine Shift

20

63

225

325

500

900

1250

1250

10

2

20

63

225

325

500

900

1250

1250

10

2

20

63

225

325

500

900

1250

1250

10

2

µs

µs

µs

µs

µs

µs

µs

µs

ms

Description-12-11-10Units

200

10

100

200

10

100

200

10

100

ms

sec

ms

Notes:

boundary frequencies, choose the higher delay.

Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.

Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.

must be present and stable during the DCM_RESET.

only applies to production step 1 LX and SX devices. For these devices, use the design solutions described in Answer Record 21127 for support

of longer reset durations. Production step 2 LX and SX devices and all production FX devices do not have this requirement.

production step 1 LX and SX devices, use the design solutions described in Answer Record 21127 for support of longer durations of stopped

clocks. For production step 2 LX and SX devices and all production FX devices, the ISE software automatically inserts a small macro to support

longer durations of stopped clocks.

all stepping levels, once the input clock is toggling again and stable after being stopped, DCM must be reset.

DS302 (v3.7) September 9, 2009

Product Specification

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Speed Grade

-12

2.43

2.60

2.54

2.69

2.88

2.94

2.94

N/A

2.65

2.81

2.83

2.43

2.54

2.87

2.92

3.16

N/A

SymbolDescriptionDevice

-11

2.81

2.95

2.91

3.05

3.27

3.33

3.35

3.51

2.99

3.18

3.20

2.78

2.88

3.25

3.31

3.58

3.79

-10

3.25

3.36

3.32

3.45

3.72

3.79

3.82

4.02

3.39

3.60

3.62

3.18

3.26

3.67

3.77

4.06

4.30

Units

LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM.

T

ICKOFDCM

Global Clock and OFF with DCMXC4VLX15

XC4VLX25

XC4VLX40

XC4VLX60

XC4VLX80

XC4VLX100

XC4VLX160

XC4VLX200

XC4VSX25

XC4VSX35

XC4VSX55

XC4VFX12

XC4VFX20

XC4VFX40

XC4VFX60

XC4VFX100

XC4VFX140

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

DS302 (v3.7) September 9, 2009

Product Specification

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Table 61: Sample Window

Symbol

T

SAMP

T

SAMP_BUFIO

Description

Sampling Error at Receiver Pins

(1)

Sampling Error at Receiver Pins using BUFIO

(2)

Device

All

All

Speed Grade

-12

450

350

-11

500

400

-10

550

450

Units

ps

ps

SymbolDescription

Speed Grade

-12

–0.45

0.97

-11

–0.45

1.08

-10

–0.44

1.17

Units

Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO

T

PSCS

/T

PHCS

Setup/Hold of I/O clock across multiple clock regionsns

Pin-to-Pin Clock-to-Out Using BUFIO

T

ICKOFCS

Clock-to-Out of I/O clock across multiple clock regions4.104.545.02ns

DS302 (v3.7) September 9, 2009

Product Specification

2024年4月6日发(作者:次云岚)

DS302 (v3.7) September 9, 2009

00

Product Specification

Virtex-4 FPGA Electrical Characteristics

Virtex®-4 FPGAs are available in -12, -11, and -10 speed

grades, with -12 having the highest performance.

Virtex-4 FPGA DC and AC characteristics are specified for

both commercial and industrial grades. Except the operat-

ing temperature range or unless otherwise noted, all the DC

and AC electrical parameters are the same for a particular

speed grade (that is, the timing characteristics of a -10

speed grade industrial device are the same as for a -10

speed grade commercial device). However, only selected

speed grades and/or devices might be available in the

industrial range.

All supply voltage and junction temperature specifications

are representative of worst-case conditions. The parame-

ters included are common to popular designs and typical

applications.

This Virtex-4 FPGA Data Sheet is part of an overall set of

documentation on the Virtex-4 family of FPGAs that is avail-

able on the Xilinx website:

Virtex-4 Family Overview, DS112

Virtex-4 FPGA User Guide, UG070

Virtex-4 FPGA Configuration Guide, UG071

XtremeDSP for Virtex-4 FPGAs User Guide, UG073

Virtex-4 FPGA Packaging and Pinout Specification,

UG075

Virtex-4 FPGA PCB Designer’s Guide, UG072

Virtex-4 RocketIO™ Multi-Gigabit Transceiver User

Guide, UG076

Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC

User Guide, UG074

PowerPC® 405 Processor Block Reference Guide,

UG018

All specifications are subject to change without notice.

Virtex-4 FPGA DC Characteristics

Table 1: Absolute Maximum Ratings

Symbol

V

CCINT

V

CCAUX

V

CCO

V

BATT

V

REF

Description

Internal supply voltage relative to GND

Auxiliary supply voltage relative to GND

Output drivers supply voltage relative to GND

Key memory battery backup supply

Input reference voltage

I/O input voltage relative to GND

(all user and dedicated I/Os)

–0.5 to 1.32

–0.5 to 3.0

–0.5 to 3.75

–0.5 to 4.05

–0.3 to 3.75

–0.75 to 4.05

–0.95 to 4.4

(Commercial Temperature)

Units

V

V

V

V

V

V

V

IN

I/O input voltage relative to GND

(restricted to maximum of 100 user I/Os)

(3,4)

2.5V or below I/O input voltage relative to GND

(user and dedicated I/Os)

–0.85 to 4.3

(Industrial Temperature)

V

–0.75 to V

CCO

+0.5

±100

±200

V

mA

mA

I

IN

Current applied to an I/O pin, powered or unpowered

Total current applied to all I/O pins, powered or unpowered

DS302 (v3.7) September 9, 2009

Product Specification

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Speed Grade

Description

Clock Synthesis Period Jitter

CLK0

CLK90

CLK180

CLK270

CLK2X, CLK2X180

CLKDV (integer division)

CLKDV (non-integer division)

CLKFX, CLKFX180

CLKOUT_PER_JITT_0

CLKOUT_PER_JITT_90

CLKOUT_PER_JITT_180

CLKOUT_PER_JITT_270

CLKOUT_PER_JITT_2X

CLKOUT_PER_JITT_DV1

CLKOUT_PER_JITT_DV2

CLKOUT_PER_JITT_FX

±100

±150

±150

±150

±200

±150

±300

Note (2)

±100

±150

±150

±150

±200

±150

±300

Note (2)

±100

±150

±150

±150

±200

±150

±300

Note (2)

ps

ps

ps

ps

ps

ps

ps

ps

SymbolConstraints-12-11-10Units

DS302 (v3.7) September 9, 2009

Product Specification

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Table 50: Miscellaneous Timing Parameters

Speed Grade

Symbol

Time Required to Achieve LOCK

T_LOCK_DLL_240

T_LOCK_DLL_120_240

T_LOCK_DLL_60_120

T_LOCK_DLL_50_60

T_LOCK_DLL_40_50

T_LOCK_DLL_30_40

T_LOCK_DLL_24_30

T_LOCK_DLL_30

T_LOCK_FX_MAX

T_LOCK_DLL_FINE_SHIFT

Fine Phase Shifting

FINE_SHIFT_RANGE_MS

FINE_SHIFT_RANGE_MR

Delay Lines

DCM_TAP_MS_MIN

DCM_TAP_MS_MAX

DCM_TAP_MR_MIN

DCM_TAP_MR_MAX

Input Signal Requirements

DCM_RESET

(4)

DCM_INPUT_CLOCK_STOP

Minimum duration that RST must be held asserted

Maximum duration that RST can be held asserted

(5)

Maximum duration that CLKIN and CLKFB can be

stopped

(6,7)

Tap delay resolution (Min) in maximum speed mode

Tap delay resolution (Max) in maximum speed mode

Tap delay resolution (Min) in maximum range mode

Tap delay resolution (Max) in maximum range mode

5

40

10

60

5

40

10

60

5

40

10

60

ps

ps

ps

ps

Absolute shifting range in maximum speed mode

Absolute shifting range in maximum range mode

7

10

7

10

7

10

ns

ns

DLL output – Frequency range > 240MHz

(2)

DLL output – Frequency range 120 - 240MHz

(1,2)

DLL output – Frequency range 60 - 120MHz

(1,2)

DLL output – Frequency range 50 - 60MHz

(1,2)

DLL output – Frequency range 40 - 50MHz

(1,2)

DLL output – Frequency range 30 - 40MHz

(1,2)

DLL output – Frequency range 24 - 30MHz

(1,2)

DLL output – Frequency range < 30MHz

(2)

DFS outputs

(3)

Multiplication factor for DLL lock time with Fine Shift

20

63

225

325

500

900

1250

1250

10

2

20

63

225

325

500

900

1250

1250

10

2

20

63

225

325

500

900

1250

1250

10

2

µs

µs

µs

µs

µs

µs

µs

µs

ms

Description-12-11-10Units

200

10

100

200

10

100

200

10

100

ms

sec

ms

Notes:

boundary frequencies, choose the higher delay.

Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.

Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.

must be present and stable during the DCM_RESET.

only applies to production step 1 LX and SX devices. For these devices, use the design solutions described in Answer Record 21127 for support

of longer reset durations. Production step 2 LX and SX devices and all production FX devices do not have this requirement.

production step 1 LX and SX devices, use the design solutions described in Answer Record 21127 for support of longer durations of stopped

clocks. For production step 2 LX and SX devices and all production FX devices, the ISE software automatically inserts a small macro to support

longer durations of stopped clocks.

all stepping levels, once the input clock is toggling again and stable after being stopped, DCM must be reset.

DS302 (v3.7) September 9, 2009

Product Specification

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Speed Grade

-12

2.43

2.60

2.54

2.69

2.88

2.94

2.94

N/A

2.65

2.81

2.83

2.43

2.54

2.87

2.92

3.16

N/A

SymbolDescriptionDevice

-11

2.81

2.95

2.91

3.05

3.27

3.33

3.35

3.51

2.99

3.18

3.20

2.78

2.88

3.25

3.31

3.58

3.79

-10

3.25

3.36

3.32

3.45

3.72

3.79

3.82

4.02

3.39

3.60

3.62

3.18

3.26

3.67

3.77

4.06

4.30

Units

LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM.

T

ICKOFDCM

Global Clock and OFF with DCMXC4VLX15

XC4VLX25

XC4VLX40

XC4VLX60

XC4VLX80

XC4VLX100

XC4VLX160

XC4VLX200

XC4VSX25

XC4VSX35

XC4VSX55

XC4VFX12

XC4VFX20

XC4VFX40

XC4VFX60

XC4VFX100

XC4VFX140

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

DS302 (v3.7) September 9, 2009

Product Specification

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics

Table 61: Sample Window

Symbol

T

SAMP

T

SAMP_BUFIO

Description

Sampling Error at Receiver Pins

(1)

Sampling Error at Receiver Pins using BUFIO

(2)

Device

All

All

Speed Grade

-12

450

350

-11

500

400

-10

550

450

Units

ps

ps

SymbolDescription

Speed Grade

-12

–0.45

0.97

-11

–0.45

1.08

-10

–0.44

1.17

Units

Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO

T

PSCS

/T

PHCS

Setup/Hold of I/O clock across multiple clock regionsns

Pin-to-Pin Clock-to-Out Using BUFIO

T

ICKOFCS

Clock-to-Out of I/O clock across multiple clock regions4.104.545.02ns

DS302 (v3.7) September 9, 2009

Product Specification

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