2024年4月7日发(作者：卢乐芸)
Configuration
Spartan-3 devices are configured by loading application specific configuration data into the internal configuration memory.
Configuration is carried out using a subset of the device pins, some of which are "Dedicated" to one function only, while
others, indicated by the term "Dual-Purpose", can be re-used as general-purpose User I/Os once configuration is complete.
Depending on the system design, several configuration modes are supported, selectable via mode pins. The mode pins M0,
M1, and M2 are Dedicated pins. The mode pin settings are shown in Table26.
Table 26:Spartan-3 FPGAs Configuration Mode Pin Settings
Configuration Mode
(1)
Master Serial
Slave Serial
Master Parallel
Slave Parallel
JTAG
Notes:
1.
2.
The voltage levels on the M0, M1, and M2 pins select the configuration mode.
The daisy chain is possible only in the Serial modes when DOUT is used.
M0
0
1
1
0
1
M1
0
1
1
1
0
M2
0
1
0
1
1
Synchronizing Clock
CCLK Output
CCLK Input
CCLK Output
CCLK Input
TCKInput
Data Width
1
1
8
8
1
Serial DOUT
(2)
Yes
Yes
No
No
No
The HSWAP_EN input pin defines whether the I/O pins that are not actively used during configuration have pull-up resistors
during configuration. By default, HSWAP_EN is tied High (via an internal pull-up resistor if left floating) which shuts off the
pull-up resistors on the user I/O pins during configuration. When HSWAP_EN is tied Low, user I/Os have pull-ups during
configuration. The Dedicated configuration pins (CCLK, DONE, PROG_B, M2, M1, M0, HSWAP_EN) and the JTAG pins
(TDI, TMS, TCK, and TDO) always have a pull-up resistor to VCCAUX during configuration, regardless of the value on the
HSWAP_EN pin. Similarly, the dual-purpose INIT_B pin has an internal pull-up resistor to VCCO_4 or VCCO_BOTTOM,
depending on the package style.
Depending on the chosen configuration mode, the FPGA either generates a CCLK output, or CCLK is an input accepting an
externally generated clock.
A persist option is available which can be used to force the configuration pins to retain their configuration function even after
device configuration is complete. If the persist option is not selected then the configuration pins with the exception of CCLK,
PROG_B, and DONE can be used as user I/O in normal operation. The persist option does not apply to the boundary-scan
related pins. The persist feature is valuable in applications that readback configuration data after entering the User mode.
Table27 lists the total number of bits required to configure each FPGA as well as the PROMs suitable for storing those bits.
See DS123
: Platform Flash In-System Programmable Configuration PROMs data sheet for more information.
Table 27:Spartan-3 FPGA Configuration Data
Device
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
File Sizes
439,264
1,047,616
1,699,136
3,223,488
5,214,784
7,673,024
11,316,864
13,271,936
Xilinx Platform Flash PROM
Serial Configuration
XCF01S
XCF01S
XCF02S
XCF04S
XCF08P
XCF08P
XCF16P
XCF16P
Parallel Configuration
XCF08P
XCF08P
XCF08P
XCF08P
XCF08P
XCF08P
XCF16P
XCF16P
DS099 (v3.1) June 27, 2013
Product Specification
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013
Product Specification
2024年4月7日发(作者：卢乐芸)
Configuration
Spartan-3 devices are configured by loading application specific configuration data into the internal configuration memory.
Configuration is carried out using a subset of the device pins, some of which are "Dedicated" to one function only, while
others, indicated by the term "Dual-Purpose", can be re-used as general-purpose User I/Os once configuration is complete.
Depending on the system design, several configuration modes are supported, selectable via mode pins. The mode pins M0,
M1, and M2 are Dedicated pins. The mode pin settings are shown in Table26.
Table 26:Spartan-3 FPGAs Configuration Mode Pin Settings
Configuration Mode
(1)
Master Serial
Slave Serial
Master Parallel
Slave Parallel
JTAG
Notes:
1.
2.
The voltage levels on the M0, M1, and M2 pins select the configuration mode.
The daisy chain is possible only in the Serial modes when DOUT is used.
M0
0
1
1
0
1
M1
0
1
1
1
0
M2
0
1
0
1
1
Synchronizing Clock
CCLK Output
CCLK Input
CCLK Output
CCLK Input
TCKInput
Data Width
1
1
8
8
1
Serial DOUT
(2)
Yes
Yes
No
No
No
The HSWAP_EN input pin defines whether the I/O pins that are not actively used during configuration have pull-up resistors
during configuration. By default, HSWAP_EN is tied High (via an internal pull-up resistor if left floating) which shuts off the
pull-up resistors on the user I/O pins during configuration. When HSWAP_EN is tied Low, user I/Os have pull-ups during
configuration. The Dedicated configuration pins (CCLK, DONE, PROG_B, M2, M1, M0, HSWAP_EN) and the JTAG pins
(TDI, TMS, TCK, and TDO) always have a pull-up resistor to VCCAUX during configuration, regardless of the value on the
HSWAP_EN pin. Similarly, the dual-purpose INIT_B pin has an internal pull-up resistor to VCCO_4 or VCCO_BOTTOM,
depending on the package style.
Depending on the chosen configuration mode, the FPGA either generates a CCLK output, or CCLK is an input accepting an
externally generated clock.
A persist option is available which can be used to force the configuration pins to retain their configuration function even after
device configuration is complete. If the persist option is not selected then the configuration pins with the exception of CCLK,
PROG_B, and DONE can be used as user I/O in normal operation. The persist option does not apply to the boundary-scan
related pins. The persist feature is valuable in applications that readback configuration data after entering the User mode.
Table27 lists the total number of bits required to configure each FPGA as well as the PROMs suitable for storing those bits.
See DS123
: Platform Flash In-System Programmable Configuration PROMs data sheet for more information.
Table 27:Spartan-3 FPGA Configuration Data
Device
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
File Sizes
439,264
1,047,616
1,699,136
3,223,488
5,214,784
7,673,024
11,316,864
13,271,936
Xilinx Platform Flash PROM
Serial Configuration
XCF01S
XCF01S
XCF02S
XCF04S
XCF08P
XCF08P
XCF16P
XCF16P
Parallel Configuration
XCF08P
XCF08P
XCF08P
XCF08P
XCF08P
XCF08P
XCF16P
XCF16P
DS099 (v3.1) June 27, 2013
Product Specification
Spartan-3 FPGA Family: Functional Description
DS099 (v3.1) June 27, 2013
Product Specification