2024年4月7日发(作者：富察萧玉)
DS183 (v1.27) April 6, 2017Product Specification
Introduction
Virtex®-7 T and XT FPGAs are available in -3, -2, -1, and
-2L speed grades, with -3 having the highest performance.
The -2L devices operate at V
CCINT
=1.0V and are screened
for lower maximum static power. The speed specification of
a -2L device is the same as the -2 speed grade. The -2G
speed grade is available in devices utilizing Stacked Silicon
Interconnect (SSI) technology. The -2G speed grade
supports 12.5Gb/s GTX or 13.1Gb/s GTH transceivers as
well as the standard -2 speed grade specifications.
Virtex-7TandXT FPGA DC and AC characteristics are
specified in commercial, extended, industrial, and military
temperature ranges. Except for the operating temperature
range or unless otherwise noted, all the DC and AC electrical
parameters are the same for a particular speed grade (that
is, the timing characteristics of a -1M speed grade military
device are the same as for a -1C speed grade commercial
device). However, only selected speed grades and/or
devices are available in each temperature range.
All supply voltage and junction temperature specifications
are representative of worst-case conditions. The parameters
included are common to popular designs and typical
applications.
Available device and package combinations can be found in:
•
•
7Series FPGAs Overview (DS180
)
Defense-Grade 7Series FPGAs Overview (DS185
)
This Virtex-7 T and XT FPGA data sheet, part of an overall
set of documentation on the 7 series FPGAs, is available
on the Xilinx website .
DC Characteristics
Table 1:Absolute Maximum Ratings
(1)
Symbol
FPGA Logic
V
CCINT
V
CCAUX
V
CCBRAM
V
CCO
V
CCAUX_IO
V
REF
Internal supply voltage
Auxiliary supply voltage
Supply voltage for the block RAM memories
Output drivers supply voltage for 3.3V HR I/O banks
Output drivers supply voltage for 1.8V HP I/O banks
Auxiliary supply voltage
Input reference voltage
I/O input voltage for 3.3V HR I/O banks
V
IN
(2)(3)(4)
I/O input voltage for 1.8V HP I/O banks
I/O input voltage (when V
CCO
=3.3V) for V
REF
and differential I/O standards except
TMDS_33
(5)
Key memory battery backup supply
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.40
–0.55
–0.40
–0.5
1.1
2.0
1.1
3.6
2.0
2.06
2.0
V
CCO
+0.55
V
CCO
+0.55
2.625
2.0
V
V
V
V
V
V
V
V
V
V
V
DescriptionMinMaxUnits
V
CCBATT
V
MGTAVCC
V
MGTAVTT
V
MGTVCCAUX
V
MGTREFCLK
GTX and GTH Transceivers
Analog supply voltage for the GTX/GTH transmitter and receiver circuits
Analog supply voltage for the GTX/GTH transmitter and receiver termination circuits
Auxiliary analog Quad PLL (QPLL) voltage supply for the GTX/GTH transceivers
GTX/GTH transceiver reference clock absolute input voltage
–0.5
–0.5
–0.5
–0.5
1.1
1.32
1.935
1.32
V
V
V
V
DS183 (v1.27) April 6, 2017
Product Specification
Virtex-7TandXT FPGAs Data Sheet: DC and AC Switching Characteristics
GTX Transceiver Protocol Jitter Characteristics
For Table62 through Table67, the 7Series FPGAs GTX/GTH Transceiver User Guide (UG476) contains recommended settings
for optimal usage of protocol specific characteristics.
Table 62:Gigabit Ethernet Protocol Characteristics (GTX Transceivers)
Description
Gigabit Ethernet Transmitter Jitter Generation
Total transmitter jitter (T_TJ)1250–0.24UI
Line Rate (Mb/s)MinMaxUnits
Gigabit Ethernet Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance12500.749–UI
Table 63:XAUI Protocol Characteristics (GTX Transceivers)
Description
XAUI Transmitter Jitter Generation
Total transmitter jitter (T_TJ)3125–0.35UI
Line Rate (Mb/s)MinMaxUnits
XAUI Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance31250.65–UI
Table 64:PCI Express Protocol Characteristics (GTX Transceivers)
(1)
Standard
PCI Express Transmitter Jitter Generation
PCI Express Gen 1
PCI Express Gen 2
PCI Express Gen 3
Total transmitter jitter
Total transmitter jitter
Total transmitter jitter uncorrelated
Deterministic transmitter jitter uncorrelated
2500
5000
8000
–
–
–
–
0.25
0.25
31.25
12
UI
UI
ps
ps
DescriptionLine Rate (Mb/s)MinMaxUnits
PCI Express Receiver High Frequency Jitter Tolerance
PCI Express Gen 1
PCI Express Gen 2
(2)
Total receiver jitter tolerance
Receiver inherent timing error
Receiver inherent deterministic timing error
0.03MHz–1.0MHz
PCI Express Gen 3
Receiver sinusoidal jitter
1.0MHz–10MHz
tolerance
10MHz–100MHz
8000
2500
5000
0.65
0.40
0.30
1.00
Note3
0.10
–
–
–
–
–
–
UI
UI
UI
UI
UI
UI
Notes:
1.
2.
3.
Tested per card electromechanical(CEM)methodology.
Using common REFCLK.
Between 1MHz and 10MHz the minimum sinusoidal jitter roll-off with a slope of 20dB/decade.
DS183 (v1.27) April 6, 2017
Product Specification
Virtex-7TandXT FPGAs Data Sheet: DC and AC Switching Characteristics
Table 65:CEI-6G and CEI-11G Protocol Characteristics (GTX Transceivers)
DescriptionLine Rate (Mb/s)
CEI-6G-SR
CEI-6G-LR
InterfaceMin
–
–
Max
0.3
0.3
Units
UI
UI
CEI-6G Transmitter Jitter Generation
Total transmitter jitter
(1)
4976–6375
CEI-6G Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance
(1)
4976–6375
CEI-6G-SR
CEI-6G-LR
0.6
0.95
–
–
UI
UI
CEI-11G Transmitter Jitter Generation
Total transmitter jitter
(2)
9950–11100
CEI-11G-SR
CEI-11G-LR/MR
–
–
0.3
0.3
UI
UI
CEI-11G Receiver High Frequency Jitter Tolerance
CEI-11G-SR
Total receiver jitter tolerance
(2)
9950–11100CEI-11G-MR
CEI-11G-LR
Notes:
1.
2.
Tested at most commonly used line rate of 6250Mb/s using 390.625MHz reference clock.
Tested at line rate of 9950Mb/s using 155.46875MHz reference clock and 11100Mb/s using 173.4375MHz reference clock.
0.65
0.65
0.825
–
–
–
UI
UI
UI
Table 66:SFP+ Protocol Characteristics (GTX Transceivers)
Description
SFP+ Transmitter Jitter Generation
9830.40
(1)
9953.00
Total transmitter jitter10312.50
10518.75
11100.00
–0.28UI
Line Rate (Mb/s)MinMaxUnits
SFP+ Receiver Frequency Jitter Tolerance
9830.40
(1)
9953.00
Total receiver jitter tolerance10312.50
10518.75
11100.00
Notes:
rated used for CPRI over SFP+ applications.
0.7–UI
DS183 (v1.27) April 6, 2017
Product Specification
Virtex-7TandXT FPGAs Data Sheet: DC and AC Switching Characteristics
Table 67:CPRI Protocol Characteristics (GTX Transceivers)
Description
CPRI Transmitter Jitter Generation
614.4
1228.8
2457.6
–
–
–
0.35
0.35
0.35
UI
UI
UI
Line Rate (Mb/s)MinMaxUnits
DS183 (v1.27) April 6, 2017
Product Specification
Virtex-7TandXT FPGAs Data Sheet: DC and AC Switching Characteristics
GTH Transceiver Specifications
GTH Transceiver DC Input and Output Levels
Table68 summarizes the DC specifications of the GTH transceivers in Virtex-7TandXT FPGAs. Consult the 7Series FPGAs
GTX/GTH Transceiver User Guide (UG476
) for further details.
Table 68:GTH Transceiver DC Specifications
Symbol
DV
PPIN
DC Parameter
Differential peak-to-peak input
voltage (external AC coupled)
Conditions
>10.3125Gb/s
6.6Gb/s to 10.3125Gb/s
≤6.6Gb/s
DC coupled
V
MGTAVTT
=1.2V
DC coupled
V
MGTAVTT
=1.2V
Min
150
150
150
–400
–
800
Typ
–
–
–
–
2/3 V
MGTAVTT
–
Max
1250
1250
2000
V
MGTAVTT
–
–
Units
mV
mV
mV
mV
mV
mV
mV
mV
V
IN
V
CMIN
DV
PPOUT
V
CMOUTDC
V
CMOUTAC
R
IN
R
OUT
T
OSKEW
C
EXT
Notes:
1.
2.
3.
Single-ended input voltage
(1)
Common mode input voltage
Differential peak-to-peak output Transmitter output swing is set to
voltage
(2)
1010
Common mode output voltage: Equation based
DC coupled
Common mode output voltage: Equation based
AC coupled
Differential input resistance
Differential output resistance
Transmitter output pair (TXP and TXN) intra-pair skew
Recommended external AC coupling capacitor
(3)
V
MGTAVTT
–DV
PPOUT
/4
V
MGTAVTT
–DV
PPOUT
/2
–
–
–
–
100
100
–
100
–
–
10
–
Ω
Ω
ps
nF
Voltage measured at the pin referenced to ground.
The output swing and preemphasis levels are programmable using the attributes discussed in the 7Series FPGAs GTX/GTH Transceiver
User Guide (UG476), and can result in values lower than reported in this table.
Other values can be used as appropriate to conform to specific protocols and standards.
+VP
Single-Ended
Peak-to-Peak
Voltage
ds183_01_062414
N
0
Figure 6:Single-Ended Peak-to-Peak Voltage
DS183 (v1.27) April 6, 2017
Product Specification
2024年4月7日发(作者：富察萧玉)
DS183 (v1.27) April 6, 2017Product Specification
Introduction
Virtex®-7 T and XT FPGAs are available in -3, -2, -1, and
-2L speed grades, with -3 having the highest performance.
The -2L devices operate at V
CCINT
=1.0V and are screened
for lower maximum static power. The speed specification of
a -2L device is the same as the -2 speed grade. The -2G
speed grade is available in devices utilizing Stacked Silicon
Interconnect (SSI) technology. The -2G speed grade
supports 12.5Gb/s GTX or 13.1Gb/s GTH transceivers as
well as the standard -2 speed grade specifications.
Virtex-7TandXT FPGA DC and AC characteristics are
specified in commercial, extended, industrial, and military
temperature ranges. Except for the operating temperature
range or unless otherwise noted, all the DC and AC electrical
parameters are the same for a particular speed grade (that
is, the timing characteristics of a -1M speed grade military
device are the same as for a -1C speed grade commercial
device). However, only selected speed grades and/or
devices are available in each temperature range.
All supply voltage and junction temperature specifications
are representative of worst-case conditions. The parameters
included are common to popular designs and typical
applications.
Available device and package combinations can be found in:
•
•
7Series FPGAs Overview (DS180
)
Defense-Grade 7Series FPGAs Overview (DS185
)
This Virtex-7 T and XT FPGA data sheet, part of an overall
set of documentation on the 7 series FPGAs, is available
on the Xilinx website .
DC Characteristics
Table 1:Absolute Maximum Ratings
(1)
Symbol
FPGA Logic
V
CCINT
V
CCAUX
V
CCBRAM
V
CCO
V
CCAUX_IO
V
REF
Internal supply voltage
Auxiliary supply voltage
Supply voltage for the block RAM memories
Output drivers supply voltage for 3.3V HR I/O banks
Output drivers supply voltage for 1.8V HP I/O banks
Auxiliary supply voltage
Input reference voltage
I/O input voltage for 3.3V HR I/O banks
V
IN
(2)(3)(4)
I/O input voltage for 1.8V HP I/O banks
I/O input voltage (when V
CCO
=3.3V) for V
REF
and differential I/O standards except
TMDS_33
(5)
Key memory battery backup supply
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–0.40
–0.55
–0.40
–0.5
1.1
2.0
1.1
3.6
2.0
2.06
2.0
V
CCO
+0.55
V
CCO
+0.55
2.625
2.0
V
V
V
V
V
V
V
V
V
V
V
DescriptionMinMaxUnits
V
CCBATT
V
MGTAVCC
V
MGTAVTT
V
MGTVCCAUX
V
MGTREFCLK
GTX and GTH Transceivers
Analog supply voltage for the GTX/GTH transmitter and receiver circuits
Analog supply voltage for the GTX/GTH transmitter and receiver termination circuits
Auxiliary analog Quad PLL (QPLL) voltage supply for the GTX/GTH transceivers
GTX/GTH transceiver reference clock absolute input voltage
–0.5
–0.5
–0.5
–0.5
1.1
1.32
1.935
1.32
V
V
V
V
DS183 (v1.27) April 6, 2017
Product Specification
Virtex-7TandXT FPGAs Data Sheet: DC and AC Switching Characteristics
GTX Transceiver Protocol Jitter Characteristics
For Table62 through Table67, the 7Series FPGAs GTX/GTH Transceiver User Guide (UG476) contains recommended settings
for optimal usage of protocol specific characteristics.
Table 62:Gigabit Ethernet Protocol Characteristics (GTX Transceivers)
Description
Gigabit Ethernet Transmitter Jitter Generation
Total transmitter jitter (T_TJ)1250–0.24UI
Line Rate (Mb/s)MinMaxUnits
Gigabit Ethernet Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance12500.749–UI
Table 63:XAUI Protocol Characteristics (GTX Transceivers)
Description
XAUI Transmitter Jitter Generation
Total transmitter jitter (T_TJ)3125–0.35UI
Line Rate (Mb/s)MinMaxUnits
XAUI Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance31250.65–UI
Table 64:PCI Express Protocol Characteristics (GTX Transceivers)
(1)
Standard
PCI Express Transmitter Jitter Generation
PCI Express Gen 1
PCI Express Gen 2
PCI Express Gen 3
Total transmitter jitter
Total transmitter jitter
Total transmitter jitter uncorrelated
Deterministic transmitter jitter uncorrelated
2500
5000
8000
–
–
–
–
0.25
0.25
31.25
12
UI
UI
ps
ps
DescriptionLine Rate (Mb/s)MinMaxUnits
PCI Express Receiver High Frequency Jitter Tolerance
PCI Express Gen 1
PCI Express Gen 2
(2)
Total receiver jitter tolerance
Receiver inherent timing error
Receiver inherent deterministic timing error
0.03MHz–1.0MHz
PCI Express Gen 3
Receiver sinusoidal jitter
1.0MHz–10MHz
tolerance
10MHz–100MHz
8000
2500
5000
0.65
0.40
0.30
1.00
Note3
0.10
–
–
–
–
–
–
UI
UI
UI
UI
UI
UI
Notes:
1.
2.
3.
Tested per card electromechanical(CEM)methodology.
Using common REFCLK.
Between 1MHz and 10MHz the minimum sinusoidal jitter roll-off with a slope of 20dB/decade.
DS183 (v1.27) April 6, 2017
Product Specification
Virtex-7TandXT FPGAs Data Sheet: DC and AC Switching Characteristics
Table 65:CEI-6G and CEI-11G Protocol Characteristics (GTX Transceivers)
DescriptionLine Rate (Mb/s)
CEI-6G-SR
CEI-6G-LR
InterfaceMin
–
–
Max
0.3
0.3
Units
UI
UI
CEI-6G Transmitter Jitter Generation
Total transmitter jitter
(1)
4976–6375
CEI-6G Receiver High Frequency Jitter Tolerance
Total receiver jitter tolerance
(1)
4976–6375
CEI-6G-SR
CEI-6G-LR
0.6
0.95
–
–
UI
UI
CEI-11G Transmitter Jitter Generation
Total transmitter jitter
(2)
9950–11100
CEI-11G-SR
CEI-11G-LR/MR
–
–
0.3
0.3
UI
UI
CEI-11G Receiver High Frequency Jitter Tolerance
CEI-11G-SR
Total receiver jitter tolerance
(2)
9950–11100CEI-11G-MR
CEI-11G-LR
Notes:
1.
2.
Tested at most commonly used line rate of 6250Mb/s using 390.625MHz reference clock.
Tested at line rate of 9950Mb/s using 155.46875MHz reference clock and 11100Mb/s using 173.4375MHz reference clock.
0.65
0.65
0.825
–
–
–
UI
UI
UI
Table 66:SFP+ Protocol Characteristics (GTX Transceivers)
Description
SFP+ Transmitter Jitter Generation
9830.40
(1)
9953.00
Total transmitter jitter10312.50
10518.75
11100.00
–0.28UI
Line Rate (Mb/s)MinMaxUnits
SFP+ Receiver Frequency Jitter Tolerance
9830.40
(1)
9953.00
Total receiver jitter tolerance10312.50
10518.75
11100.00
Notes:
rated used for CPRI over SFP+ applications.
0.7–UI
DS183 (v1.27) April 6, 2017
Product Specification
Virtex-7TandXT FPGAs Data Sheet: DC and AC Switching Characteristics
Table 67:CPRI Protocol Characteristics (GTX Transceivers)
Description
CPRI Transmitter Jitter Generation
614.4
1228.8
2457.6
–
–
–
0.35
0.35
0.35
UI
UI
UI
Line Rate (Mb/s)MinMaxUnits
DS183 (v1.27) April 6, 2017
Product Specification
Virtex-7TandXT FPGAs Data Sheet: DC and AC Switching Characteristics
GTH Transceiver Specifications
GTH Transceiver DC Input and Output Levels
Table68 summarizes the DC specifications of the GTH transceivers in Virtex-7TandXT FPGAs. Consult the 7Series FPGAs
GTX/GTH Transceiver User Guide (UG476
) for further details.
Table 68:GTH Transceiver DC Specifications
Symbol
DV
PPIN
DC Parameter
Differential peak-to-peak input
voltage (external AC coupled)
Conditions
>10.3125Gb/s
6.6Gb/s to 10.3125Gb/s
≤6.6Gb/s
DC coupled
V
MGTAVTT
=1.2V
DC coupled
V
MGTAVTT
=1.2V
Min
150
150
150
–400
–
800
Typ
–
–
–
–
2/3 V
MGTAVTT
–
Max
1250
1250
2000
V
MGTAVTT
–
–
Units
mV
mV
mV
mV
mV
mV
mV
mV
V
IN
V
CMIN
DV
PPOUT
V
CMOUTDC
V
CMOUTAC
R
IN
R
OUT
T
OSKEW
C
EXT
Notes:
1.
2.
3.
Single-ended input voltage
(1)
Common mode input voltage
Differential peak-to-peak output Transmitter output swing is set to
voltage
(2)
1010
Common mode output voltage: Equation based
DC coupled
Common mode output voltage: Equation based
AC coupled
Differential input resistance
Differential output resistance
Transmitter output pair (TXP and TXN) intra-pair skew
Recommended external AC coupling capacitor
(3)
V
MGTAVTT
–DV
PPOUT
/4
V
MGTAVTT
–DV
PPOUT
/2
–
–
–
–
100
100
–
100
–
–
10
–
Ω
Ω
ps
nF
Voltage measured at the pin referenced to ground.
The output swing and preemphasis levels are programmable using the attributes discussed in the 7Series FPGAs GTX/GTH Transceiver
User Guide (UG476), and can result in values lower than reported in this table.
Other values can be used as appropriate to conform to specific protocols and standards.
+VP
Single-Ended
Peak-to-Peak
Voltage
ds183_01_062414
N
0
Figure 6:Single-Ended Peak-to-Peak Voltage
DS183 (v1.27) April 6, 2017
Product Specification