2024年4月26日发(作者：遇帆)
Spartan-3 FPGA Family: Pinout Descriptions
CCLK: Configuration Clock
The configuration clock signal on this pin synchronizes the reading or writing of configuration data. The CCLK pin is an
input-only pin for the Slave Serial and Slave Parallel configuration modes. In the Master Serial and Master Parallel
configuration modes, the FPGA drives the CCLK pin and CCLK should be treated as a full bidirectional I/O pin for signal
integrity analysis.
Although the CCLK frequency is relatively low, Spartan-3 FPGA output edge rates are fast. Any potential signal integrity
problems on the CCLK board trace can cause FPGA configuration to fail. Therefore, pay careful attention to the CCLK signal
integrity on the printed circuit board. Signal integrity simulation with IBIS is recommended. For all configuration modes
except JTAG, consider the signal integrity at every CCLK trace destination, including the FPGA’s CCLK pin. For more details
on CCLK design considerations, see Chapter 2 of UG332
, Spartan-3 Generation Configuration User Guide.
During configuration, the CCLK pin has a pull-up resistor to VCCAUX, regardless of the HSWAP_EN pin. After configuration,
the CCLK pin is pulled High to VCCAUX by default as defined by the CclkPin bitstream selection, although this behavior is
programmable. Any clocks applied to CCLK after configuration are ignored unless the bitstream option Persist is set to Yes,
which retains the configuration interface. Persist is set to No by default. However, if Persist is set to Yes, then all clock
edges are potentially active events, depending on the other configuration control signals.
The bitstream generator option ConfigRate determines the frequency of the internally-generated CCLK oscillator required
for the Master configuration modes. The actual frequency is approximate due to the characteristics of the silicon oscillator
and varies by up to 50% over the temperature and voltage range. By default, CCLK operates at approximately 6 MHz. Via
the ConfigRate option, the oscillator frequency is set at approximately 3, 6, 12, 25, or 50 MHz. At power-on, CCLK always
starts operation at its lowest frequency. The device does not start operating at the higher frequency until the ConfigRate
control bits are loaded during the configuration process.
PROG_B: Program/Configure Device
This asynchronous pin initiates the configuration or re-configuration processes. A Low-going pulse resets the configuration
logic, initializing the configuration memory. This initialization process cannot finish until PROG_B returns High. Asserting
PROG_B Low for an extended period delays the configuration process. At power-up, there is always a pull-up resistor to
VCCAUX on this pin, regardless of the HSWAP_EN input. After configuration, the bitstream generator option ProgPin
determines whether or not the pull-up resistor is present. By default, the ProgPin option retains the pull-up resistor.
After configuration, hold the PROG_B input High. Any Low-going pulse on PROG_B lasting 300ns or longer restarts the
configuration process.
Table 73:PROG_B Operation
PROG_B Input
Power-up
Low-going pulse
Automatically initiates configuration process.
Initiate (re-)configuration process and continue to completion.
Initiate (re-)configuration process and stall process at step where configuration memory is cleared. Process is
stalled until PROG_B returns High.
If the configuration process is started, continue to completion. If configuration process is complete, stay in User
mode.
Response
Extended Low
1
DONE: Configuration Done, Delay Start-Up Sequence
The FPGA produces a Low-to-High transition on this pin indicating that the configuration process is complete. The bitstream
generator option DriveDone determines whether this pin functions as a totem-pole output that can drive High or as an
open-drain output. If configured as an open-drain output—which is the default behavior—then a pull-up resistor is required
to produce a High logic level. There is a bitstream option that provides an internal pull-up resistor, otherwise an external
pull-up resistor is required.
The open-drain option permits the DONE lines of multiple FPGAs to be tied together, so that the common node transitions
High only after all of the FPGAs have completed configuration. Externally holding the open-drain DONE pin Low delays the
start-up sequence, which marks the transition to user mode.
DS099 (v3.1) June 27, 2013
Product Specification
Spartan-3 FPGA Family: Pinout Descriptions
Package Thermal Characteristics
The power dissipated by an FPGA application has implications on package selection and system design. The power
consumed by a Spartan-3 FPGA is reported using either the XPower
Estimator (XPE) or the XPower Analyzer integrated in
the Xilinx ISE development software. Table86 provides the thermal characteristics for the various Spartan-3 device/package
offerings.
The junction-to-case thermal resistance (θ
JC
) indicates the difference between the temperature measured on the package
body (case) and the die junction temperature per watt of power consumption. The junction-to-board (θ
JB
) value similarly
reports the difference between the board and junction temperature. The junction-to-ambient (θ
JA
) value reports the
temperature difference per watt between the ambient environment and the junction temperature. The θ
JA
value is reported
at different air velocities, measured in linear feet per minute (LFM). The “Still Air (0 LFM)” column shows the θ
JA
value in a
system without a fan. The thermal resistance drops with increasing air flow.
Table 86:Spartan-3 FPGA Package Thermal Characteristics
PackageDevice
XC3S50
XC3S200
XC3S50
XC3S50
TQ(G)144XC3S200
XC3S400
XC3S50
PQ(G)208XC3S200
XC3S400
XC3S200
FT(G)256XC3S400
XC3S1000
XC3S400
FG(G)320XC3S1000
XC3S1500
XC3S400
FG(G)456
XC3S1000
XC3S1500
XC3S2000
XC3S1000
XC3S1500
FG(G)676XC3S2000
XC3S4000
XC3S5000
XC3S2000
FG(G)900XC3S4000
XC3S5000
Junction-to-
Case (θ
JC
)
12.0
10.0
14.5
7.6
6.6
6.1
10.6
8.6
7.5
9.9
7.9
5.6
8.9
7.8
6.7
8.4
6.4
4.9
3.7
6.0
4.9
4.1
3.6
3.4
3.7
3.3
2.9
Junction-to-B
oard (θ
JB
)
–
–
32.8
–
–
–
–
–
–
22.9
19.0
14.7
13.9
11.8
9.8
13.6
10.6
8.3
6.5
10.4
8.8
7.9
7.0
6.3
7.0
6.4
5.9
Junction-to-Ambient (θ
JA
) at Different Air Flows
Still Air
(0 LFM)
46.2
40.5
53.0
41.0
34.5
32.8
37.4
36.2
35.4
31.7
28.4
24.8
24.4
22.3
20.3
20.8
19.3
18.3
17.7
17.9
16.8
15.6
15.0
14.7
14.3
13.6
13.1
250 LFM
38.4
33.7
46.4
31.9
26.9
25.5
27.6
26.7
26.1
25.6
22.8
19.2
19.0
17.0
15.18
15.1
13.4
12.4
11.7
13.7
12.4
11.1
10.5
10.3
10.3
9.7
9.2
500 LFM
35.8
31.3
44.0
27.2
23.0
21.8
24.4
23.6
23.1
24.5
21.5
18.0
17.8
15.8
13.8
13.9
12.3
11.2
10.5
12.6
11.3
9.9
9.3
9.1
9.3
8.7
8.1
750 LFM
34.9
30.5
42.5
25.6
21.6
20.4
22.6
21.9
21.4
24.2
21.0
17.5
17.0
15.0
13.1
13.4
11.7
10.7
10.0
12.0
10.7
9.3
8.7
8.5
8.8
8.2
7.6
Units
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
VQ(G)100
CP(G)132
(1)
DS099 (v3.1) June 27, 2013
Product Specification
2024年4月26日发(作者：遇帆)
Spartan-3 FPGA Family: Pinout Descriptions
CCLK: Configuration Clock
The configuration clock signal on this pin synchronizes the reading or writing of configuration data. The CCLK pin is an
input-only pin for the Slave Serial and Slave Parallel configuration modes. In the Master Serial and Master Parallel
configuration modes, the FPGA drives the CCLK pin and CCLK should be treated as a full bidirectional I/O pin for signal
integrity analysis.
Although the CCLK frequency is relatively low, Spartan-3 FPGA output edge rates are fast. Any potential signal integrity
problems on the CCLK board trace can cause FPGA configuration to fail. Therefore, pay careful attention to the CCLK signal
integrity on the printed circuit board. Signal integrity simulation with IBIS is recommended. For all configuration modes
except JTAG, consider the signal integrity at every CCLK trace destination, including the FPGA’s CCLK pin. For more details
on CCLK design considerations, see Chapter 2 of UG332
, Spartan-3 Generation Configuration User Guide.
During configuration, the CCLK pin has a pull-up resistor to VCCAUX, regardless of the HSWAP_EN pin. After configuration,
the CCLK pin is pulled High to VCCAUX by default as defined by the CclkPin bitstream selection, although this behavior is
programmable. Any clocks applied to CCLK after configuration are ignored unless the bitstream option Persist is set to Yes,
which retains the configuration interface. Persist is set to No by default. However, if Persist is set to Yes, then all clock
edges are potentially active events, depending on the other configuration control signals.
The bitstream generator option ConfigRate determines the frequency of the internally-generated CCLK oscillator required
for the Master configuration modes. The actual frequency is approximate due to the characteristics of the silicon oscillator
and varies by up to 50% over the temperature and voltage range. By default, CCLK operates at approximately 6 MHz. Via
the ConfigRate option, the oscillator frequency is set at approximately 3, 6, 12, 25, or 50 MHz. At power-on, CCLK always
starts operation at its lowest frequency. The device does not start operating at the higher frequency until the ConfigRate
control bits are loaded during the configuration process.
PROG_B: Program/Configure Device
This asynchronous pin initiates the configuration or re-configuration processes. A Low-going pulse resets the configuration
logic, initializing the configuration memory. This initialization process cannot finish until PROG_B returns High. Asserting
PROG_B Low for an extended period delays the configuration process. At power-up, there is always a pull-up resistor to
VCCAUX on this pin, regardless of the HSWAP_EN input. After configuration, the bitstream generator option ProgPin
determines whether or not the pull-up resistor is present. By default, the ProgPin option retains the pull-up resistor.
After configuration, hold the PROG_B input High. Any Low-going pulse on PROG_B lasting 300ns or longer restarts the
configuration process.
Table 73:PROG_B Operation
PROG_B Input
Power-up
Low-going pulse
Automatically initiates configuration process.
Initiate (re-)configuration process and continue to completion.
Initiate (re-)configuration process and stall process at step where configuration memory is cleared. Process is
stalled until PROG_B returns High.
If the configuration process is started, continue to completion. If configuration process is complete, stay in User
mode.
Response
Extended Low
1
DONE: Configuration Done, Delay Start-Up Sequence
The FPGA produces a Low-to-High transition on this pin indicating that the configuration process is complete. The bitstream
generator option DriveDone determines whether this pin functions as a totem-pole output that can drive High or as an
open-drain output. If configured as an open-drain output—which is the default behavior—then a pull-up resistor is required
to produce a High logic level. There is a bitstream option that provides an internal pull-up resistor, otherwise an external
pull-up resistor is required.
The open-drain option permits the DONE lines of multiple FPGAs to be tied together, so that the common node transitions
High only after all of the FPGAs have completed configuration. Externally holding the open-drain DONE pin Low delays the
start-up sequence, which marks the transition to user mode.
DS099 (v3.1) June 27, 2013
Product Specification
Spartan-3 FPGA Family: Pinout Descriptions
Package Thermal Characteristics
The power dissipated by an FPGA application has implications on package selection and system design. The power
consumed by a Spartan-3 FPGA is reported using either the XPower
Estimator (XPE) or the XPower Analyzer integrated in
the Xilinx ISE development software. Table86 provides the thermal characteristics for the various Spartan-3 device/package
offerings.
The junction-to-case thermal resistance (θ
JC
) indicates the difference between the temperature measured on the package
body (case) and the die junction temperature per watt of power consumption. The junction-to-board (θ
JB
) value similarly
reports the difference between the board and junction temperature. The junction-to-ambient (θ
JA
) value reports the
temperature difference per watt between the ambient environment and the junction temperature. The θ
JA
value is reported
at different air velocities, measured in linear feet per minute (LFM). The “Still Air (0 LFM)” column shows the θ
JA
value in a
system without a fan. The thermal resistance drops with increasing air flow.
Table 86:Spartan-3 FPGA Package Thermal Characteristics
PackageDevice
XC3S50
XC3S200
XC3S50
XC3S50
TQ(G)144XC3S200
XC3S400
XC3S50
PQ(G)208XC3S200
XC3S400
XC3S200
FT(G)256XC3S400
XC3S1000
XC3S400
FG(G)320XC3S1000
XC3S1500
XC3S400
FG(G)456
XC3S1000
XC3S1500
XC3S2000
XC3S1000
XC3S1500
FG(G)676XC3S2000
XC3S4000
XC3S5000
XC3S2000
FG(G)900XC3S4000
XC3S5000
Junction-to-
Case (θ
JC
)
12.0
10.0
14.5
7.6
6.6
6.1
10.6
8.6
7.5
9.9
7.9
5.6
8.9
7.8
6.7
8.4
6.4
4.9
3.7
6.0
4.9
4.1
3.6
3.4
3.7
3.3
2.9
Junction-to-B
oard (θ
JB
)
–
–
32.8
–
–
–
–
–
–
22.9
19.0
14.7
13.9
11.8
9.8
13.6
10.6
8.3
6.5
10.4
8.8
7.9
7.0
6.3
7.0
6.4
5.9
Junction-to-Ambient (θ
JA
) at Different Air Flows
Still Air
(0 LFM)
46.2
40.5
53.0
41.0
34.5
32.8
37.4
36.2
35.4
31.7
28.4
24.8
24.4
22.3
20.3
20.8
19.3
18.3
17.7
17.9
16.8
15.6
15.0
14.7
14.3
13.6
13.1
250 LFM
38.4
33.7
46.4
31.9
26.9
25.5
27.6
26.7
26.1
25.6
22.8
19.2
19.0
17.0
15.18
15.1
13.4
12.4
11.7
13.7
12.4
11.1
10.5
10.3
10.3
9.7
9.2
500 LFM
35.8
31.3
44.0
27.2
23.0
21.8
24.4
23.6
23.1
24.5
21.5
18.0
17.8
15.8
13.8
13.9
12.3
11.2
10.5
12.6
11.3
9.9
9.3
9.1
9.3
8.7
8.1
750 LFM
34.9
30.5
42.5
25.6
21.6
20.4
22.6
21.9
21.4
24.2
21.0
17.5
17.0
15.0
13.1
13.4
11.7
10.7
10.0
12.0
10.7
9.3
8.7
8.5
8.8
8.2
7.6
Units
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
°C/Watt
VQ(G)100
CP(G)132
(1)
DS099 (v3.1) June 27, 2013
Product Specification