2024年4月29日发(作者：公羊芳春)
EI
A/
JEDEC Standard 51-3
Page 1
Low Effective Thermal Conductivity Test
Board
for Leaded Surface Mount Packages
(F
rom JEDEC Council Ballot JCB-95-40
,
formulated under the cognizance of JC-15.1
Committee on Thermal Characterization T echniques for Electronic Packages and Interconnects.)
1
1.
1
1.
2
1.
3
1.
4
Background
The measurement of the Junction-to-
Am
bient (8 J
A>
thermal characteristics of an
integrated circuit
(I
C) package has historically been carried out using a number oftest
fixturing methods. The most prominent fixturing method is the soldering of the packaged
devices to a printed circuit board
σCB).
The characteristics ofthe test PCB's can have a
dramatic (>60%) impact on the measured
8JA Due to this wide variability
,
it is desirable
to have an industry wide standard for the design ofPCB test boards to
minin也e
discrepancies in measured values between companies.
To obtain consistent measurements
of8JA企om
one company to the next
,
the test PCB
geometry and trace layout must be completely specified for each package geometry tested.
Such a complete specification would limit the flexibility
ofuser companies who would like
to design test boards for their individual needs. Thus
,
one characteristic of a test board
specification
is to allow some variability ofPCB test board design while minirnizing
measurement
v缸iability.
This specification should be used in conjunction with the electrical test procedures
described in JEDEC Standard No. 51-1
,
"In
tegrated Circuit Thermal Measurement
Method -Electrical Test Method (Single Semiconductor Device)
,"
[1]
,
and JEDEC
Standard No. 51-2
,
"Integrated Circuit Thermal Test Method Environmental Conditions-
Natural Convection (Still
Ai
r)
,"
[2].
References
[1] JEDEC Standard No.
51-1，吁ntegrated
Circuit Thermal Measurement Method -
Electrical Test Method (Single Semiconductor Device)."
[2] JEDEC Standard No.
51-2，吨ntegrated
Circuit Thermal T est Method
Environmental Conditions -Natural Convection (Still
Air)."
[3] Surface Mount Land Pattems (Configurations and Design Rules)
,
Pub. No.
ANS盯IPC-SM-782
(782A)
,
Developed by the
Insti阳te
for
In
terconnecting
and Packaging Electronic Circuits
,
1987.
2024年4月29日发(作者：公羊芳春)
EI
A/
JEDEC Standard 51-3
Page 1
Low Effective Thermal Conductivity Test
Board
for Leaded Surface Mount Packages
(F
rom JEDEC Council Ballot JCB-95-40
,
formulated under the cognizance of JC-15.1
Committee on Thermal Characterization T echniques for Electronic Packages and Interconnects.)
1
1.
1
1.
2
1.
3
1.
4
Background
The measurement of the Junction-to-
Am
bient (8 J
A>
thermal characteristics of an
integrated circuit
(I
C) package has historically been carried out using a number oftest
fixturing methods. The most prominent fixturing method is the soldering of the packaged
devices to a printed circuit board
σCB).
The characteristics ofthe test PCB's can have a
dramatic (>60%) impact on the measured
8JA Due to this wide variability
,
it is desirable
to have an industry wide standard for the design ofPCB test boards to
minin也e
discrepancies in measured values between companies.
To obtain consistent measurements
of8JA企om
one company to the next
,
the test PCB
geometry and trace layout must be completely specified for each package geometry tested.
Such a complete specification would limit the flexibility
ofuser companies who would like
to design test boards for their individual needs. Thus
,
one characteristic of a test board
specification
is to allow some variability ofPCB test board design while minirnizing
measurement
v缸iability.
This specification should be used in conjunction with the electrical test procedures
described in JEDEC Standard No. 51-1
,
"In
tegrated Circuit Thermal Measurement
Method -Electrical Test Method (Single Semiconductor Device)
,"
[1]
,
and JEDEC
Standard No. 51-2
,
"Integrated Circuit Thermal Test Method Environmental Conditions-
Natural Convection (Still
Ai
r)
,"
[2].
References
[1] JEDEC Standard No.
51-1，吁ntegrated
Circuit Thermal Measurement Method -
Electrical Test Method (Single Semiconductor Device)."
[2] JEDEC Standard No.
51-2，吨ntegrated
Circuit Thermal T est Method
Environmental Conditions -Natural Convection (Still
Air)."
[3] Surface Mount Land Pattems (Configurations and Design Rules)
,
Pub. No.
ANS盯IPC-SM-782
(782A)
,
Developed by the
Insti阳te
for
In
terconnecting
and Packaging Electronic Circuits
,
1987.