2024年5月9日发(作者：伏妙之)
专利内容由知识产权出版社提供
专利名称：Data strobe device
发明人：EJIMA NAOKI,江島 直樹
申请号：JP特願昭62-9302
申请日：19870119
公开号：JP第2661026号B2
公开日：19971008
摘要：PURPOSE:To stabilize the data strobing of an input signal in 'I' pattern by
obtaining a data for strobing from a suitable tap of a delay means that generates T/2
pulses, and punching out at the edge of a recovered clock. CONSTITUTION:8-10
modulation signals Sa are supplied to a T/2 pulse generation circuit 2, and signals S1, S2
are delayed and outputted from taps 1 and 2. An EX-OR circuit 202 supplies such a signal
Sc that comes to an 'H' level only for a time equal to the time difference between the
signal S1 and the signal S2 to a phase comparator circuit 3. This time duration is equal to
the T/2, and the phase locked loop is established for the circuit 3. A clock signal Sd
generated at this time is delayed from the signal S1 by a length of T/4, while the signal Sa
shifts forward for a length of T/4, therefore, Sa is shifted from the Sd by T/2, and thus
comes to be an optimum timing is attained. Accordingly, in an FF10, the data strobing is
executed by punching out with the signals Sa, Sd.
申请人：MATSUSHITA DENKI SANGYO KK,松下電器産業株式会社
地址：大阪府門真市大字門真1006番地
国籍：JP
代理人：滝本 智之
更多信息请下载全文后查看
2024年5月9日发(作者：伏妙之)
专利内容由知识产权出版社提供
专利名称：Data strobe device
发明人：EJIMA NAOKI,江島 直樹
申请号：JP特願昭62-9302
申请日：19870119
公开号：JP第2661026号B2
公开日：19971008
摘要：PURPOSE:To stabilize the data strobing of an input signal in 'I' pattern by
obtaining a data for strobing from a suitable tap of a delay means that generates T/2
pulses, and punching out at the edge of a recovered clock. CONSTITUTION:8-10
modulation signals Sa are supplied to a T/2 pulse generation circuit 2, and signals S1, S2
are delayed and outputted from taps 1 and 2. An EX-OR circuit 202 supplies such a signal
Sc that comes to an 'H' level only for a time equal to the time difference between the
signal S1 and the signal S2 to a phase comparator circuit 3. This time duration is equal to
the T/2, and the phase locked loop is established for the circuit 3. A clock signal Sd
generated at this time is delayed from the signal S1 by a length of T/4, while the signal Sa
shifts forward for a length of T/4, therefore, Sa is shifted from the Sd by T/2, and thus
comes to be an optimum timing is attained. Accordingly, in an FF10, the data strobing is
executed by punching out with the signals Sa, Sd.
申请人：MATSUSHITA DENKI SANGYO KK,松下電器産業株式会社
地址：大阪府門真市大字門真1006番地
国籍：JP
代理人：滝本 智之
更多信息请下载全文后查看