FPGA可编程逻辑器件芯片XC7A15T-1CSG325C中文规格书-USB迷|专注于互联网分享

2024年5月17日发(作者：尉迟绮波)

Chapter 1:Packaging Overview

Pin Definitions

Table1-12 lists the pin definitions used in 7series FPGAs packages.

Note:

There are dedicated general purpose user I/O pins listed separately in Table1-12. There are

also multi-function pins where the pin names start with either IO_LXXY_ZZZ_# or IO_XX_ZZZ_#,

where ZZZ represents one or more functions in addition to being general purpose user I/O. If not

used for their special function, these pins can be user I/O.

IMPORTANT:

For Tandem PROM configuration, the configuration PERSIST property is required. In this

case, a dual-purpose I/O that is used for stage 1 and stage 2 configuration cannot be repurposed as

user I/O after stage 2 configuration is complete.

Table 1-12:7Series FPGAs Pin Definitions

TypeDirectionDescription

Most user I/O pins are capable of differential signaling

and can be implemented as pairs. The top and bottom I/

O pins are always single ended. Each user I/O is labeled

IO_LXXY_#, where:

Pin Name

User I/O Pins

IO_LXXY_#

IO_XX_#

Dedicated

Input/

Output

IO indicates a user I/O pin

L indicates a differential pair, with XX a unique pair in

the bank and Y = [P|N] for the positive/negative sides

of the differential pair

# indicates a bank number

Configuration Pins

For more information, see the Configuration Pin Definitions table in UG470, 7Series FPGAs Configuration User

Guide.

CCLK_0

DONE_0

INIT_B_0

M0_0, M1_0, or M2_0

PROGRAM_B_0

TCK_0

TDI_0

TDO_0

TMS_0

Dedicated

(1)

Dedicated

(1)

Dedicated

(1)

Dedicated

(1)

Dedicated

(1)

Dedicated

(1)

Dedicated

(1)

Dedicated

(1)

Dedicated

(1)

Input/

Output

Bidirectional

Configuration clock. Output in Master mode or input in

Slave mode

DONE indicates successful completion of configuration

(active High)

Bidirectional Indicates initialization of configuration memory (active

(open-drain)Low)

Input

Output

Input

Configuration mode selection

Asynchronous reset to configuration logic (active Low)

JTAG clock

JTAG data input

JTAG data output

JTAG mode select

7 Series FPGAs Packaging

UG475 (v1.18) July 16, 2019

Chapter 1:Packaging Overview

7 Series FPGAs Packaging

UG475 (v1.18) July 16, 2019

Chapter 1:Packaging Overview

Table 1-12:7Series FPGAs Pin Definitions (Cont’d)

TypeDirectionDescriptionPin Name

Multi-gigabit Serial Transceiver Pins (GTPE2, GTXE2, and GTHE2)

For more information on the GTPE2 pins see the Pin Description and Design Guidelines section in UG482, 7Series

FPGAs GTP Transceivers User Guide. For more information on the on the GTXE2 and GTHE2 pins see the Pin

Description and Design Guidelines section in UG476, 7Series FPGAs GTX/GTH Transceivers User Guide.

MGTPRXP[0:3]

MGTPRXN[0:3]

MGTPTXP[0:3]

MGTPTXN[0:3]

MGTXRXP[0:3]

MGTXRXN[0:3]

MGTXTXP[0:3]

MGTXTXN[0:3]

MGTHRXP[0:3]

MGTHRXN[0:3]

MGTHTXP[0:3]

MGTHTXN[0:3]

MGTAVCC_G#

(7)

MGTAVTT_G#

(7)

MGTVCCAUX_G#

(7)

MGTREFCLK0/1P

MGTREFCLK0/1N

MGTAVTTRCAL

MGTRREF

Dedicated

Input

Output

Input

Output

Input

Output

Input

N/A

Input

Positive differential receive port GTP Quad

Negative differential receive port GTP Quad

Positive differential transmit port GTP Quad

Negative differential transmit port GTP Quad

Positive differential receive port GTX Quad

Negative differential receive port GTX Quad

Positive differential transmit port GTX Quad

Negative differential transmit port GTX Quad

Positive differential receive port GTH Quad

Negative differential receive port GTH Quad

Positive differential transmit port GTH Quad

Negative differential transmit port GTH Quad

1.0V analog power-supply pin for the receiver and

transmitter internal circuits.

1.2V analog power-supply pin for the transmit driver

1.8V auxiliary analog Quad PLL (QPLL) voltage supply for

the transceivers

Positive differential reference clock for the transceivers

Negative differential reference clock for the transceivers

Precision reference resistor pin for internal calibration

termination. Not used for Artix-7 devices.

Precision reference resistor pin for internal calibration

termination

Other Pins

These are the clock capable I/Os driving BUFRs, BUFIOs,

BUFGs, and MMCMs/PLLs. In addition, these pins can

drive the BUFMR for multi-region BUFIO and BUFR

support. These pins become regular user I/Os when not

needed as a clock. When connecting a single-ended clock

to the differential CC pair of pins, it must be connected to

the positive (P) side of the pair. The MRCC (multi-region)

pins, when used as single region resource, can drive four

BUFIOs and four BUFR in a single bank.

MRCCMulti-functionInput

7 Series FPGAs Packaging

UG475 (v1.18) July 16, 2019

Chapter 2:7Series FPGAs Package Files

Table 2-1:

Device

XC7S6

XA7S6

XC7S15

XA7S15

XC7S25

XA7S25

XC7S50

XA7S50

XC7S75

XA7S75

XC7S100

XA7S100

Spartan-7 FPGAs Package/Device Pinout Files

CPGA196

Production

CPGA196

Production

CSGA225

Production

CSGA225

Production

CSGA225

Production

CSGA324FTGB196

FTGB196

Production

FTGB196

Production

FGGA484FGGA676

CSGA324

Production

CSGA324

Production

FTGB196

Production

FTGB196

Production

FGGA484

Production

FGGA484

Production

FGGA484

Production

FGGA676

Production

FGGA676

Production

7 Series FPGAs Packaging

UG475 (v1.18) July 16, 2019

Chapter 2:7Series FPGAs Package Files

To download all available Virtex-7 FPGAs package/device/pinout files click here:

7 Series FPGAs Packaging

UG475 (v1.18) July 16, 2019

2024年5月17日发(作者：尉迟绮波)

Chapter 1:Packaging Overview

Pin Definitions

Table1-12 lists the pin definitions used in 7series FPGAs packages.

Note:

There are dedicated general purpose user I/O pins listed separately in Table1-12. There are

also multi-function pins where the pin names start with either IO_LXXY_ZZZ_# or IO_XX_ZZZ_#,

where ZZZ represents one or more functions in addition to being general purpose user I/O. If not

used for their special function, these pins can be user I/O.

IMPORTANT:

For Tandem PROM configuration, the configuration PERSIST property is required. In this

case, a dual-purpose I/O that is used for stage 1 and stage 2 configuration cannot be repurposed as

user I/O after stage 2 configuration is complete.

Table 1-12:7Series FPGAs Pin Definitions

TypeDirectionDescription

Most user I/O pins are capable of differential signaling

and can be implemented as pairs. The top and bottom I/

O pins are always single ended. Each user I/O is labeled

IO_LXXY_#, where:

Pin Name

User I/O Pins

IO_LXXY_#

IO_XX_#

Dedicated

Input/

Output

IO indicates a user I/O pin

L indicates a differential pair, with XX a unique pair in

the bank and Y = [P|N] for the positive/negative sides

of the differential pair

# indicates a bank number

Configuration Pins

For more information, see the Configuration Pin Definitions table in UG470, 7Series FPGAs Configuration User

Guide.

CCLK_0

DONE_0

INIT_B_0

M0_0, M1_0, or M2_0

PROGRAM_B_0

TCK_0

TDI_0

TDO_0

TMS_0

Dedicated

(1)

Dedicated

(1)

Dedicated

(1)

Dedicated

(1)

Dedicated

(1)

Dedicated

(1)

Dedicated

(1)

Dedicated

(1)

Dedicated

(1)

Input/

Output

Bidirectional

Configuration clock. Output in Master mode or input in

Slave mode

DONE indicates successful completion of configuration

(active High)

Bidirectional Indicates initialization of configuration memory (active

(open-drain)Low)

Input

Output

Input

Configuration mode selection

Asynchronous reset to configuration logic (active Low)

JTAG clock

JTAG data input

JTAG data output

JTAG mode select

7 Series FPGAs Packaging

UG475 (v1.18) July 16, 2019

Chapter 1:Packaging Overview

7 Series FPGAs Packaging

UG475 (v1.18) July 16, 2019

Chapter 1:Packaging Overview

Table 1-12:7Series FPGAs Pin Definitions (Cont’d)

TypeDirectionDescriptionPin Name

Multi-gigabit Serial Transceiver Pins (GTPE2, GTXE2, and GTHE2)

For more information on the GTPE2 pins see the Pin Description and Design Guidelines section in UG482, 7Series

FPGAs GTP Transceivers User Guide. For more information on the on the GTXE2 and GTHE2 pins see the Pin

Description and Design Guidelines section in UG476, 7Series FPGAs GTX/GTH Transceivers User Guide.

MGTPRXP[0:3]

MGTPRXN[0:3]

MGTPTXP[0:3]

MGTPTXN[0:3]

MGTXRXP[0:3]

MGTXRXN[0:3]

MGTXTXP[0:3]

MGTXTXN[0:3]

MGTHRXP[0:3]

MGTHRXN[0:3]

MGTHTXP[0:3]

MGTHTXN[0:3]

MGTAVCC_G#

(7)

MGTAVTT_G#

(7)

MGTVCCAUX_G#

(7)

MGTREFCLK0/1P

MGTREFCLK0/1N

MGTAVTTRCAL

MGTRREF

Dedicated

Input

Output

Input

Output

Input

Output

Input

N/A

Input

Positive differential receive port GTP Quad

Negative differential receive port GTP Quad

Positive differential transmit port GTP Quad

Negative differential transmit port GTP Quad

Positive differential receive port GTX Quad

Negative differential receive port GTX Quad

Positive differential transmit port GTX Quad

Negative differential transmit port GTX Quad

Positive differential receive port GTH Quad

Negative differential receive port GTH Quad

Positive differential transmit port GTH Quad

Negative differential transmit port GTH Quad

1.0V analog power-supply pin for the receiver and

transmitter internal circuits.

1.2V analog power-supply pin for the transmit driver

1.8V auxiliary analog Quad PLL (QPLL) voltage supply for

the transceivers

Positive differential reference clock for the transceivers

Negative differential reference clock for the transceivers

Precision reference resistor pin for internal calibration

termination. Not used for Artix-7 devices.

Precision reference resistor pin for internal calibration

termination

Other Pins

These are the clock capable I/Os driving BUFRs, BUFIOs,

BUFGs, and MMCMs/PLLs. In addition, these pins can

drive the BUFMR for multi-region BUFIO and BUFR

support. These pins become regular user I/Os when not

needed as a clock. When connecting a single-ended clock

to the differential CC pair of pins, it must be connected to

the positive (P) side of the pair. The MRCC (multi-region)

pins, when used as single region resource, can drive four

BUFIOs and four BUFR in a single bank.

MRCCMulti-functionInput

7 Series FPGAs Packaging

UG475 (v1.18) July 16, 2019

Chapter 2:7Series FPGAs Package Files

Table 2-1:

Device

XC7S6

XA7S6

XC7S15

XA7S15

XC7S25

XA7S25

XC7S50

XA7S50

XC7S75

XA7S75

XC7S100

XA7S100

Spartan-7 FPGAs Package/Device Pinout Files

CPGA196

Production

CPGA196

Production

CSGA225

Production

CSGA225

Production

CSGA225

Production

CSGA324FTGB196

FTGB196

Production

FTGB196

Production

FGGA484FGGA676

CSGA324

Production

CSGA324

Production

FTGB196

Production

FTGB196

Production

FGGA484

Production

FGGA484

Production

FGGA484

Production

FGGA676

Production

FGGA676

Production

7 Series FPGAs Packaging

UG475 (v1.18) July 16, 2019

Chapter 2:7Series FPGAs Package Files

To download all available Virtex-7 FPGAs package/device/pinout files click here:

7 Series FPGAs Packaging

UG475 (v1.18) July 16, 2019

USB迷 | 专注于互联网分享

FPGA可编程逻辑器件芯片XC7A15T-1CSG325C中文规格书

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