2024年5月19日发(作者：机芳洲)

14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual

FEATURES

SNR = 77.6 dBFS @ 70 MHz and 125 MSPS

SFDR = 88 dBc @ 70 MHz and 125 MSPS

Low power: 750 mW @ 125 MSPS

1.8 V analog supply operation

1.8 V CMOS or LVDS output supply

Integer 1-to-8 input clock divider

IF sampling frequencies to 300 MHz

−152.8 dBm/Hz small signal input noise with 200 Ω input

impedance @ 70 MHz and 125 MSPS

Optional on-chip dither

Programmable internal ADC voltage reference

Integrated ADC sample-and-hold inputs

Flexible analog input range: 1 V p-p to 2 V p-p

Differential analog inputs with 650 MHz bandwidth

ADC clock duty cycle stabilizer

95 dB channel isolation/crosstalk

Serial port control

User-configurable, built-in self-test (BIST) capability

Energy-saving power-down modes

APPLICATIONS

Communications

Diversity radio systems

Multimode digital receivers (3G)

GSM, EDGE, W-CDMA, LTE,

CDMA2000, WiMAX, TD-SCDMA

I/Q demodulation systems

Smart antenna systems

General-purpose software radios

Broadband data applications

Ultrasound equipment

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

Analog-to-Digital Converter (ADC)

AD9258

FUNCTIONAL BLOCK DIAGRAM

AVDD

SDIO/SCLK/

DCSDFS

CSBDRVDD

AD9258

SPI

PROGRAMMING DATA

ORA

VIN+A

CMOS/LVDS

D13A (MSB)

VIN–A

ADC

14

OUTPUT BUFFER

TO

D0A (LSB)

VREF

DIVIDE 1

CLK+

SENSE

TO 8

CLK–

REF

DUTY CYCLEDCO

DCOA

SELECT

STABILIZERGENERATION

DCOB

VCM

RBIAS

ORB

VIN–B

ADC

CMOS/LVDS

14

D13B (MSB)

VIN+B

OUTPUT BUFFER

TO

D0B (LSB)

MULTICHIP

SYNC

AGNDSYNCPDWNOEB

NOTES

1

0

0

1. PIN NAMESARE FOR THE CMOS PIN CONFIGURATION ONLY;

-

4

2

SEE FIGURE 7 FORLVDS PIN NAMES.

1

8

0

Figure 1.

PRODUCT HIGHLIGHTS

1. On-chip dither option for improved SFDR performance

with low power analog input.

2. Proprietary differential input that maintains excellent SNR

performance for input frequencies up to 300 MHz.

3. Operation from a single 1.8 V supply and a separate digital

output driver supply accommodating 1.8 V CMOS or

LVDS outputs.

4. Standard serial port interface (SPI) that supports various

product features and functions, such as data formatting

(offset binary, twos complement, or gray coding), enabling

the clock DCS, power-down, test modes, and voltage

reference mode.

5. Pin compatibility with the AD9268, allowing a simple

migration from 14 bits to 16 bits. The AD9258 is also pin

compatible with the AD9251, AD9231, and AD9204 family

of products for lower sample rate, low power applications.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.

AD9258

Clock Input Considerations ...................................................... 30

Channel/Chip Synchronization ................................................ 31

Power Dissipation and Standby Mode .................................... 32

Digital Outputs ........................................................................... 32

Timing ......................................................................................... 33

Built-In Self-Test (BIST) and Output Test .................................. 34

Built-In Self-Test (BIST) ............................................................ 34

Output Test Modes ..................................................................... 34

Serial Port Interface (SPI) .............................................................. 35

Configuration Using the SPI ..................................................... 35

Hardware Interface ..................................................................... 36

Configuration Without the SPI ................................................ 36

SPI Accessible Features .............................................................. 36

Memory Map .................................................................................. 37

Reading the Memory Map Register Table ............................... 37

Memory Map Register Table ..................................................... 38

Memory Map Register Descriptions ........................................ 40

Applications Information .............................................................. 41

Design Guidelines ...................................................................... 41

Outline Dimensions ....................................................................... 42

Ordering Guide .......................................................................... 42

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Specifications ..................................................................................... 4

ADC DC Specifications ................................................................. 4

ADC AC Specifications ................................................................. 6

Digital Specifications ................................................................... 7

Switching Specifications ................................................................ 9

Timing Specifications ................................................................ 10

Absolute Maximum Ratings .......................................................... 12

Thermal Characteristics ............................................................ 12

ESD Caution ................................................................................ 12

Pin Configurations and Function Descriptions ......................... 13

Typical Performance Characteristics ........................................... 17

Equivalent Circuits ......................................................................... 25

Theory of Operation ...................................................................... 26

ADC Architecture ...................................................................... 26

Analog Input Considerations .................................................... 26

Voltage Reference ....................................................................... 29

REVISION HISTORY

9/09—Rev. 0 to Rev. A

Changes to Features List .................................................................. 1

Changes to Specifications Section .................................................. 4

Changes to Table 5 ............................................................................ 9

Changes to Typical Performance Characteristics Section ......... 17

5/09—Revision 0: Initial Version

Rev. A | Page 2 of 44

2024年5月19日发(作者：机芳洲)

14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual

FEATURES

SNR = 77.6 dBFS @ 70 MHz and 125 MSPS

SFDR = 88 dBc @ 70 MHz and 125 MSPS

Low power: 750 mW @ 125 MSPS

1.8 V analog supply operation

1.8 V CMOS or LVDS output supply

Integer 1-to-8 input clock divider

IF sampling frequencies to 300 MHz

−152.8 dBm/Hz small signal input noise with 200 Ω input

impedance @ 70 MHz and 125 MSPS

Optional on-chip dither

Programmable internal ADC voltage reference

Integrated ADC sample-and-hold inputs

Flexible analog input range: 1 V p-p to 2 V p-p

Differential analog inputs with 650 MHz bandwidth

ADC clock duty cycle stabilizer

95 dB channel isolation/crosstalk

Serial port control

User-configurable, built-in self-test (BIST) capability

Energy-saving power-down modes

APPLICATIONS

Communications

Diversity radio systems

Multimode digital receivers (3G)

GSM, EDGE, W-CDMA, LTE,

CDMA2000, WiMAX, TD-SCDMA

I/Q demodulation systems

Smart antenna systems

General-purpose software radios

Broadband data applications

Ultrasound equipment

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

Analog-to-Digital Converter (ADC)

AD9258

FUNCTIONAL BLOCK DIAGRAM

AVDD

SDIO/SCLK/

DCSDFS

CSBDRVDD

AD9258

SPI

PROGRAMMING DATA

ORA

VIN+A

CMOS/LVDS

D13A (MSB)

VIN–A

ADC

14

OUTPUT BUFFER

TO

D0A (LSB)

VREF

DIVIDE 1

CLK+

SENSE

TO 8

CLK–

REF

DUTY CYCLEDCO

DCOA

SELECT

STABILIZERGENERATION

DCOB

VCM

RBIAS

ORB

VIN–B

ADC

CMOS/LVDS

14

D13B (MSB)

VIN+B

OUTPUT BUFFER

TO

D0B (LSB)

MULTICHIP

SYNC

AGNDSYNCPDWNOEB

NOTES

1

0

0

1. PIN NAMESARE FOR THE CMOS PIN CONFIGURATION ONLY;

-

4

2

SEE FIGURE 7 FORLVDS PIN NAMES.

1

8

0

Figure 1.

PRODUCT HIGHLIGHTS

1. On-chip dither option for improved SFDR performance

with low power analog input.

2. Proprietary differential input that maintains excellent SNR

performance for input frequencies up to 300 MHz.

3. Operation from a single 1.8 V supply and a separate digital

output driver supply accommodating 1.8 V CMOS or

LVDS outputs.

4. Standard serial port interface (SPI) that supports various

product features and functions, such as data formatting

(offset binary, twos complement, or gray coding), enabling

the clock DCS, power-down, test modes, and voltage

reference mode.

5. Pin compatibility with the AD9268, allowing a simple

migration from 14 bits to 16 bits. The AD9258 is also pin

compatible with the AD9251, AD9231, and AD9204 family

of products for lower sample rate, low power applications.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.

AD9258

Clock Input Considerations ...................................................... 30

Channel/Chip Synchronization ................................................ 31

Power Dissipation and Standby Mode .................................... 32

Digital Outputs ........................................................................... 32

Timing ......................................................................................... 33

Built-In Self-Test (BIST) and Output Test .................................. 34

Built-In Self-Test (BIST) ............................................................ 34

Output Test Modes ..................................................................... 34

Serial Port Interface (SPI) .............................................................. 35

Configuration Using the SPI ..................................................... 35

Hardware Interface ..................................................................... 36

Configuration Without the SPI ................................................ 36

SPI Accessible Features .............................................................. 36

Memory Map .................................................................................. 37

Reading the Memory Map Register Table ............................... 37

Memory Map Register Table ..................................................... 38

Memory Map Register Descriptions ........................................ 40

Applications Information .............................................................. 41

Design Guidelines ...................................................................... 41

Outline Dimensions ....................................................................... 42

Ordering Guide .......................................................................... 42

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Specifications ..................................................................................... 4

ADC DC Specifications ................................................................. 4

ADC AC Specifications ................................................................. 6

Digital Specifications ................................................................... 7

Switching Specifications ................................................................ 9

Timing Specifications ................................................................ 10

Absolute Maximum Ratings .......................................................... 12

Thermal Characteristics ............................................................ 12

ESD Caution ................................................................................ 12

Pin Configurations and Function Descriptions ......................... 13

Typical Performance Characteristics ........................................... 17

Equivalent Circuits ......................................................................... 25

Theory of Operation ...................................................................... 26

ADC Architecture ...................................................................... 26

Analog Input Considerations .................................................... 26

Voltage Reference ....................................................................... 29

REVISION HISTORY

9/09—Rev. 0 to Rev. A

Changes to Features List .................................................................. 1

Changes to Specifications Section .................................................. 4

Changes to Table 5 ............................................................................ 9

Changes to Typical Performance Characteristics Section ......... 17

5/09—Revision 0: Initial Version

Rev. A | Page 2 of 44