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    MEMORY存储芯片TMS320C6455BZTZ中文规格书

    IT圈 admin 14浏览 0评论

    2024年11月5日发(作者：南门松)

    TMS320C6414, TMS320C6415, TMS320C6416

    FIXED-POINT DIGITAL SIGNAL PROCESSORS

    SPRS146N − FEBRUARY 2001 − REVISED MAY 2005

    peripheral register descriptions

    Table 4 through Table 23 identify the peripheral registers for the C6414, C6415, and C6416 devices by their

    register names, acronyms, and hex address or hex address range. For more detailed information on the register

    contents, bit names and their descriptions, see the specific peripheral reference guide listed in the

    TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190).

    Table 4. EMIFA Registers

    HEX ADDRESS RANGE

    0180 0000

    0180 0004

    0180 0008

    0180 000C

    0180 0010

    0180 0014

    0180 0018

    0180 001C

    0180 0020

    0180 0024 − 0180 003C

    0180 0040

    0180 0044

    0180 0048

    0180 004C

    0180 0050

    0180 0054

    0180 0058 − 0183 FFFF

    ACRONYM

    GBLCTL

    CECTL1

    CECTL0

    −

    CECTL2

    CECTL3

    SDCTL

    SDTIM

    SDEXT

    −

    PDTCTL

    CESEC1

    CESEC0

    −

    CESEC2

    CESEC3

    –

    EMIFA global control

    EMIFA CE1 space control

    EMIFA CE0 space control

    Reserved

    EMIFA CE2 space control

    EMIFA CE3 space control

    EMIFA SDRAM control

    EMIFA SDRAM refresh control

    EMIFA SDRAM extension

    Reserved

    Peripheral device transfer (PDT) control

    EMIFA CE1 space secondary control

    EMIFA CE0 space secondary control

    Reserved

    EMIFA CE2 space secondary control

    EMIFA CE3 space secondary control

    Reserved

    REGISTER NAME

    Table 5. EMIFB Registers

    HEX ADDRESS RANGE

    01A8 0000

    01A8 0004

    01A8 0008

    01A8 000C

    01A8 0010

    01A8 0014

    01A8 0018

    01A8 001C

    01A8 0020

    01A8 0024 − 01A8 003C

    01A8 0040

    01A8 0044

    01A8 0048

    01A8 004C

    01A8 0050

    01A8 0054

    01A8 0058 − 01AB FFFF

    ACRONYM

    GBLCTL

    CECTL1

    CECTL0

    −

    CECTL2

    CECTL3

    SDCTL

    SDTIM

    SDEXT

    −

    PDTCTL

    CESEC1

    CESEC0

    −

    CESEC2

    CESEC3

    –

    EMIFB global control

    EMIFB CE1 space control

    EMIFB CE0 space control

    Reserved

    EMIFB CE2 space control

    EMIFB CE3 space control

    EMIFB SDRAM control

    EMIFB SDRAM refresh control

    EMIFB SDRAM extension

    Reserved

    Peripheral device transfer (PDT) control

    EMIFB CE1 space secondary control

    EMIFB CE0 space secondary control

    Reserved

    EMIFB CE2 space secondary control

    EMIFB CE3 space secondary control

    Reserved

    REGISTER NAME

    TMS320C6414, TMS320C6415, TMS320C6416

    FIXED-POINT DIGITAL SIGNAL PROCESSORS

    SPRS146N − FEBRUARY 2001 − REVISED MAY 2005

    peripheral register descriptions (continued)

    Table 6. L2 Cache Registers

    HEX ADDRESS RANGE

    0184 0000

    0184 0004 − 0184 0FFC

    0184 1000

    0184 1004 − 0184 1FFC

    0184 2000

    0184 2004

    0184 2008

    0184 200C

    0184 2010 − 0184 3FFC

    0184 4000

    0184 4004

    0184 4010

    0184 4014

    0184 4018

    0184 401C

    0184 4020

    0184 4024

    0184 4030

    0184 4034

    0184 4038 − 0184 4044

    0184 4048

    0184 404C

    0184 4050 − 0184 4FFC

    0184 5000

    0184 5004

    0184 5008 − 0184 7FFC

    0184 8000 − 0184 817C

    0184 8180

    0184 8184

    0184 8188

    0184 818C

    0184 8190

    0184 8194

    0184 8198

    0184 819C

    0184 81A0

    0184 81A4

    0184 81A8

    0184 81AC

    ACRONYM

    CCFG

    −

    EDMAWEIGHT

    −

    L2ALLOC0

    L2ALLOC1

    L2ALLOC2

    L2ALLOC3

    −

    L2WBAR

    L2WWC

    L2WIBAR

    L2WIWC

    L2IBAR

    L2IWC

    L1PIBAR

    L1PIWC

    L1DWIBAR

    L1DWIWC

    −

    L1DIBAR

    L1DIWC

    −

    L2WB

    L2WBINV

    −

    MAR0 to

    MAR95

    MAR96

    MAR97

    MAR98

    MAR99

    MAR100

    MAR101

    MAR102

    MAR103

    MAR104

    MAR105

    MAR106

    MAR107

    Reserved

    L2 EDMA access control register

    Reserved

    L2 allocation register 0

    L2 allocation register 1

    L2 allocation register 2

    L2 allocation register 3

    Reserved

    L2 writeback base address register

    L2 writeback word count register

    L2 writeback invalidate base address register

    L2 writeback invalidate word count register

    L2 invalidate base address register

    L2 invalidate word count register

    L1P invalidate base address register

    L1P invalidate word count register

    L1D writeback invalidate base address register

    L1D writeback invalidate word count register

    Reserved

    L1D invalidate base address register

    L1D invalidate word count register

    Reserved

    L2 writeback all register

    L2 writeback invalidate all register

    Reserved

    Reserved

    Controls EMIFB CE0 range 6000 0000 − 60FF FFFF

    Controls EMIFB CE0 range 6100 0000 − 61FF FFFF

    Controls EMIFB CE0 range 6200 0000 − 62FF FFFF

    Controls EMIFB CE0 range 6300 0000 − 63FF FFFF

    Controls EMIFB CE1 range 6400 0000 − 64FF FFFF

    Controls EMIFB CE1 range 6500 0000 − 65FF FFFF

    Controls EMIFB CE1 range 6600 0000 − 66FF FFFF

    Controls EMIFB CE1 range 6700 0000 − 67FF FFFF

    Controls EMIFB CE2 range 6800 0000 − 68FF FFFF

    Controls EMIFB CE2 range 6900 0000 − 69FF FFFF

    Controls EMIFB CE2 range 6A00 0000 − 6AFF FFFF

    Controls EMIFB CE2 range 6B00 0000 − 6BFF FFFF

    REGISTER NAME

    Cache configuration register

    COMMENTS

    2024年11月5日发(作者：南门松)

    TMS320C6414, TMS320C6415, TMS320C6416

    FIXED-POINT DIGITAL SIGNAL PROCESSORS

    SPRS146N − FEBRUARY 2001 − REVISED MAY 2005

    peripheral register descriptions

    Table 4 through Table 23 identify the peripheral registers for the C6414, C6415, and C6416 devices by their

    register names, acronyms, and hex address or hex address range. For more detailed information on the register

    contents, bit names and their descriptions, see the specific peripheral reference guide listed in the

    TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190).

    Table 4. EMIFA Registers

    HEX ADDRESS RANGE

    0180 0000

    0180 0004

    0180 0008

    0180 000C

    0180 0010

    0180 0014

    0180 0018

    0180 001C

    0180 0020

    0180 0024 − 0180 003C

    0180 0040

    0180 0044

    0180 0048

    0180 004C

    0180 0050

    0180 0054

    0180 0058 − 0183 FFFF

    ACRONYM

    GBLCTL

    CECTL1

    CECTL0

    −

    CECTL2

    CECTL3

    SDCTL

    SDTIM

    SDEXT

    −

    PDTCTL

    CESEC1

    CESEC0

    −

    CESEC2

    CESEC3

    –

    EMIFA global control

    EMIFA CE1 space control

    EMIFA CE0 space control

    Reserved

    EMIFA CE2 space control

    EMIFA CE3 space control

    EMIFA SDRAM control

    EMIFA SDRAM refresh control

    EMIFA SDRAM extension

    Reserved

    Peripheral device transfer (PDT) control

    EMIFA CE1 space secondary control

    EMIFA CE0 space secondary control

    Reserved

    EMIFA CE2 space secondary control

    EMIFA CE3 space secondary control

    Reserved

    REGISTER NAME

    Table 5. EMIFB Registers

    HEX ADDRESS RANGE

    01A8 0000

    01A8 0004

    01A8 0008

    01A8 000C

    01A8 0010

    01A8 0014

    01A8 0018

    01A8 001C

    01A8 0020

    01A8 0024 − 01A8 003C

    01A8 0040

    01A8 0044

    01A8 0048

    01A8 004C

    01A8 0050

    01A8 0054

    01A8 0058 − 01AB FFFF

    ACRONYM

    GBLCTL

    CECTL1

    CECTL0

    −

    CECTL2

    CECTL3

    SDCTL

    SDTIM

    SDEXT

    −

    PDTCTL

    CESEC1

    CESEC0

    −

    CESEC2

    CESEC3

    –

    EMIFB global control

    EMIFB CE1 space control

    EMIFB CE0 space control

    Reserved

    EMIFB CE2 space control

    EMIFB CE3 space control

    EMIFB SDRAM control

    EMIFB SDRAM refresh control

    EMIFB SDRAM extension

    Reserved

    Peripheral device transfer (PDT) control

    EMIFB CE1 space secondary control

    EMIFB CE0 space secondary control

    Reserved

    EMIFB CE2 space secondary control

    EMIFB CE3 space secondary control

    Reserved

    REGISTER NAME

    TMS320C6414, TMS320C6415, TMS320C6416

    FIXED-POINT DIGITAL SIGNAL PROCESSORS

    SPRS146N − FEBRUARY 2001 − REVISED MAY 2005

    peripheral register descriptions (continued)

    Table 6. L2 Cache Registers

    HEX ADDRESS RANGE

    0184 0000

    0184 0004 − 0184 0FFC

    0184 1000

    0184 1004 − 0184 1FFC

    0184 2000

    0184 2004

    0184 2008

    0184 200C

    0184 2010 − 0184 3FFC

    0184 4000

    0184 4004

    0184 4010

    0184 4014

    0184 4018

    0184 401C

    0184 4020

    0184 4024

    0184 4030

    0184 4034

    0184 4038 − 0184 4044

    0184 4048

    0184 404C

    0184 4050 − 0184 4FFC

    0184 5000

    0184 5004

    0184 5008 − 0184 7FFC

    0184 8000 − 0184 817C

    0184 8180

    0184 8184

    0184 8188

    0184 818C

    0184 8190

    0184 8194

    0184 8198

    0184 819C

    0184 81A0

    0184 81A4

    0184 81A8

    0184 81AC

    ACRONYM

    CCFG

    −

    EDMAWEIGHT

    −

    L2ALLOC0

    L2ALLOC1

    L2ALLOC2

    L2ALLOC3

    −

    L2WBAR

    L2WWC

    L2WIBAR

    L2WIWC

    L2IBAR

    L2IWC

    L1PIBAR

    L1PIWC

    L1DWIBAR

    L1DWIWC

    −

    L1DIBAR

    L1DIWC

    −

    L2WB

    L2WBINV

    −

    MAR0 to

    MAR95

    MAR96

    MAR97

    MAR98

    MAR99

    MAR100

    MAR101

    MAR102

    MAR103

    MAR104

    MAR105

    MAR106

    MAR107

    Reserved

    L2 EDMA access control register

    Reserved

    L2 allocation register 0

    L2 allocation register 1

    L2 allocation register 2

    L2 allocation register 3

    Reserved

    L2 writeback base address register

    L2 writeback word count register

    L2 writeback invalidate base address register

    L2 writeback invalidate word count register

    L2 invalidate base address register

    L2 invalidate word count register

    L1P invalidate base address register

    L1P invalidate word count register

    L1D writeback invalidate base address register

    L1D writeback invalidate word count register

    Reserved

    L1D invalidate base address register

    L1D invalidate word count register

    Reserved

    L2 writeback all register

    L2 writeback invalidate all register

    Reserved

    Reserved

    Controls EMIFB CE0 range 6000 0000 − 60FF FFFF

    Controls EMIFB CE0 range 6100 0000 − 61FF FFFF

    Controls EMIFB CE0 range 6200 0000 − 62FF FFFF

    Controls EMIFB CE0 range 6300 0000 − 63FF FFFF

    Controls EMIFB CE1 range 6400 0000 − 64FF FFFF

    Controls EMIFB CE1 range 6500 0000 − 65FF FFFF

    Controls EMIFB CE1 range 6600 0000 − 66FF FFFF

    Controls EMIFB CE1 range 6700 0000 − 67FF FFFF

    Controls EMIFB CE2 range 6800 0000 − 68FF FFFF

    Controls EMIFB CE2 range 6900 0000 − 69FF FFFF

    Controls EMIFB CE2 range 6A00 0000 − 6AFF FFFF

    Controls EMIFB CE2 range 6B00 0000 − 6BFF FFFF

    REGISTER NAME

    Cache configuration register

    COMMENTS

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