2024年7月16日发(作者：迮昕昕)
System MMR Assignments
Table A-18. MXVR Memory Map (Cont’d)
Memory
Mapped
Address
Register NameDescription
0xFFC0 2728MXVR_DELAY
16-bit RO
Reset = 0x8000
0xFFC0 272CMXVR_MAX_DELAY
16-bit RO
Reset = 0x0000
0xFFC0 2730MXVR_LADDR
32-bit R/W
Reset = 0x0000 0FFF
0xFFC0 2734MXVR_GADDR
16-bit R/W
Reset = 0x0000
0xFFC0 2738MXVR_AADDR
32-bit R/W
Reset = 0x0000 0FFF
0xFFC0 273CMXVR_ALLOC_0
32-bit RO
Reset = 0xXXXX XXXX
0xFFC0 2740MXVR_ALLOC_1
32-bit RO
Reset = 0xXXXX XXXX
0xFFC0 2744MXVR_ALLOC_2
32-bit RO
Reset = 0xXXXX XXXX
0xFFC0 2748MXVR_ALLOC_3
32-bit RO
Reset = 0xXXXX XXXX
0xFFC0 274CMXVR_ALLOC_4
32-bit RO
Reset = 0xXXXX XXXX
“MXVR Node Frame Delay (MXVR_DELAY)
Register” on page29-50
“MXVR Maximum Node Frame Delay
(MXVR_MAX_DELAY) Register” on
page29-52
“MXVR Logical Address (MXVR_LADDR)
Register” on page29-53
“MXVR Group Address (MXVR_GADDR)
Register” on page29-54
“MXVR Alternate Address (MXVR_AADDR)
Register” on page29-55
“MXVR Allocation Table (MXVR_ALLOC_0
–MXVR_ALLOC_14) Registers” on
page29-55
“MXVR Allocation Table (MXVR_ALLOC_0
–MXVR_ALLOC_14) Registers” on
page29-55
“MXVR Allocation Table (MXVR_ALLOC_0
–MXVR_ALLOC_14) Registers” on
page29-55
“MXVR Allocation Table (MXVR_ALLOC_0
–MXVR_ALLOC_14) Registers” on
page29-55
“MXVR Allocation Table (MXVR_ALLOC_0
–MXVR_ALLOC_14) Registers” on
page29-55
ADSP-BF54x Blackfin Processor Hardware Reference
2024年7月16日发(作者：迮昕昕)
System MMR Assignments
Table A-18. MXVR Memory Map (Cont’d)
Memory
Mapped
Address
Register NameDescription
0xFFC0 2728MXVR_DELAY
16-bit RO
Reset = 0x8000
0xFFC0 272CMXVR_MAX_DELAY
16-bit RO
Reset = 0x0000
0xFFC0 2730MXVR_LADDR
32-bit R/W
Reset = 0x0000 0FFF
0xFFC0 2734MXVR_GADDR
16-bit R/W
Reset = 0x0000
0xFFC0 2738MXVR_AADDR
32-bit R/W
Reset = 0x0000 0FFF
0xFFC0 273CMXVR_ALLOC_0
32-bit RO
Reset = 0xXXXX XXXX
0xFFC0 2740MXVR_ALLOC_1
32-bit RO
Reset = 0xXXXX XXXX
0xFFC0 2744MXVR_ALLOC_2
32-bit RO
Reset = 0xXXXX XXXX
0xFFC0 2748MXVR_ALLOC_3
32-bit RO
Reset = 0xXXXX XXXX
0xFFC0 274CMXVR_ALLOC_4
32-bit RO
Reset = 0xXXXX XXXX
“MXVR Node Frame Delay (MXVR_DELAY)
Register” on page29-50
“MXVR Maximum Node Frame Delay
(MXVR_MAX_DELAY) Register” on
page29-52
“MXVR Logical Address (MXVR_LADDR)
Register” on page29-53
“MXVR Group Address (MXVR_GADDR)
Register” on page29-54
“MXVR Alternate Address (MXVR_AADDR)
Register” on page29-55
“MXVR Allocation Table (MXVR_ALLOC_0
–MXVR_ALLOC_14) Registers” on
page29-55
“MXVR Allocation Table (MXVR_ALLOC_0
–MXVR_ALLOC_14) Registers” on
page29-55
“MXVR Allocation Table (MXVR_ALLOC_0
–MXVR_ALLOC_14) Registers” on
page29-55
“MXVR Allocation Table (MXVR_ALLOC_0
–MXVR_ALLOC_14) Registers” on
page29-55
“MXVR Allocation Table (MXVR_ALLOC_0
–MXVR_ALLOC_14) Registers” on
page29-55
ADSP-BF54x Blackfin Processor Hardware Reference