2024年7月23日发(作者：摩歌韵)
Feature Descriptions
Table1-15 lists the SFP+ module RX and TX connections to the FPGA.
Table 1-15:FPGA U1 GTX Bank 113 to SFP+ Module Connections
Schematic Net Name
SFP_RX_N
SFP_RX_P
SFP_TX_P
SFP_TX_N
SFP_TX_DISABLE_TRANS
SFP+ Module (P3)
Pin
12
13
18
19
3
Name
RD_N
RD_P
TD_P
TD_N
TX_DISABLE
FPGA (U1) Pin
AL5
AL6
AM4
AM3
AP33
Table1-16 lists the SFP+ module control and status connections to the FPGA.
Table 1-16:SFP+ Module Control and Status
Board Connection
Test Point J22High=Fault
Low=Normal Operation
SFP_TX_DISABLEJumper J6Off=SFP Disabled
On=SFP Enabled
SFP_MOD_DETECTTest Point J21High=Module Not Present
Low=Module Present
SFP_RS0Jumper J38Jumper Pins 1-2=Full RX Bandwidth
Jumper Pins 2-3=Reduced RX Bandwidth
SFP_RS1Jumper J39Jumper Pins 1-2=Full TX Bandwidth
Jumper Pins 2-3=Reduced TX Bandwidth
SFP_LOSTest Point J20High=Loss of Receiver Signal
Low=Normal Operation
SFP Control/Status
Signal
SFP_TX_FAULT
10/100/1000 Tri-Speed Ethernet PHY
[Figure1-2, callout 15]
The VC707 board utilizes the Marvell Alaska PHY device (88E1111) U50 for Ethernet
communications at 10, 100, or 1000 Mb/s. The board supports SGMII mode only. The PHY
connection to a user-provided Ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector (P4)
with built-in magnetics.
On power-up, or on reset, the PHY is configured to operate in SGMII mode with PHY address
0b00111 using the settings shown in Table1-17. These settings can be overwritten by software
commands passed over the MDIO interface.
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
Chapter 1:VC707 Evaluation Board Features
The 10x40 rows of an FMC HPC connector provides pins for up to:
•
•
•
•
•
160 single-ended or 80 differential user-defined signals
10 GTX transceivers
2 GTX clocks
4 differential clocks
159 ground and 15 power connections
The VC707 board FMC2 HPC connector J37 implements a subset of the maximum signal and clock
connectivity capabilities:
•58 differential user-defined pairs (as shipped with the Virtex-7 XC7VX485T-2FFG1761C
FPGA installed on the VC707 board, the FMC2 HB00-HB21 bus connections are not
supported. Refer to the Virtex-7FPGA VC707 Evaluation Kit Master Answer Record in
Appendix
G: References for more information).
34 LA pairs (LA00-LA33)
24 HA pairs (HA00-HA23)
8 GTX transceivers
2 GTX clocks
2 differential clocks
•
•
•
•
•
The FMC2 HPC signals are distributed across GTX Quads 116 and 117. Each Quad has the VCCO
voltage connected to VADJ.
Note:
The VC707 board VADJ voltage for the FMC2 HPC (J37) connector is determined by the
FMC VADJ power sequencing logic described in FMC_VADJ Voltage Control.
Signaling Speed Ratings:
•
•
Single-ended: 9GHz (18 Gb/s)
Differential
•
•
•
Optimal Vertical: 9GHz (18 Gb/s)
Optimal Horizontal: 16GHz (32 Gb/s)
High Density Vertical: 7GHz (15 Gb/s)
Mechanical specifications:
•
•
Samtec SEAM/SEAF Series
1.27 mm x 1.27 mm (0.050" x 0.050") pitch
The Samtec connector system is rated for signaling speeds up to 9GHz (18 Gb/s) based on a -3 dB
insertion loss point within a two-level signaling environment.
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
2024年7月23日发(作者：摩歌韵)
Feature Descriptions
Table1-15 lists the SFP+ module RX and TX connections to the FPGA.
Table 1-15:FPGA U1 GTX Bank 113 to SFP+ Module Connections
Schematic Net Name
SFP_RX_N
SFP_RX_P
SFP_TX_P
SFP_TX_N
SFP_TX_DISABLE_TRANS
SFP+ Module (P3)
Pin
12
13
18
19
3
Name
RD_N
RD_P
TD_P
TD_N
TX_DISABLE
FPGA (U1) Pin
AL5
AL6
AM4
AM3
AP33
Table1-16 lists the SFP+ module control and status connections to the FPGA.
Table 1-16:SFP+ Module Control and Status
Board Connection
Test Point J22High=Fault
Low=Normal Operation
SFP_TX_DISABLEJumper J6Off=SFP Disabled
On=SFP Enabled
SFP_MOD_DETECTTest Point J21High=Module Not Present
Low=Module Present
SFP_RS0Jumper J38Jumper Pins 1-2=Full RX Bandwidth
Jumper Pins 2-3=Reduced RX Bandwidth
SFP_RS1Jumper J39Jumper Pins 1-2=Full TX Bandwidth
Jumper Pins 2-3=Reduced TX Bandwidth
SFP_LOSTest Point J20High=Loss of Receiver Signal
Low=Normal Operation
SFP Control/Status
Signal
SFP_TX_FAULT
10/100/1000 Tri-Speed Ethernet PHY
[Figure1-2, callout 15]
The VC707 board utilizes the Marvell Alaska PHY device (88E1111) U50 for Ethernet
communications at 10, 100, or 1000 Mb/s. The board supports SGMII mode only. The PHY
connection to a user-provided Ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector (P4)
with built-in magnetics.
On power-up, or on reset, the PHY is configured to operate in SGMII mode with PHY address
0b00111 using the settings shown in Table1-17. These settings can be overwritten by software
commands passed over the MDIO interface.
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
Chapter 1:VC707 Evaluation Board Features
The 10x40 rows of an FMC HPC connector provides pins for up to:
•
•
•
•
•
160 single-ended or 80 differential user-defined signals
10 GTX transceivers
2 GTX clocks
4 differential clocks
159 ground and 15 power connections
The VC707 board FMC2 HPC connector J37 implements a subset of the maximum signal and clock
connectivity capabilities:
•58 differential user-defined pairs (as shipped with the Virtex-7 XC7VX485T-2FFG1761C
FPGA installed on the VC707 board, the FMC2 HB00-HB21 bus connections are not
supported. Refer to the Virtex-7FPGA VC707 Evaluation Kit Master Answer Record in
Appendix
G: References for more information).
34 LA pairs (LA00-LA33)
24 HA pairs (HA00-HA23)
8 GTX transceivers
2 GTX clocks
2 differential clocks
•
•
•
•
•
The FMC2 HPC signals are distributed across GTX Quads 116 and 117. Each Quad has the VCCO
voltage connected to VADJ.
Note:
The VC707 board VADJ voltage for the FMC2 HPC (J37) connector is determined by the
FMC VADJ power sequencing logic described in FMC_VADJ Voltage Control.
Signaling Speed Ratings:
•
•
Single-ended: 9GHz (18 Gb/s)
Differential
•
•
•
Optimal Vertical: 9GHz (18 Gb/s)
Optimal Horizontal: 16GHz (32 Gb/s)
High Density Vertical: 7GHz (15 Gb/s)
Mechanical specifications:
•
•
Samtec SEAM/SEAF Series
1.27 mm x 1.27 mm (0.050" x 0.050") pitch
The Samtec connector system is rated for signaling speeds up to 9GHz (18 Gb/s) based on a -3 dB
insertion loss point within a two-level signaling environment.
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019