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TLC7528C, TLC7528E, TLC7528I

DUAL 8ĆBIT MULTIPLYING

DIGITALĆTOĆANALOG CONVERTERS

SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008

Easily Interfaced to Microprocessors

On-Chip Data Latches

Monotonic Over the Entire A/D Conversion

Range

Interchangeable With Analog Devices

AD7528 and PMI PM-7528

Fast Control Signaling for Digital Signal

Processor (DSP) Applications Including

Interface With TMS320

Voltage-Mode Operation

CMOS Technology

KEY PERFORMANCE SPECIFICATIONS

Resolution

Linearity Error

Power Dissipation at V

= 5V

Settling Time at V

= 5V

Propagation Delay Time at V

= 5V

8 bits

1/2LSB

20mW

100ns

80ns

DW, N OR PW PACKAGE

(TOP VIEW)

AGND

OUTA

RFBA

REFA

DGND

DACA/DACB

(MSB) DB7

DB6

DB5

DB4

OUTB

RFBB

REFB

DB0 (LSB)

DB1

DB2

DB3

FN PACKAGE

(TOP VIEW)

description

The TLC7528C, TLC7528E, and TLC7528I are

dual, 8-bit, digital-to-analog converters (DACs)

designed with separate on-chip data latches and

feature exceptionally close DAC-to-DAC match-

ing. Data are transferred to either of the two DAC

data latches through a common, 8-bit, input port.

Control input DACA/DACB determines which

DAC is to be loaded. The load cycle of these

devices is similar to the write cycle of a

random-access memory, allowing easy interface

to most popular microprocessor buses and output

ports. Segmenting the high-order bits minimizes

glitches during changes in the most significant

bits, where glitch impulse is typically the

strongest.

REFA

DGND

DACA/DACB

(MSB) DB7

DB6

3212019

910111213

REFB

DB0 (LSB)

These devices operate from a 5V to 15V power supply and dissipates less than 15mW (typical). The 2- or

4-quadrant multiplying makes these devices a sound choice for many microprocessor-controlled gain-setting

and signal-control applications. It can be operated in voltage mode, which produces a voltage output rather than

a current output. Refer to the typical application information in this data sheet.

The TLC7528C is characterized for operation from 0°C to +70°C. The TLC7528I is characterized for operation

from −25°C to +85°C. The TLC7528E is characterized for operation from −40°C to +85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

•

SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008

TLC7528C, TLC7528E, TLC7528I

DUAL 8ĆBIT MULTIPLYING

DIGITALĆTOĆANALOG CONVERTERS

functional block diagram

DB0

Data

Inputs

DB7

REFA

Input

Buffer

RFBA

OUTA

Latch A

DACA

AGND

RFBB

OUTB

DACA/DACB

Logic

Control

Latch B

DACB

REFB

operating sequence

su(CS)

su(DAC

)

DACA/DACB

w(WR)

su(D)

DB0−DB7

Data In Stable

h(D)

h(DAC)

h(CS)

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

•

TLC7528C, TLC7528E, TLC7528I

DUAL 8ĆBIT MULTIPLYING

DIGITALĆTOĆANALOG CONVERTERS

SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

(to AGND or DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to 16.5V

Voltage between AGND and DGND

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±V

Input voltage range, V

(to DGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to V

+ 0.3

Reference voltage, V

refA

or V

refB

(to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V

Feedback voltage V

RFBA

or V

RFBB

(to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V

Input voltage (voltage mode out A, out B to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3V to V

+ 0.3

Output voltage, V

or V

(to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V

Peak input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°COperating free-air temperature range, T

: TLC7528C

TLC7528I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25°C to +85°C

TLC7528E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to +85°C

Storage temperature range, T

stg

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C

Case temperature for 10 seconds, T

: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C

Lead temperature 1,6mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . . . . . . . . . +260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

package/ordering information

For the most current package and ordering information, see the Package Option Addendum at the end of this

document, or see the TI website at .

recommended operating conditions

= 4.75V to 5.25V

MINNOMMAX

Reference voltage, V

refA

or V

refB

High-level input voltage, V

Low-level input voltage, V

CS setup time, t

su(CS)

CS hold time, t

h(CS)

DAC select setup time, t

su(DAC)

DAC select hold time, t

h(DAC)

Data bus input setup time t

su(D)

Data bus input hold time t

h(D)

Pulse duration, WR low, t

w(WR)

TLC7628C

Operating free-air temperature, T

TLC7628I

TLC7628E

±10

2.4

0.8

−25

−40

+70

+85

−25

−40

+70

+85

13.5

1.5

= 14.5V to 15.5V

MINNOMMAX

±10

UNIT

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SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008

TLC7528C, TLC7528E, TLC7528I

DUAL 8ĆBIT MULTIPLYING

DIGITALĆTOĆANALOG CONVERTERS

electrical characteristics over recommended operating free-air temperature range,

refA

= V

refB

= 10V, V

and V

at 0V (unless otherwise noted)

PARAMETER

High-level input current

Low-level input current

Reference input impedance

REFA or REFB to AGND

OUTA

Ikg

Output leakage current

OUTB

Input resistance match

(REFA to REFB)

DC supply sensitivity, ∆gain/∆V

Supply current (quiescent)

Supply current (standby)

DB0−DB7

Input capacitance

WR, CS,

DACA/DACB

DAC data latches loaded with

00000000

DAC data latches loaded with

11111111

∆V

= ±10%

All digital inputs at V

min or

max

All digital inputs at 0V or V

DAC data latch loaded with

00000000, V

refA

= ±10V

DAC data latch loaded with

00000000, V

refB

= ±10V

TEST CONDITIONS

= V

= 0

= 5V

MINTYP

†

MAX

512−10

±400

±1%

0.04

0.5

120

512

= 15V

MINTYP

†

MAX

−10

±200

±1%

0.02

0.5

120

%/%

UNIT

µA

kΩ

Output capacitance (OUTA, OUTB)

†

All typical values are at T

= +25°C.

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TLC7528C, TLC7528E, TLC7528I

DUAL 8ĆBIT MULTIPLYING

DIGITALĆTOĆANALOG CONVERTERS

SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008

operating characteristics over recommended operating free-air temperature range,

refA

= V

refB

= 10V, V

and V

at 0V (unless otherwise noted)

PARAMETER

Linearity error

Settling time (to 1/2LSB)

Gain error

AC feedthrough

REFA to OUTA

REFB to OUTB

See Note 1

See Note 2

See Note 3

See Note 4

See Note 5

See Note 6

See Note 7

Measured for code transition from

00000000 to 11111111,

= +25°C

Measured for code transition from

00000000 to 11111111,

= +25°C

160

TEST CONDITIONS

= 5V

MINTYPMAX

±1/2

100

2.5

−65

0.007

440

= 15V

MINTYPMAX

±1/2

100

2.5

−65

UNIT

LSB

Temperature coefficient of gain

Propagation delay (from digital input to

90% of final analog output current)

Channel-to-channel

isolation

REFA to OUTB

REFB to OUTA

0.0035%FSR/°C

80ns

Digital-to-analog glitch impulse areanV−s

Digital crosstalk

Harmonic distortion

NOTES:1.

3060nV−s

= 6V,f = 1kHz,T

= +25°C−85−85dB

OUTA, OUTB load = 100Ω, C

ext

= 13pF; WR and CS at 0V; DB0−DB7 at 0V to V

or V

to 0V.

Gain error is measured using an internal feedback resistor. Nominal full scale range (FSR) = V

ref

− 1LSB.

ref

= 20V peak-to-peak, 100kHz sine wave; DAC data latches loaded with 00000000.

Temperature coefficient of gain measured from 0°C to +25°C or from +25°C to +70°C.

refA

= V

refB

= 10V; OUTA/OUTB load = 100Ω, C

ext

= 13pF; WR and CS at 0V; DB0−DB7 at 0V to V

or V

to 0V.

Both DAC latches loaded with 11111111; V

refA

= 20V peak-to-peak, 100kHz sine wave; V

refB

= 0; T

= +25°C.

Both DAC latches loaded with 11111111; V

refB

= 20V peak-to-peak, 100kHz sine wave; V

refA

= 0; T

= +25°C.

PRINCIPLES OF OPERATION

These devices contain two identical, 8-bit-multiplying DACs, DACA and DACB. Each DAC consists of an

inverted R-2R ladder, analog switches, and input data latches. Binary-weighted currents are switched between

DAC output and AGND, thus maintaining a constant current in each ladder leg independent of the switch state.

Most applications require only the addition of an external operational amplifier and voltage reference. A

simplified DAC circuit for DACA with all digital inputs low is shown in Figure 1.

Figure 2 shows the DACA equivalent circuit. A similar equivalent circuit can be drawn for DACB. Both DACs

share the analog ground terminal 1 (AGND). With all digital inputs high, the entire reference current flows to

OUTA. A small leakage current (I

Ikg

) flows across internal junctions, and as with most semiconductor devices,

doubles every 10°C. C

is due to the parallel combination of the NMOS switches and has a value that depends

on the number of switches connected to the output. The range of C

is 50pF to 120pF maximum. The equivalent

output resistance (r

) varies with the input code from 0.8R to 3R where R is the nominal value of the ladder

resistor in the R-2R network.

These devices interface to a microprocessor through the data bus, CS, WR, and DACA/DACB control signals.

When CS and WR are both low, the TLC7528 analog output, specified by the DACA/DACB control line,

responds to the activity on the DB0−DB7 data bus inputs. In this mode, the input latches are transparent and

input data directly affects the analog output. When either the CS signal or WR signal goes high, the data on the

DB0−DB7 inputs are latched until the CS and WR signals go low again. When CS is high, the data inputs are

disabled regardless of the state of the WR signal.

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SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008

TLC7528C, TLC7528E, TLC7528I

DUAL 8ĆBIT MULTIPLYING

DIGITALĆTOĆANALOG CONVERTERS

PRINCIPLES OF OPERATION

The digital inputs of these devices provide TTL compatibility when operated from a supply voltage of 5V. These

devices can operate with any supply voltage in the range from 5V to 15V; however, input logic levels are not

TTL-compatible above 5V.

S1S2S3S8

OUTA

AGND

RFBA

REFA

DACA Data Latches and Drivers

Figure 1. Simplified Functional Circuit for DACA

RFBA

REFA

256

Ikg

OUT

AGND

OUTA

Figure 2. TLC7528 Equivalent Circuit, DACA Latch Loaded With 11111111

MODE SELECTION TABLE

DACA/DACB

DACA

Write

Hold

DACB

Hold

Write

Hold

L = low level, H = high level, X = don’t care

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TLC7528C, TLC7528E, TLC7528I

DUAL 8ĆBIT MULTIPLYING

DIGITALĆTOĆANALOG CONVERTERS

SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008

APPLICATION INFORMATION

These devices are capable of performing 2-quadrant or full 4-quadrant multiplication. Circuit configurations for

2-quadrant and 4-quadrant multiplication are shown in Figure 3 and Figure 4. Table 1 and Table 2 summarize

input coding for unipolar and bipolar operation, respectively.

I(A)

±10 V

R1 (see Note A)

REFA

Input

Buffer

Latch

OUTA

RFBA

R2 (see Note A)

(see Note B)

−

R4 (see Note A)

(see Note B)

−

AGND

DB0

DB7

DACA

AGND

RFBB

OUTB

DACA/DACB

Control

Logic

DGND

Latch

DACB

REFB

AGND

RECOMMENDED TRIM

RESISTOR VALUES

R1, R3

R2, R4

500 Ω

150 Ω

R3 (see Note A)

I(B)

±10 V

NOTES:A.R1, R2, R3, and R4 are used only if gain adjustment is required. See table for recommended values. Make gain adjustment with

digital input of 255.

B.C1 and C2 phase compensation capacitors (10pF to 15pF) are required when using high-speed amplifiers to prevent ringing or

oscillation.

Figure 3. Unipolar Operation (2-Quadrant Multiplication)

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SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008

TLC7528C, TLC7528E, TLC7528I

DUAL 8ĆBIT MULTIPLYING

DIGITALĆTOĆANALOG CONVERTERS

APPLICATION INFORMATION

I(A)

±10 V

20 kΩ

(see Note B)

(see Note A)

DB0

DB7

RFBA

R2 (see Note A)

(see Note C)

20 kΩ

−

Latch

DACA

RFBB

DGND

AGND

(see Note A)

R10

20 kΩ

(see Note B)

R11

5 kΩ

AGND

I(B)

±10 V

NOTES:A.R1, R2, R3, and R4 are used only if gain adjustment is required. See table in Figure 3 for recommended values. Adjust R1 for

= 0V with code 10000000 in DACA latch. Adjust R3 for V

= 0V with 10000000 in DACB latch.

ng and tracking are essential for resistor pairs R6, R7, R9, and R10.

C.C1 and C2 phase compensation capacitors (10pF to 15pF) may be required if A1 and A3 are high-speed amplifiers.

Figure 4. Bipolar Operation (4-Quadrant Operation)

Table 1. Unipolar Binary Code

DAC LATCH CONTENTS

MSBLSB

†

1 1 1 1 1 1 1 1

1 0 0 0 0 0 0 1

1 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1

0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0

†

1LSB = (2

−8

ANALOG OUTPUT

−V

(255/256)

−V

(129/256)

−V

(128/256) = −V

−V

(127/256)

−V

(1/256)

−V

(0/256) = 0

Table 2. Bipolar (Offset Binary) Code

DAC LATCH CONTENTS

MSBLSB

‡

1 1 1 1 1 1 1 1

1 0 0 0 0 0 0 1

1 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1

0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0

‡

1LSB = (2

−7

ANALOG OUTPUT

(127/128)

(1/128)

−V

(1/128)

−V

(127/128)

−V

(128/128)

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•

REFB

AGND

10 kΩ

(see Note B)

−

Latch

DACB

−

DACA/

DACB

R4 (see Note A)

(see Note C)

Control

Logic

OUTB

AGND

−

Input

Buffer

OUTA

10 kΩ

(see Note B)

R11

5 kΩ

20 kΩ

A4V

TLC7528C, TLC7528E, TLC7528I

DUAL 8ĆBIT MULTIPLYING

DIGITALĆTOĆANALOG CONVERTERS

SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008

APPLICATION INFORMATION

microprocessor interface information

A8−A15

Address Bus

DACA/DACB

Address

Decode

Logic

A + 1

DB0

DB7

ALE

Latch

AD0−AD7

Data Bus

TLC7528

CPU

8051

NOTE A:A = decoded address for TLC7528 DACA

A + 1 = decoded address for TLC7528 DACB

Figure 5. TLC7528: Intel 8051 Interface

A8−A15

Address Bus

DACA/DACB

VMA

CPU

6800

φ2

Address

Decode

Logic

A + 1

DB0

DB7

TLC7528

AD0−AD7

Data Bus

NOTE A:A = decoded address for TLC7528 DACA

A + 1 = decoded address for TLC7528 DACB

Figure 6. TLC7528: 6800 Interface

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TLC7528C, TLC7528E, TLC7528I

DUAL 8ĆBIT MULTIPLYING

DIGITALĆTOĆANALOG CONVERTERS

APPLICATION INFORMATION

A8−A15

Address Bus

DACA/DACB

IORQ

CPU

Z80-A

Address

Decode

Logic

A + 1

TLC7528

DB0

DB7

D0−D7

Data Bus

NOTE A:A = decoded address for TLC7528 DACA

A + 1 = decoded address for TLC7528 DACB

Figure 7. TLC7528 To Z-80A Interface

programmable window detector

The programmable window comparator shown in Figure 8 determines if the voltage applied to the DAC

feedback resistors is within the limits programmed into the data latches of these devices. Input signal range

depends on the reference and polarity; that is, the test input range is 0 to −V

ref

. The DACA and DACB data

latches are programmed with the upper and lower test limits. A signal within the programmed limits drives the

output high.

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TLC7528C, TLC7528E, TLC7528I

DUAL 8ĆBIT MULTIPLYING

DIGITALĆTOĆANALOG CONVERTERS

SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008

APPLICATION INFORMATION

Test Input

0 to −V

ref

RFBA

−

REFA

Data Inputs

14−7

DB0−DB7

TLC7528

DACA/DACB

OUTB

ref

REFB

DGND

RFBB

DACB

−

AGND

PASS/FAIL Output

OUTA

DACA

317

1 kΩ

Figure 8. Digitally-Programmable Window Comparator (Upper- and Lower-Limit Tester)

digitally-controlled signal attenuator

Figure 9 shows a TLC7528 configured as a two-channel programmable attenuator. Applications include stereo

audio and telephone signal level control. Table 3 shows input codes vs attenuation for a 0dB to 15.5dB range.

Attenuation dB = −20 log

D/256, D = digital input code

REFA

DACA

RFBA

OUTA

A1Output

DB0−DB7

TLC7528

OUTB

DACB

DACA/DACB

REFB

AGND

RFBB

DGND

14−7

Figure 9. Digitally Controlled Dual Telephone Attenuator

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Data Bus

SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008

TLC7528C, TLC7528E, TLC7528I

DUAL 8ĆBIT MULTIPLYING

DIGITALĆTOĆANALOG CONVERTERS

APPLICATION INFORMATION

Table 3. Attenuation vs DACA, DACB Code

ATTEN (dB)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

DAC INPUT CODE

1 1 1 1 1 1 1 1

1 1 1 1 0 0 1 0

1 1 1 0 0 1 0 0

1 1 0 1 0 1 1 1

1 1 0 0 1 0 1 1

1 1 0 0 0 0 0 0

1 0 1 1 0 1 0 1

1 0 1 0 1 0 1 1

1 0 1 0 0 0 1 0

1 0 0 1 1 0 0 0

1 0 0 1 1 1 1 1

1 0 0 0 1 0 0 0

1 0 0 0 0 0 0 0

0 1 1 1 1 0 0 1

0 1 1 1 0 0 1 0

0 1 1 0 1 1 0 0

CODE IN

DECIMAL

255

242

228

215

203

192

181

171

162

152

144

136

128

121

114

108

ATTN (dB)

8.0

8.5

9.0

9.5

10.0

10.5

11.0

11.5

12.0

12.5

13.0

13.5

14.0

14.5

15.0

15.5

DAC INPUT CODE

0 1 1 0 0 1 1 0

0 1 1 0 0 0 0 0

0 1 0 1 1 0 1 1

0 1 0 1 0 1 1 0

0 1 0 1 0 0 0 1

0 1 0 0 1 1 0 0

0 1 0 0 1 0 0 0

0 1 0 0 0 1 0 0

0 1 0 0 0 0 0 0

0 0 1 1 1 1 0 1

0 0 1 1 1 0 0 1

0 0 1 1 0 1 1 0

0 0 1 1 0 0 1 1

0 0 1 1 0 0 0 0

0 0 1 0 1 1 1 0

0 0 1 0 1 0 1 1

CODE IN

DECIMAL

102

programmable state-variable filter

This programmable state-variable or universal filter configuration provides low-pass, high-pass, and bandpass

outputs, and is suitable for applications requiring microprocessor control of filter parameters.

As shown in Figure 10, DACA1 and DACB1 control the gain and Q of the filter while DACA2 and DACB2 control

the cutoff frequency. Both halves of the DACA2 and DACB2 must track accurately in order for the

cutoff-frequency equation to be true. With the TLC7528, this validity is easy to achieve.

2pR1C1

The programmable range for the cutoff or center frequency is 0kHz to 15kHz with a Q ranging from 0.3 to 4.5.

This parameter defines the limits of the component values.

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TLC7528C, TLC7528E, TLC7528I

DUAL 8ĆBIT MULTIPLYING

DIGITALĆTOĆANALOG CONVERTERS

SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008

APPLICATION INFORMATION

47pF

TLC7528

DGND

DACA

/DACB

DACA1ANDDACB1

1000pF

DataIn

TLC7528

DGND

DACA/DACB

DACA2andDACB2

CircuitEquations:

DACB

)

REFA

DACA

)

OUTA

LowPassOut

DACB

)

REFA

DACA

)

OUTA

30k

Ω

10k

Ω

30k

Ω

HighPass

Out

RFBA

AGND

OUTB

RFBB

DataIn

REFB

BandpassOut

RFBA

AGND

OUTB

RFBB

1000pF

REFB

fb(DACB1)

Where:

RistheinternalresistorconnectedbetweenOUTBandRFBB

−

NOTES:-amps A1, A2, A3, and A4 are TL287.

compensates for the op-amp gain-bandwidth limitations.

256 (DACladderresistance)

equivalent resistance equals

DACdigitalcode

Figure 10. Digitally-Controlled State-Variable Filter

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

•

SLAS062E − JANUARY 1987 − REVISED NOVEMBER 2008

TLC7528C, TLC7528E, TLC7528I

DUAL 8ĆBIT MULTIPLYING

DIGITALĆTOĆANALOG CONVERTERS

APPLICATION INFORMATION

voltage-mode operation

It is possible to operate the current multiplying D/A converter of these devices in a voltage mode. In the voltage

mode, a fixed voltage is placed on the current output terminal. The analog output voltage is then available at

the reference voltage terminal. Figure 11 is an example of a current multiplying D/A that operates in the voltage

mode.

REF

(Analog Output Voltage)

RRR

2R2R2R2R

“0”“1”

Out (Fixed Input Voltage)

AGND

Figure 11. Voltage-Mode Operation

The following equation shows the relationship between the fixed input voltage and the analog output voltage:

= V

(D/256)

Where:

= analog output voltage

= fixed input voltage (must not be forced below 0V.)

D = digital input code converted to decimal

In voltage-mode operation, these devices meet the following specification:

PARAMETER

Linearity error at REFA or REFBV

= 5V,

TEST CONDITIONS

OUTA or OUTB at 2.5V,T

= +25°C

MINMAX

UNIT

LSB

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

•

Revision History

DATE

11/08

6/07

REV

PAGE

Front Page

SECTION

Application Information

—

Corrected Figure 10.

Deleted Available Options table.

Inserted Package/Ordering information.

DESCRIPTION

NOTE

Page numbers for previous revisions may differ from page numbers in the current version.

PACKAGEOPTIONADDENDUM

28-May-2009

PACKAGINGINFORMATION

OrderableDevice

TLC7528CDW

TLC7528CDWG4

TLC7528CDWR

TLC7528CDWRG4

TLC7528CFN

TLC7528CFNG3

TLC7528CFNR

TLC7528CFNRG3

TLC7528CN

TLC7528CNE4

TLC7528CNS

TLC7528CNSG4

TLC7528CNSR

TLC7528CNSRG4

TLC7528CPW

TLC7528CPWG4

TLC7528CPWR

TLC7528CPWRG4

TLC7528EDW

TLC7528EDWG4

TLC7528EDWR

TLC7528EDWRG4

TLC7528EN

TLC7528ENE4

TLC7528IDW

Status

(1)

ACTIVE

Package

Type

SOIC

PLCC

PDIP

TSSOP

SOIC

PDIP

SOIC

Package

Drawing

PinsPackageEcoPlan

(2)

Qty

Green(RoHS&

noSb/Br)

Green(RoHS&

noSb/Br)

Lead/BallFinish

CUNIPDAU

CUSN

CUNIPDAU

MSLPeakTemp

(3)

Level-1-260C-UNLIM

N/AforPkgType

Level-1-260C-UNLIM

N/AforPkgType

Level-1-260C-UNLIM

2000Green(RoHS&

noSb/Br)

2000Green(RoHS&

noSb/Br)

Green(RoHS&

noSb/Br)

Green(RoHS&

noSb/Br)

1000Green(RoHS&

noSb/Br)

1000Green(RoHS&

noSb/Br)

Pb-Free

(RoHS)

Pb-Free

(RoHS)

Green(RoHS&

noSb/Br)

Green(RoHS&

noSb/Br)

2000Green(RoHS&

noSb/Br)

2000Green(RoHS&

noSb/Br)

Green(RoHS&

noSb/Br)

Green(RoHS&

noSb/Br)

2000Green(RoHS&

noSb/Br)

2000Green(RoHS&

noSb/Br)

Green(RoHS&

noSb/Br)

Green(RoHS&

noSb/Br)

2000Green(RoHS&

noSb/Br)

2000Green(RoHS&

noSb/Br)

Pb-Free

(RoHS)

Pb-Free

(RoHS)

Green(RoHS&

noSb/Br)

Addendum-Page1

PACKAGEOPTIONADDENDUM

28-May-2009

OrderableDevice

TLC7528IDWG4

TLC7528IDWR

TLC7528IDWRG4

TLC7528IFN

TLC7528IFNG3

TLC7528IN

TLC7528INE4

TLC7528IPW

TLC7528IPWG4

TLC7528IPWR

TLC7528IPWRG4

(1)

Status

(1)

ACTIVE

Package

Type

SOIC

PLCC

PDIP

TSSOP

Package

Drawing

PinsPackageEcoPlan

(2)

Qty

25Green(RoHS&

noSb/Br)

Lead/BallFinish

CUNIPDAU

CUSN

CUNIPDAU

MSLPeakTemp

(3)

Level-1-260C-UNLIM

N/AforPkgType

Level-1-260C-UNLIM

2000Green(RoHS&

noSb/Br)

2000Green(RoHS&

noSb/Br)

Green(RoHS&

noSb/Br)

Green(RoHS&

noSb/Br)

Pb-Free

(RoHS)

Pb-Free

(RoHS)

Green(RoHS&

noSb/Br)

Green(RoHS&

noSb/Br)

2000Green(RoHS&

noSb/Br)

2000Green(RoHS&

noSb/Br)

Themarketingstatusvaluesaredefinedasfollows:

ACTIVE:Productdevicerecommendedfornewdesigns.

LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect.

NRND:isinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartin

anewdesign.

PREVIEW:smayormaynotbeavailable.

OBSOLETE:TIhasdiscontinuedtheproductionofthedevice.

(2)

EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheck

/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails.

TBD:ThePb-Free/Greenconversionplanhasnotbeendefined.

Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirements

forall6substances,includingtherequirementthatleadnotexceed0.1%esignedtobesoldered

athightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses.

Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieand

package,or2)ponentisotherwiseconsideredPb-Free(RoHS

compatible)asdefinedabove.

Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflame

retardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial)

(3)

MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksolder

temperature.

ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitis

sitsknowledgeandbeliefoninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastothe

akenandcontinuestotake

reasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysison

Isuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimited

informationmaynotbeavailableforrelease.

InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTI

toCustomeronanannualbasis.

Addendum-Page2

PACKAGEMATERIALSINFORMATION

9-Apr-2009

TAPEANDREELINFORMATION

*Alldimensionsarenominal

DevicePackagePackagePins

TypeDrawing

TSSOP

SPQReelReel

DiameterWidth

(mm)W1(mm)

330.0

24.4

16.4

A0(mm)B0(mm)K0(mm)P1

(mm)

12.0

8.0

WPin1

(mm)Quadrant

24.0

16.0

TLC7528CNSR

TLC7528CPWR

TLC7528IPWR

2000

8.2

6.95

13.0

7.1

2.5

1.6

PackMaterials-Page1

PACKAGEMATERIALSINFORMATION

9-Apr-2009

*Alldimensionsarenominal

Device

TLC7528CNSR

TLC7528CPWR

TLC7528IPWR

PackageType

TSSOP

PackageDrawing

Pins

SPQ

2000

Length(mm)

346.0

Width(mm)

346.0

Height(mm)

41.0

33.0

PackMaterials-Page2

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

MECHANICAL DATA

PW (R-PDSO-G**)

14 PINS SHOWN

PLASTIC SMALL-OUTLINE PACKAGE

0,65

148

0,30

0,19

0,10

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

0°–8°

0,75

0,50

Seating Plane

1,20 MAX

0,15

0,05

0,10

PINS **

DIM

A MAX

3,10

5,10

6,60

7,90

9,80

A MIN

2,90

4,90

6,40

7,70

9,60

4040064/F 01/97

NOTES:A.

All linear dimensions are in millimeters.

This drawing is subject to change without notice.

Body dimensions do not include mold flash or protrusion not to exceed 0,15.

Falls within JEDEC MO-153

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

•

MECHANICAL DATA

MPLC004A – OCTOBER 1994

FN (S-PQCC-J**)

20 PIN SHOWN

PLASTIC J-LEADED CHIP CARRIER

Seating Plane

0.004 (0,10)

3119

0.032 (0,81)

0.026 (0,66)

418

D2/E2

0.180 (4,57) MAX

0.120 (3,05)

0.090 (2,29)

0.020 (0,51) MIN

EE1

D2/E2

814

913

0.050 (1,27)

0.008 (0,20) NOM

0.021 (0,53)

0.013 (0,33)

0.007 (0,18)

NO. OF

PINS

D/E

MIN

0.385 (9,78)

0.485 (12,32)

0.685 (17,40)

0.785 (19,94)

0.985 (25,02)

1.185 (30,10)

MAX

0.395 (10,03)

0.495 (12,57)

0.695 (17,65)

0.795 (20,19)

0.995 (25,27)

1.195 (30,35)

MIN

D1/E1

MAX

0.356 (9,04)

0.456 (11,58)

0.656 (16,66)

0.756 (19,20)

0.958 (24,33)

1.158 (29,41)

MIN

D2/E2

MAX

0.169 (4,29)

0.219 (5,56)

0.319 (8,10)

0.369 (9,37)

0.469 (11,91)

0.569 (14,45)

4040005/B 03/95

0.350 (8,89)

0.450 (11,43)

0.650 (16,51)

0.750 (19,05)

0.950 (24,13)

1.150 (29,21)

0.141 (3,58)

0.191 (4,85)

0.291 (7,39)

0.341 (8,66)

0.441 (11,20)

0.541 (13,74)

NOTES: linear dimensions are in inches (millimeters).

drawing is subject to change without notice.

within JEDEC MS-018

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

•

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