2024年3月14日发(作者：蹉新柔)
元器件交易网
a
CMOS, 330 MHz
Triple 10-Bit High Speed Video DAC
FEATURES
330 MSPS Throughput Rate
Triple 10-Bit D/A Converters
SFDR
–70 dB at f
CLK
= 50 MHz; f
OUT
= 1 MHz
–53 dB at f
CLK
= 140 MHz; f
OUT
= 40 MHz
RS-343A/RS-170 Compatible Output
Complementary Outputs
DAC Output Current Range 2 mA to 26 mA
TTL Compatible Inputs
Internal Reference (1.23 V)
Single-Supply 5 V/3.3 V Operation
48-Lead LQFP Package
Low Power Dissipation (30 mW Min @ 3 V)
Low Power Standby Mode (6 mW Typ @ 3 V)
Industrial Temperature Range (–40؇C to +85؇C)
APPLICATIONS
Digital Video Systems (1600 ؋ 1200 @ 100 Hz)
High Resolution Color Graphics
Digital Radio Modulation
Image Processing
Instrumentation
Video Signal Reconstruction
GENERAL DESCRIPTION
The ADV7123 (ADV
®
) is a triple high speed, digital-to-analog
converter on a single monolithic chip. It consists of three
high speed, 10-bit, video D/A converters with complementary
outputs, a standard TTL input interface, and a high impedance,
analog output current source.
The ADV7123 has three separate 10-bit-wide input ports. A
single 5 V/3.3 V power supply and clock are all that are required
to make the part functional. The ADV7123 has additional video
control signals, composite SYNC and BLANK.
The ADV7123 also has a Power-Save Mode.
The ADV7123 is fabricated in a 5 V CMOS process. Its mono-
lithic CMOS construction ensures greater functionality with
lower power dissipation. The ADV7123 is available in a
48-lead LQFP package.
ADV is a registered trademark of Analog Devices, Inc.
REV.B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
ADV7123
FUNCTIONAL BLOCK DIAGRAM
V
AA
BLANK
BLANK AND
SYNC
SYNC LOGIC
R9–R0
DATA
IOR
10
REGISTER
10DAC
IOR
G9–G0
DATA
10DAC
IOG
10
REGISTER
IOG
B9–B0
10
DATA
10DAC
IOB
REGISTER
IOB
PSAVE
POWER-DOWN
VOLTAGE
MODE
REFERENCE
V
CIRCUIT
REF
CLOCK
ADV7123
GND
R
SET
COMP
PRODUCT HIGHLIGHTS
1.330 MSPS throughput
teed monotonic to 10 bits
ible with a wide variety of high resolution color
graphics systems, including RS-343A and RS-170
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/
Fax: 781/326-8703© Analog Devices, Inc., 2002
元器件交易网
ADV7123–SPECIFICATIONS
5 V SPECIFICATIONS
Parameter
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity (BSL)
Differential Nonlinearity
DIGITAL AND CONTROL INPUTS
Input High Voltage, V
IH
Input Low Voltage, V
IL
Input Current, I
IN
PSAVE Pull-Up Current
Input Capacitance, C
IN
ANALOG OUTPUTS
Output Current
DAC to DAC Matching
Output Compliance Range, V
OC
Output Impedance, R
OUT
Output Capacitance, C
OUT
Offset Error
Gain Error
2
VOLTAGE REFERENCE (Ext. and Int.)
Reference Range, V
REF
POWER DISSIPATION
Digital Supply Current
3
Analog Supply Current
Standby Supply Current
4
Power Supply Rejection Ratio
(V
AA
= 5 V ؎ 5%, V
REF
= 1.235 V, R
SET
= 560 ⍀, C
L
= 10 pF. All specifications T
MIN
to T
MAX
1
, unless other-
wise noted, T
J
MAX
= 110؇C.)
Min
10
–1
–1
2
–1
20
10
2.0
2.0
1.0
0
100
10
–0.025
–5.0
1.12 1.235
3.4
10.5
18
67
8
2.1
0.1
+0.025
+5.0
1.35
9
15
25
72
5.0
0.5
26.5
18.5
5
1.4
0.8
+1
TypMaxUnit
Bits
LSB
LSB
V
V
µA
µA
pF
mA
mA
%
V
kΩ
pF
% FSR
% FSR
V
mA
mA
mA
mA
mA
mA
%/%
f
CLK
= 50 MHz
f
CLK
= 140 MHz
f
CLK
= 240 MHz
R
SET
= 560 Ω
R
SET
= 4933 Ω
PSAVE = Low, Digital, and Control
Inputs at V
DD
Test Conditions
1
±0.4
±0.25
+1
+1Guaranteed Monotonic
V
IN
= 0.0 V or V
DD
Green DAC, Sync = High
RGB DAC, Sync = Low
I
OUT
= 0 mA
Tested with DAC Output = 0 V
FSR = 17.62 mA
NOTES
1
Temperature range T
MIN
to T
MAX
: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
2
Gain error = {(Measured (FSC)/Ideal (FSC) –1) × 100}, where Ideal = V
REF
/R
SET
× K × (3FFH) and K = 7.9896.
3
Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V
DD
.
4
These maximum/minimum specifications are guaranteed by characterization to be over the 4.75 V to 5.25 V range.
Specifications subject to change without notice.
–2–
REV. B
2024年3月14日发(作者：蹉新柔)
元器件交易网
a
CMOS, 330 MHz
Triple 10-Bit High Speed Video DAC
FEATURES
330 MSPS Throughput Rate
Triple 10-Bit D/A Converters
SFDR
–70 dB at f
CLK
= 50 MHz; f
OUT
= 1 MHz
–53 dB at f
CLK
= 140 MHz; f
OUT
= 40 MHz
RS-343A/RS-170 Compatible Output
Complementary Outputs
DAC Output Current Range 2 mA to 26 mA
TTL Compatible Inputs
Internal Reference (1.23 V)
Single-Supply 5 V/3.3 V Operation
48-Lead LQFP Package
Low Power Dissipation (30 mW Min @ 3 V)
Low Power Standby Mode (6 mW Typ @ 3 V)
Industrial Temperature Range (–40؇C to +85؇C)
APPLICATIONS
Digital Video Systems (1600 ؋ 1200 @ 100 Hz)
High Resolution Color Graphics
Digital Radio Modulation
Image Processing
Instrumentation
Video Signal Reconstruction
GENERAL DESCRIPTION
The ADV7123 (ADV
®
) is a triple high speed, digital-to-analog
converter on a single monolithic chip. It consists of three
high speed, 10-bit, video D/A converters with complementary
outputs, a standard TTL input interface, and a high impedance,
analog output current source.
The ADV7123 has three separate 10-bit-wide input ports. A
single 5 V/3.3 V power supply and clock are all that are required
to make the part functional. The ADV7123 has additional video
control signals, composite SYNC and BLANK.
The ADV7123 also has a Power-Save Mode.
The ADV7123 is fabricated in a 5 V CMOS process. Its mono-
lithic CMOS construction ensures greater functionality with
lower power dissipation. The ADV7123 is available in a
48-lead LQFP package.
ADV is a registered trademark of Analog Devices, Inc.
REV.B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
ADV7123
FUNCTIONAL BLOCK DIAGRAM
V
AA
BLANK
BLANK AND
SYNC
SYNC LOGIC
R9–R0
DATA
IOR
10
REGISTER
10DAC
IOR
G9–G0
DATA
10DAC
IOG
10
REGISTER
IOG
B9–B0
10
DATA
10DAC
IOB
REGISTER
IOB
PSAVE
POWER-DOWN
VOLTAGE
MODE
REFERENCE
V
CIRCUIT
REF
CLOCK
ADV7123
GND
R
SET
COMP
PRODUCT HIGHLIGHTS
1.330 MSPS throughput
teed monotonic to 10 bits
ible with a wide variety of high resolution color
graphics systems, including RS-343A and RS-170
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/
Fax: 781/326-8703© Analog Devices, Inc., 2002
元器件交易网
ADV7123–SPECIFICATIONS
5 V SPECIFICATIONS
Parameter
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity (BSL)
Differential Nonlinearity
DIGITAL AND CONTROL INPUTS
Input High Voltage, V
IH
Input Low Voltage, V
IL
Input Current, I
IN
PSAVE Pull-Up Current
Input Capacitance, C
IN
ANALOG OUTPUTS
Output Current
DAC to DAC Matching
Output Compliance Range, V
OC
Output Impedance, R
OUT
Output Capacitance, C
OUT
Offset Error
Gain Error
2
VOLTAGE REFERENCE (Ext. and Int.)
Reference Range, V
REF
POWER DISSIPATION
Digital Supply Current
3
Analog Supply Current
Standby Supply Current
4
Power Supply Rejection Ratio
(V
AA
= 5 V ؎ 5%, V
REF
= 1.235 V, R
SET
= 560 ⍀, C
L
= 10 pF. All specifications T
MIN
to T
MAX
1
, unless other-
wise noted, T
J
MAX
= 110؇C.)
Min
10
–1
–1
2
–1
20
10
2.0
2.0
1.0
0
100
10
–0.025
–5.0
1.12 1.235
3.4
10.5
18
67
8
2.1
0.1
+0.025
+5.0
1.35
9
15
25
72
5.0
0.5
26.5
18.5
5
1.4
0.8
+1
TypMaxUnit
Bits
LSB
LSB
V
V
µA
µA
pF
mA
mA
%
V
kΩ
pF
% FSR
% FSR
V
mA
mA
mA
mA
mA
mA
%/%
f
CLK
= 50 MHz
f
CLK
= 140 MHz
f
CLK
= 240 MHz
R
SET
= 560 Ω
R
SET
= 4933 Ω
PSAVE = Low, Digital, and Control
Inputs at V
DD
Test Conditions
1
±0.4
±0.25
+1
+1Guaranteed Monotonic
V
IN
= 0.0 V or V
DD
Green DAC, Sync = High
RGB DAC, Sync = Low
I
OUT
= 0 mA
Tested with DAC Output = 0 V
FSR = 17.62 mA
NOTES
1
Temperature range T
MIN
to T
MAX
: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
2
Gain error = {(Measured (FSC)/Ideal (FSC) –1) × 100}, where Ideal = V
REF
/R
SET
× K × (3FFH) and K = 7.9896.
3
Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V
DD
.
4
These maximum/minimum specifications are guaranteed by characterization to be over the 4.75 V to 5.25 V range.
Specifications subject to change without notice.
–2–
REV. B