2024年3月22日发(作者：卯访烟)

Introduction

Chapter6

Implementing FPGA Designs

Introduction

After you have successfully simulated your design, the synthesis stage converts the code-

based HDL or schematic-based design into an NGC netlist file. The netlist is a non-

readable file that describes the actual circuit to be implemented at a very low level. The

implementation phase uses the netlist and a constraints file to recreate the design using the

available resources within the FPGA. Constraints may be physical or timing and are

commonly used for setting the required frequency of the design or declaring the required

pin-out.

The map stage distributes the design to the resources available in the FPGA. Obviously, if

the design is too big for the specified device, mapping will be incomplete. The map stage

also uses the UCF file to understand timing and may sometimes decide to add further logic

(replication) to meet the given timing requirements. Map has the ability to “shuffle’ the

design around LUTs to create the best possible implementation for the design. The whole

process is automatic and requires little user input.

The place and route stage works with the allocated CLBs and chooses the best location for

each block. For a fast logic path, it makes sense to place relevant CLBs next to each other

simply to minimize the path length. The routing resources are then allocated to each

connection, again using a careful selection of the best possible routing types. For example,

if you need a signal for many areas of the design, the place and route tool would use a

“longline” to span the chip with minimal delay or skew.

At this point, it is good practice to re-simulate. As all of the logic delays added by the LUTs

and flip-flops are now known (as well as the routing delays), the chosen simulator can use

this information for timing simulation.

Finally, a program called “bitgen” takes the output of place and route and creates a

programming bitstream. When developing a design, it may not be necessary to create a bit

file on every implementation, as you may only need to ensure that a particular portion of

your design passes timing verification. The steps of implementation must be carried out in

this order:

1.

2.

3.

4.

5.

Synthesize

Map

Place and Route

Timing Simulate

Program.

WebPACK ISE software will automatically perform the steps required if a particular step is

selected. For example, if the design has only just been functionally simulated and you

decide to do a timing simulation, the software will automatically synthesize and fit. It will

Programmable Logic Design

May 8, 2008

2024年3月22日发(作者：卯访烟)

Introduction

Chapter6

Implementing FPGA Designs

Introduction

After you have successfully simulated your design, the synthesis stage converts the code-

based HDL or schematic-based design into an NGC netlist file. The netlist is a non-

readable file that describes the actual circuit to be implemented at a very low level. The

implementation phase uses the netlist and a constraints file to recreate the design using the

available resources within the FPGA. Constraints may be physical or timing and are

commonly used for setting the required frequency of the design or declaring the required

pin-out.

The map stage distributes the design to the resources available in the FPGA. Obviously, if

the design is too big for the specified device, mapping will be incomplete. The map stage

also uses the UCF file to understand timing and may sometimes decide to add further logic

(replication) to meet the given timing requirements. Map has the ability to “shuffle’ the

design around LUTs to create the best possible implementation for the design. The whole

process is automatic and requires little user input.

The place and route stage works with the allocated CLBs and chooses the best location for

each block. For a fast logic path, it makes sense to place relevant CLBs next to each other

simply to minimize the path length. The routing resources are then allocated to each

connection, again using a careful selection of the best possible routing types. For example,

if you need a signal for many areas of the design, the place and route tool would use a

“longline” to span the chip with minimal delay or skew.

At this point, it is good practice to re-simulate. As all of the logic delays added by the LUTs

and flip-flops are now known (as well as the routing delays), the chosen simulator can use

this information for timing simulation.

Finally, a program called “bitgen” takes the output of place and route and creates a

programming bitstream. When developing a design, it may not be necessary to create a bit

file on every implementation, as you may only need to ensure that a particular portion of

your design passes timing verification. The steps of implementation must be carried out in

this order:

1.

2.

3.

4.

5.

Synthesize

Map

Place and Route

Timing Simulate

Program.

WebPACK ISE software will automatically perform the steps required if a particular step is

selected. For example, if the design has only just been functionally simulated and you

decide to do a timing simulation, the software will automatically synthesize and fit. It will

Programmable Logic Design

May 8, 2008